CN111785731A - Three-dimensional memory, preparation method and electronic equipment - Google Patents
Three-dimensional memory, preparation method and electronic equipment Download PDFInfo
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- CN111785731A CN111785731A CN202010563701.1A CN202010563701A CN111785731A CN 111785731 A CN111785731 A CN 111785731A CN 202010563701 A CN202010563701 A CN 202010563701A CN 111785731 A CN111785731 A CN 111785731A
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- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
- H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
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- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
- H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
- H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
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Abstract
The application provides a three-dimensional memory, a preparation method and electronic equipment. The preparation method comprises the steps of providing a substrate and forming a sacrificial layer covering the substrate. A first protective layer is formed overlying the sacrificial layer. A stacked structure covering the first protective layer is formed. A NAND string is formed through the stacked structure, the first protection layer, and the sacrificial layer, the NAND string including a channel layer and a memory layer disposed at a periphery of the channel layer. And forming a gate gap penetrating through the laminated structure and the first protection layer. The sacrificial layer is removed to form a void. And removing part of the memory layer in the gap to expose the channel layer. A first layer of semiconductor material is formed within the void. After a first protective layer covering the sacrificial layer is formed, a laminated structure covering the first protective layer is formed. Therefore, the first protective layer can be used for preventing the insulating layer from being consumed when the memory layer is removed subsequently, the uniformity of the thickness of the insulating layer is ensured, the stability of the electrical performance of the bottom selection grid is improved, and the quality of the three-dimensional memory is improved.
Description
Technical Field
The application belongs to the technical field of electronic products, and particularly relates to a three-dimensional memory, a preparation method and electronic equipment.
Background
The three-dimensional memory has low power consumption, light weight and belongs to a nonvolatile memory product with excellent performance, and the three-dimensional memory is more and more widely applied to electronic products. But at the same time, the expectation and the demand of users for three-dimensional memories are also higher and higher. For example, as the number of layers of a three-dimensional memory increases, a semiconductor material layer is usually added between a substrate and a stacked structure to reduce the difficulty of etching a NAND string during plug formation. The general preparation method comprises the following steps: the method comprises the steps of sequentially stacking and depositing a sacrificial layer and a stacked structure on a substrate, forming a NAND string and a gate gap, and removing the sacrificial layer to form a gap. The memory layer surrounding the NAND string within the void is then removed to expose the channel layer. And ventilating the gate gap to form a semiconductor material layer in the gap. However, the memory layer is removed poorly during the process of removing the memory layer, the insulating layer may be excessively etched, or the memory layer at the edge region may not be completely etched. Therefore, the uniformity of the thickness of the bottom insulating layer cannot be effectively controlled, the stability of the electrical performance of the bottom selection grid is influenced, and the quality of the three-dimensional memory is influenced.
Disclosure of Invention
In view of this, the first aspect of the present application provides a method for manufacturing a three-dimensional memory, the method comprising:
providing a substrate, and forming a sacrificial layer covering the substrate;
forming a first protective layer covering the sacrificial layer;
forming a laminated structure covering the first protective layer;
forming a NAND string through the stacked structure, the first protective layer, and the sacrificial layer, the NAND string including a channel layer and a memory layer disposed at a periphery of the channel layer;
forming a gate gap penetrating through the laminated structure and the first protective layer;
removing the sacrificial layer to form a void;
removing a portion of the memory layer located within the void to expose the channel layer;
a first layer of semiconductor material is formed within the void.
In the manufacturing method provided by the first aspect of the present application, after the first protection layer covering the sacrificial layer is formed, the stacked structure covering the first protection layer is formed, and then the NAND string is formed. Therefore, the first protective layer can be used for preventing the insulating layer from being consumed when the memory layer is removed subsequently, the uniformity of the thickness of the insulating layer is ensured, the insulating layer is prevented from being etched through, the stability of the electrical property of the bottom selection grid electrode is improved, and the quality of the three-dimensional memory is improved.
Wherein forming a NAND string through the stack structure, the first protective layer, and the sacrificial layer comprises:
forming a channel hole penetrating through the laminated structure and the sacrificial layer; the channel hole has a protruding region located within the sacrificial layer, the protruding region protruding in a radial direction;
a NAND string is formed within the channel hole.
Before the step of forming the first semiconductor material layer in the gap, the method further includes:
removing at least a portion of the first protective layer.
Wherein providing a substrate and forming a sacrificial layer overlying the substrate comprises:
providing a substrate, wherein a groove is formed in the substrate;
and forming a sacrificial layer covering the substrate and the groove.
Wherein "forming a gate gap through the stacked structure and the first protective layer" includes:
and forming a gate gap penetrating through the laminated structure and the first protective layer, so that the orthographic projection of the gate gap on the substrate is positioned in the groove.
Wherein, after the step of forming the first semiconductor material layer in the gap, the method further comprises:
removing a portion of the first semiconductor material layer in the void and a portion of the first semiconductor material layer in the recess;
forming a second layer of semiconductor material on the first layer of semiconductor material within the recess and within the void.
Wherein forming a second layer of semiconductor material over the first layer of semiconductor material within the recess and within the void comprises:
and forming a second semiconductor material layer on the first semiconductor material layer in the groove and the gap, and enabling the surface of one side, close to the substrate, of the laminated structure to be flush with the surface of one side, away from the substrate, of the second semiconductor material layer.
Wherein providing a substrate and forming a sacrificial layer overlying the substrate comprises:
providing a substrate;
forming a second protective layer covering the substrate;
and forming a sacrificial layer covering the second protective layer.
Wherein, after "forming a gate gap penetrating the stacked structure and the first protective layer", the method further comprises:
forming a third protective layer covering the side wall of the gate gap; the third protective layer comprises a first sub protective layer, a second sub protective layer, a third sub protective layer and a fourth sub protective layer which are sequentially arranged along the direction far away from the side wall of the gate gap in a stacking mode.
Wherein before "removing the sacrificial layer to form a void", the method further comprises:
and removing at least part of the third protective layer close to one side of the sacrificial layer to expose the sacrificial layer.
The memory layer comprises a tunneling layer, a memory layer and a blocking layer which are sequentially arranged in a stacking mode along the direction far away from the channel layer; after "removing the sacrificial layer to form a void", further comprising:
and removing the second protective layer and the barrier layer.
Wherein "removing a portion of the memory layer located within the void" comprises:
removing the fourth sub-protection layer;
removing the third sub-protection layer and part of the storage layer;
and removing part of the tunneling layer to expose the channel layer, and removing part of the second sub-protection layer.
A second aspect of the present application provides a three-dimensional memory, comprising:
a substrate;
a first layer of semiconductor material disposed on the substrate;
a stack structure disposed on the first semiconductor material layer;
a NAND string extending through the stack structure and the layers of semiconductor material;
the NAND string has a protrusion within the first layer of semiconductor material, the protrusion protruding in a radial direction.
The three-dimensional memory provided by the second aspect of the present application, by having the NAND string have a protrusion within the first layer of semiconductor material, the protrusion protrudes radially. It can also be understood that making the width of the NAND string across the stack smaller than the width of the NAND string across the first semiconductor material layer makes the memory layer in an "L" shape even if the width of the NAND string at the first semiconductor material layer is wider, which makes the memory layer occupy the edge area of the first semiconductor material layer, which makes it possible to better remove the memory layer during the manufacturing process, thereby controlling the thickness of the bottom insulating layer and greatly improving the stability of the threshold voltage of the bottom select gate. In addition, since the uniformity of the thickness of the bottom insulating layer can be controlled, this also keeps the furthest distance of the bottom select gate from the channel layer in the NAND string fixed, thereby further improving the stability of the bottom select gate current.
Wherein a first protective layer is sandwiched between the protruding portion of the NAND string and the stack structure.
Wherein, still include: a second layer of semiconductor material passing through the first layer of semiconductor material and the substrate.
Wherein the three-dimensional memory further comprises an array common source electrode throughout the stack structure, the array common source electrode connecting the second semiconductor material layer.
Wherein an orthographic projection of the array common source on the substrate is located within the second layer of semiconductor material.
A third aspect of the present application provides an electronic device comprising a three-dimensional memory as provided in the second aspect of the present application and a processor for writing data into the three-dimensional memory and reading data from the three-dimensional memory.
According to the electronic device provided by the third aspect of the present application, by using the three-dimensional memory provided by the second aspect of the present application, the stability of the electrical performance of the three-dimensional memory and the electronic device can be improved, and the quality of the electronic device can be improved.
Drawings
In order to more clearly explain the technical solution in the embodiments of the present application, the drawings that are required to be used in the embodiments of the present application will be described below.
Fig. 1 is a process flow diagram of a method for manufacturing a three-dimensional memory according to an embodiment of the present disclosure.
Fig. 2 to 9 are schematic structural diagrams corresponding to S100, S200, S300, S400, S500, S600, S700, and S800 in fig. 1, respectively.
Fig. 10 is a process flow diagram of a method for fabricating a three-dimensional memory according to another embodiment of the present disclosure.
Fig. 11-12 are schematic structural diagrams corresponding to S410 and S420 in fig. 10, respectively.
Fig. 13 is a process flow diagram of a method for fabricating a three-dimensional memory according to yet another embodiment of the present application.
Fig. 14 is a schematic structural diagram corresponding to S710 in fig. 13.
Fig. 15 is a process flow diagram of a method for fabricating a three-dimensional memory according to yet another embodiment of the present application.
Fig. 16-17 are schematic structural diagrams corresponding to S110 and S120 in fig. 15, respectively.
Fig. 18 is a process flow diagram of a method for fabricating a three-dimensional memory according to yet another embodiment of the present application.
Fig. 19 is a schematic structural diagram corresponding to S510 in fig. 18.
Fig. 20 is a process flow diagram of a method for fabricating a three-dimensional memory according to yet another embodiment of the present application.
Fig. 21 is a process flow diagram of a method for fabricating a three-dimensional memory according to yet another embodiment of the present application.
Fig. 22-23 are schematic structural diagrams corresponding to S810 and S820 in fig. 21, respectively.
Fig. 24 is a process flow diagram of a method for fabricating a three-dimensional memory according to yet another embodiment of the present application.
Fig. 25 is a schematic structural diagram corresponding to S830 in fig. 24.
Fig. 26 is a process flow diagram of a method for fabricating a three-dimensional memory according to yet another embodiment of the present application.
Fig. 27-29 are schematic structural diagrams corresponding to S130, S140, and S150 in fig. 26, respectively.
Fig. 30 is a process flow diagram of a method for fabricating a three-dimensional memory according to yet another embodiment of the present application.
Fig. 31 is a schematic structural diagram corresponding to S430 in fig. 30.
Fig. 32 is a process flow diagram of a method for fabricating a three-dimensional memory according to yet another embodiment of the present application.
Fig. 33 is a schematic structural diagram corresponding to S440 in fig. 32.
Fig. 34 is a process flow diagram of a method for fabricating a three-dimensional memory according to yet another embodiment of the present application.
Fig. 35 is a schematic structural diagram corresponding to S530 in fig. 34.
Fig. 36 is a process flow diagram of a method for fabricating a three-dimensional memory according to yet another embodiment of the present application.
Fig. 37-39 are schematic structural diagrams corresponding to S610, S620, and S630 in fig. 36, respectively.
Fig. 40 is a schematic structural diagram of a three-dimensional memory according to an embodiment of the present application.
Fig. 41 is a schematic structural diagram of a three-dimensional memory according to another embodiment of the present application.
Fig. 42 is a schematic structural diagram of a three-dimensional memory according to yet another embodiment of the present application.
Description of reference numerals:
three-dimensional memory-1, substrate-10, forming surface-11, recess-12, pocket-13, sacrificial layer-20, void-21, stacked structure-30, stacked pair-31, insulating layer-32, replacement layer-33, gate layer-34, NAND string-40, protrusion-400, fill layer-41, channel layer-42, memory layer-43, gate gap-44, trench hole-45, protrusion region-450, tunneling layer-46, memory layer-47, barrier layer-48, array common source-49, semiconductor material layer-50, first semiconductor material layer-51, second semiconductor material layer-52, third protective layer-60, first sub-protective layer-61, second sub-protective layer-62, a third sub-passivation layer-63, a fourth sub-passivation layer-64, a stack structure-70, a second passivation layer-80, and a first passivation layer-81.
Detailed Description
The following is a preferred embodiment of the present application, and it should be noted that, for those skilled in the art, several improvements and modifications can be made without departing from the principle of the present application, and these improvements and modifications are also considered as the protection scope of the present application.
Before the technical scheme of the application is introduced, the background problem in the related art is further described in detail.
At present, the number of layers of the three-dimensional memory is more and more, that is, the number of stacked pairs is more and more, which leads to the height of the three-dimensional memory being more and more, which leads to the height of the NAND string being more and more, thus making the fabrication of the NAND string more and more difficult, especially the fabrication of the plug structure at the bottom of the NAND string being more and more difficult. Therefore, at present, a semiconductor material layer is usually formed between the substrate and the stacked structure, i.e., a whole layer of semiconductor material layer is disposed to replace the plug, thereby reducing the manufacturing difficulty. The general preparation method comprises the following steps: the method comprises the steps of sequentially stacking and depositing a sacrificial layer and a stacked structure on a substrate, forming a NAND string and a gate gap, and removing the sacrificial layer to form a gap. The memory layer surrounding the NAND string within the void is then removed to expose the channel layer. And ventilating the gate gap to form a semiconductor material layer in the gap. The replacement layer in the stacked structure is subsequently replaced by a replacement-layer gate layer, and the gate layer closest to the substrate may serve as a Bottom Select Gate (BSG).
In order to improve the electrical performance of the bottom select gate, the thickness of the insulating layer between the bottom select gate and the substrate is usually made as thin as possible. However, when the memory layer is removed, the etching may be over-etched, so that the bottom select gate is exposed, and the stability of the electrical performance of the bottom select gate is affected. In addition, the memory layer at the edge of the gap may not be cleaned, so that the thickness of the insulating layer may be increased, which also affects the stability of the electrical performance of the bottom select gate. All of which affect the quality of the three-dimensional memory.
In order to solve the above problems, the present application provides a method for manufacturing a three-dimensional memory. Please refer to fig. 1-9. Fig. 1 is a process flow diagram of a method for manufacturing a three-dimensional memory according to an embodiment of the present disclosure. Fig. 2 to 9 are schematic structural diagrams corresponding to S100, S200, S300, S400, S500, S600, S700, and S800 in fig. 1, respectively. The application provides a preparation method of a three-dimensional memory 1, which comprises S100, S200, S300, S400, S500, S600, S700 and S800. The details of S100, S200, S300, S400, S500, S600, S700, and S800 are as follows.
Referring to fig. 2, S100, a substrate 10 is provided, and a sacrificial layer 20 is formed to cover the substrate 10.
The sacrificial layer 20 may be formed on one side of the substrate 10, wherein the sacrificial layer 20 plays a role of supporting other structures to be subsequently prepared, and the sacrificial layer 20 is subsequently replaced by the semiconductor material layer 50, so that a preparation space of the semiconductor material layer 50 is reserved in advance. Alternatively, the substrate 10 may include a Silicon substrate 10, a Germanium substrate 10, a Silicon On Insulator (SOI) substrate 10, or a Germanium On Insulator (GOI) substrate 10, etc. Optionally, the material of the sacrificial layer 20 includes polysilicon.
Referring to fig. 3, S200, a first protection layer 81 covering the sacrificial layer 20 is formed.
The first protection layer 81 can be formed on the sacrificial layer 20 first, so as to provide a good foundation for the subsequent protection insulating layer 32.
Referring to fig. 4, S300, a stacked structure 30 covering the first protection layer 81 is formed.
Subsequently, the laminated structure 30 is continuously prepared on the first protective layer 81. Optionally, the stacked structure 30 includes one or more stacked pairs 31, wherein each stacked pair 31 includes an insulating layer 32 and a replacement layer 33, and the material of the insulating layer 32 may be an oxide, such as silicon oxide. The material of the replacement layer 33 may be a nitride, such as silicon nitride. And the replacement layer 33 is subsequently replaced by a metal (e.g., tungsten) to prepare the gate layer 34, so that the intermediate-state stacked structure 30 becomes the final-state stacked structure 70. And the gate layer 34 closest to the substrate 10 may act as a bottom select gate to control the three-dimensional memory 1. In addition, what is mentioned above in the present application that the insulating layer 32 is protected by the first protective layer 81 is the insulating layer 32 closest to the substrate 10 in the stacked-layer structure 30, and may also be understood as the insulating layer 32 between the bottom select gate and the substrate 10.
Referring to fig. 5, S400, a NAND string 40 penetrating the stacked structure 30, the first protection layer 81, and the sacrificial layer 20 is formed, wherein the NAND string 40 includes a channel layer 42 and a memory layer 43 disposed at a periphery of the channel layer 42.
The NAND string 40 is prepared before the sacrificial layer 20 is etched, so that the NAND string 40 can be used to support the stacked structure 30 when the sacrificial layer 20 is etched, and the stability of the structure of the three-dimensional memory 1 is ensured. The NAND string 40 includes a channel layer 42, and a memory layer 43. Wherein the memory layer 43 is disposed on the periphery of the channel layer 42, i.e. the memory layer 43 is disposed corresponding to the periphery of the outer surface of the channel layer 42. Alternatively, the memory layer 43 may be made of an insulating material and a conductive material, such as silicon oxide and silicon. As for the specific structure of the memory layer 47, the present application will be described later. Optionally, a NAND string 40 may extend through the stack 30, the sacrificial layer 20, and a portion of the substrate 10 (as shown in figure 4). Optionally, NAND string 40 may also include a fill layer 41, with fill layer 41 disposed within channel layer 42. The material of the filling layer 41 may be an insulating material, such as silicon oxide. The channel layer 42 is made of amorphous, polycrystalline, or single crystal silicon.
Referring to fig. 6, S500, a gate gap 44 is formed through the stacked structure 30 and the first protection layer 81.
The present application may then form a gate gap 44 through at least the stack 30 and expose the sacrificial layer 20. Wherein the gate slits 44 are used to subsequently form an array common source 49 within the gate slits 44. In addition, the gate slit 44 is formed first to expose the stacked structure 30 and the sacrificial layer 20, thereby providing a good removal path for subsequent processing of the stacked structure 30 and the sacrificial layer 20.
Referring to fig. 7, S600, the sacrificial layer 20 is removed to form a void 21.
The sacrificial layer 20 may then be removed through the gate slits 44. Optionally, the sacrificial layer 20 is removed using a wet etch.
Referring to fig. 8, S700, a portion of the memory layer 43 in the void 21 is removed to expose the channel layer 42.
As will be understood from the related art, when the memory layer 43 is removed, the insulating layer 32 may be etched into the stacked structure 30 close to the substrate 10 to reduce the thickness of a local area of the insulating layer 32, and even the insulating layer 32 may be etched through, thereby affecting the stability of the electrical performance of the bottom select gate. Optionally, the material of the insulating layer 32 is the same as that of the partial structure in the memory layer 43. Therefore, the first protective layer 81 can be formed on the sacrificial layer 20, and then the stacked-layer structure 30 can be formed on the first protective layer 81, so that the first protective layer 81 can be disposed under the insulating layer 32 as described above, even if the first protective layer 81 is disposed between the insulating layer 32 and the memory layer 43 at the gap 21. Like this when getting rid of memory layer 43, owing to there is the protection of first protective layer 81, no matter how get rid of memory layer 43, can not influence the state of insulating layer 32 yet, can not make the thickness thickening of insulating layer 32 promptly, can not make the thickness attenuate of insulating layer 32 yet, can not make insulating layer 32 by the etching wear even more, controlled insulating layer 32 thickness homogeneity effectively, avoided insulating layer 32 to receive the influence of memory layer 43, improved the stability of bottom select gate electrical property, improved the quality of three-dimensional memory 1. Alternatively, the material of the first protective layer 81 is different from the material of the insulating layer 32 and the memory layer 43. Further optionally, the material of the first protection layer 81 includes, but is not limited to, aluminum oxide.
Referring to fig. 9, S800, a first semiconductor material layer 51 is formed in the gap 21.
Finally, the present application only requires the formation of a semiconductor material within the voids 21. Alternatively, the present embodiment may form the semiconductor material layer 50 in the void 21, on the sidewall of the gate slit 44, and on the surface of the stacked structure 30 by using a chemical vapor deposition method. The array common source 49 may then be formed within the gate gap 44.
In summary, the manufacturing method provided by the present application forms the first protection layer 81 covering the sacrificial layer 20, then forms the stacked structure 30 covering the first protection layer 81, and then forms the NAND string 40. Thus, the first protective layer 81 can be used to prevent the insulating layer 32 from being consumed when the memory layer 43 is subsequently removed, the uniformity of the thickness of the insulating layer 32 is ensured, the insulating layer 32 is prevented from being etched through, the stability of the electrical performance of the bottom selection gate is improved, and the quality of the three-dimensional memory 1 is improved.
Please refer to fig. 10-12 together. Fig. 10 is a process flow diagram of a method for fabricating a three-dimensional memory according to another embodiment of the present disclosure. Fig. 11-12 are schematic structural diagrams corresponding to S410 and S420 in fig. 10, respectively. In this embodiment, defining the surface of the substrate 10 on which the sacrificial layer 20 is formed as a formation surface 11, and forming the NAND string 40 penetrating the stacked structure 30, the first protective layer 81, and the sacrificial layer 20 in S400 "includes S410 and S420. The details of S410 and S420 are as follows.
Referring to fig. 11, S410, forming a trench hole 45 penetrating through the stacked structure 30 and the sacrificial layer 20; the channel hole 45 has a protruding region 450 in the sacrificial layer 20, the protruding region 450 protruding in a radial direction.
Referring to fig. 12, S420, a NAND string 40 is formed within the channel hole 45.
The present application may first form a trench hole 45 penetrating through the stacked structure 30 and the sacrificial layer 20, and during the formation of the trench hole 45, the trench hole may protrude and widen radially in the sacrificial layer 20 to form a protruding region 450. It is also understood that a trench hole 45 is formed through the stacked structure 30 and the sacrificial layer 20; and the width of the channel hole 45 penetrating the laminated structure 30 is made smaller than the width of the channel hole 45 penetrating the sacrifice layer 20 in a direction parallel to the formation surface 11, that is, the channel hole 45 at the sacrifice layer 20 is made wider. NAND string 40 is then formed within channel hole 45. This allows for the formation of a protrusion 400 at the sacrificial layer 20 when forming a NAND string. Alternatively, the memory layer 43 may be formed on the wall of the channel hole 45 first, and then the channel layer 42 may be formed on the surface of the memory layer 43, and optionally, the filling layer 41 may also be formed on the surface of the channel layer 42.
As can be seen from the related art, the memory layer 43 of the NAND string 40 at the edge of the void 21 is not removed cleanly after the sacrificial layer 20 is removed, i.e., the NAND string 40 is close to the substrate 10 and close to the stacked structure 30 in the void 21, so that the thickness of the insulating layer 32 is increased, which also affects the stability of the bottom select gate electrical performance. Accordingly, the present application controls the channel hole 45 at the sacrificial layer 20 to be wider, so that the shape of the memory layer 43 may become "L" shaped (as shown in fig. 12) instead of the vertical shape in the related art, during the formation of the NAND string 40, for example, when the memory layer 43 is formed. I.e. the memory layer 43 occupies the edge positions of the void 21. Therefore, the memory layer 43 protrudes when the memory layer 43 is removed, so that the memory layer 43 can be removed better, the thickness of the insulating layer 32 can be controlled better, the stability of the electrical performance of the bottom selection gate can be improved, and the quality of the three-dimensional memory 1 can be improved. In addition, since the uniformity of the thickness of the bottom insulating layer 32 can be controlled, this also keeps the furthest distance of the bottom select gate from the channel layer 42 in the NAND string 40 fixed, thereby further improving the stability of the bottom select gate current.
Please refer to fig. 13-14 together. Fig. 13 is a process flow diagram of a method for fabricating a three-dimensional memory according to yet another embodiment of the present application. Fig. 14 is a schematic structural diagram corresponding to S710 in fig. 13. In this embodiment, S710 is further included before S800 "forming the first semiconductor material layer 51" in the void 21. The details of S710 are as follows.
Referring to fig. 14, S710, at least a portion of the first passivation layer 81 is removed.
The present application may also remove at least a portion of the first protective layer 81 before forming the first semiconductor material layer 51, thereby removing unwanted structures in the three-dimensional memory 1. Optionally, the removal may be performed together with the subsequent fourth sub-protection layer 64. Alternatively, when the width of the NAND string 40 penetrating the stack structure 70 is smaller than the width of the NAND string 40 penetrating the first semiconductor material layer 51, the embodiment may remove only a portion of the first protection layer 81, so as to leave a portion of the first protection layer 81, i.e., the first protection layer 81 is interposed between the NAND string 40 in the gap 21 and the stacked structure 30 (as shown in fig. 14), so as to further protect the uniformity of the thickness of the insulation layer 32 at the edge.
Please refer to fig. 15-17. Fig. 15 is a process flow diagram of a method for fabricating a three-dimensional memory according to yet another embodiment of the present application. Fig. 16-17 are schematic structural diagrams corresponding to S110 and S120 in fig. 15, respectively. In this embodiment, S100 "providing the substrate 10, and forming the sacrificial layer 20" covering the substrate 10 includes S110 and S120. The details of S110 and S120 are as follows.
Referring to fig. 16, S110, a substrate 10 is provided, and a groove 12 is formed on the substrate 10.
Referring to fig. 17, S120, a sacrificial layer 20 is formed to cover the substrate 10 and the groove 12.
In the preparation of the gate slit 44, since the controller is difficult to form, the gate slit 44 may be etched onto the substrate 10, and even the substrate 10 may be etched through to destroy the three-dimensional memory 1. Therefore, in this embodiment, the substrate 10 may be provided with the groove 12, and the groove 12 corresponds to the position of the gate slit 44 to be formed subsequently, and then the sacrificial layer 20 covering the substrate 10 and the groove 12 is formed. Thus, when the gate gap 44 is formed, if an over-etching condition occurs, the sacrificial layer 20 in the groove 12 can be used to slow down the formation of the gate gap 44, so as to prevent the gate gap 44 from etching through the substrate 10.
In addition, a P-N junction may be formed within the three-dimensional memory 1 to better control the electrical signals of the three-dimensional memory 1. Alternatively, the present application utilizes substrate 10, first layer of semiconductor material 51, and second layer of semiconductor material 52 subsequently formed within recess 12 to form the P-N. Alternatively, in one embodiment, the substrate 10 of the present application may be a P-type semiconductor layer, the first semiconductor material layer 51 may also be a P-type semiconductor layer, and the second semiconductor material layer 52 may be an N-type semiconductor layer. Of course, the substrate 10 may be an N-type semiconductor layer, the first semiconductor material layer 51 may also be an N-type semiconductor layer, and the second semiconductor material layer 52 may be a P-type semiconductor layer. The existence of the groove 12 leads to the fact that the semiconductor layer can be formed directly through epitaxial growth of ion-doped semiconductor materials, and the preparation difficulty of the semiconductor layer is reduced.
Please refer to fig. 18-19 together. Fig. 18 is a process flow diagram of a method for fabricating a three-dimensional memory according to yet another embodiment of the present application. Fig. 19 is a schematic structural diagram corresponding to S510 in fig. 18. In this embodiment, defining the surface of the substrate 10 on which the recess 12 is opened as the formation surface 11, and forming the gate gap 44 "penetrating the stacked structure 30 and the first protective layer 81 in S500" includes S510. The details of S510 are as follows.
Referring to fig. 19, S510, a gate slit 44 penetrating through the stacked structure 30 and the first protection layer 81 is formed, such that an orthographic projection of the gate slit 44 on the substrate 10 is located in the groove 12. It is also understood that the orthographic projection of the gate slit 44 on the substrate 10 is at least partially located within the recess 12; and the width of the groove 12 is made larger than the width of the gate slit 44 in a direction parallel to the formation surface 11.
The present application may also make the width of the groove 12 larger than the width of the gate slit 44, so that the gate slit 44 is more easily aligned with the groove 12, and the gate slit 44 and the groove 12 are prevented from being misaligned.
Please refer to fig. 6 and fig. 20. Fig. 20 is a process flow diagram of a method for fabricating a three-dimensional memory according to yet another embodiment of the present application. In the present embodiment, S500 "forming the gate slit 44" penetrating the stacked structure 30 and the first protective layer 81 includes S520. The details of S520 are as follows.
Referring to fig. 6, S520, a gate slit 44 is formed through the stacked structure 30 and the first protection layer 81, and an opening of the gate slit 44 close to the substrate 10 is flush with a surface of the first protection layer 81 close to the substrate 10.
When the gate slit 44 is formed, the opening of the gate slit 44 close to the substrate 10 can be flush with the surface of the first protection layer 81 close to the substrate 10. Thus, the upper part of the sacrificial layer 20, namely, the part of the sacrificial layer 20 close to the laminated structure 30, can be better removed when the sacrificial layer 20 is removed, and the removal effect of the sacrificial layer 20 is improved.
Please refer to fig. 21-23. Fig. 21 is a process flow diagram of a method for fabricating a three-dimensional memory according to yet another embodiment of the present application. Fig. 22-23 are schematic structural diagrams corresponding to S810 and S820 in fig. 21, respectively. In this embodiment, after S800 "forming the first semiconductor material layer 51" in the void 21, S810 and S820 are further included. The details of S810 and S820 are as follows.
Referring to fig. 22, S810, a portion of the first semiconductor material layer 51 in the gap 21 and a portion of the first semiconductor material layer 51 in the groove 12 are removed.
Referring to fig. 23, S820, a second semiconductor material layer 52 is formed on the first semiconductor material layer 51 in the recess 12 and in the gap 21.
As mentioned above, the three-dimensional memory 1 may form a semiconductor layer, i.e., the second semiconductor material layer 52, by directly epitaxially growing an ion-doped semiconductor material in order to form a P-N junction. Therefore, the present application may first remove the excess first semiconductor material layer 51, and optionally, may remove the first semiconductor material layer 51 on the side of the stacked structure 30 away from the substrate 10, remove the first semiconductor material layer 51 on the sidewall of the gate gap 44, remove a portion of the first semiconductor material layer 51 in the gap 21, and remove a portion of the first semiconductor material layer 51 in the groove 12. In this way, not only the first semiconductor material layer 51 in the recess 12 is removed to expose the substrate 10, but also the first semiconductor material layer 51 in the gap 21 is removed to expose a part of the space and form the receiving groove 13 together with the recess 12. A second layer of semiconductor material 52 is then formed on the first layer of semiconductor material 51 in the recess 12 and in the void 21, i.e. in the receiving pocket 13.
Please refer to fig. 24-25 together. Fig. 24 is a process flow diagram of a method for fabricating a three-dimensional memory according to yet another embodiment of the present application. Fig. 25 is a schematic structural diagram corresponding to S830 in fig. 24. In this embodiment, S820 "forming the second semiconductor material layer 52" on the first semiconductor material layer 51 in the groove 12 and in the void 21 includes S830. The details of S830 are as follows.
Referring to fig. 25, S830, a second semiconductor material layer 52 is formed on the first semiconductor material layer 51 in the recess 12 and in the gap 21, and a side surface of the stacked structure 30 close to the substrate 10 is flush with a side surface of the second semiconductor material layer 52 away from the substrate 10.
The present application can also make the surface of the first semiconductor material layer 51 facing away from the substrate 10 flush with the surface of the stacked structure 30 adjacent to the substrate 10, which can also control the structure of the array common source 49 because the array common source 49 is connected to the second semiconductor material layer 52.
Please refer to fig. 26-29 together. Fig. 26 is a process flow diagram of a method for fabricating a three-dimensional memory according to yet another embodiment of the present application. Fig. 27-29 are schematic structural diagrams corresponding to S130, S140, and S150 in fig. 26, respectively. In this embodiment, S100 "providing the substrate 10, and forming the sacrificial layer 20" covering the substrate 10 includes S130, S140, and S150. The details of S130, S140, and S150 are as follows.
Referring to fig. 27, S130, a substrate 10 is provided.
Referring to fig. 28, S140, a second protective layer 80 is formed to cover the substrate 10.
Referring to fig. 29, S150, a sacrificial layer 20 is formed to cover the second passivation layer 80.
The second protective layer 80 covering the substrate 10 may be formed prior to forming the sacrificial layer 20. Thus, when the sacrificial layer 20 is removed, the second protection layer 80 can be used to protect the substrate 10, so as to prevent the substrate 10 from being partially removed, and effectively protect the structure of the substrate 10. Alternatively, the material of the second protection layer 80 may be silicon oxide.
Please refer to fig. 30-fig. 31. Fig. 30 is a process flow diagram of a method for fabricating a three-dimensional memory according to yet another embodiment of the present application. Fig. 31 is a schematic structural diagram corresponding to S430 in fig. 30. In this embodiment, after forming the gate slit 44 penetrating the stacked structure 30 and the first protective layer 81 in S400 ″, S430 is further included. The details of S430 are as follows.
Referring to fig. 31, S430, a third passivation layer 60 is formed to cover the sidewalls of the gate gap 44. The third protective layer 60 includes a first sub-protective layer 61, a second sub-protective layer 62, a third sub-protective layer 63, and a fourth sub-protective layer 64, which are stacked in sequence along a direction away from the sidewall of the gate slit 44.
After the gate gap 44 is formed, a third protective layer 60 covering the sidewalls of the gate gap 44 may be formed, so that the sidewalls of the gate gap 44 are partially removed and damaged in a subsequent manufacturing process. Optionally, the third protective layer 60 includes a first sub-protective layer 61, a second sub-protective layer 62, a third sub-protective layer 63, and a fourth sub-protective layer 64, which are stacked in sequence along a direction away from the sidewall of the gate slit 44. Further alternatively, the material of the first sub-passivation layer 61 may be silicon nitride, the material of the second sub-passivation layer 62 may be silicon oxide, the material of the third sub-passivation layer 63 may be silicon nitride, and the material of the fourth sub-passivation layer 64 may be aluminum oxide.
Please refer to fig. 32-33 together. Fig. 32 is a process flow diagram of a method for fabricating a three-dimensional memory according to yet another embodiment of the present application. Fig. 33 is a schematic structural diagram corresponding to S440 in fig. 32. In this embodiment, before S500 "removing the sacrificial layer 20 to form the void 21", S440 is further included. The details of S440 are as follows.
Referring to fig. 33, S440, at least a portion of the third passivation layer 60 near one side of the sacrificial layer 20 is removed to expose the sacrificial layer 20.
The present application may also remove at least a portion of the third protection layer 60 near one side of the sacrificial layer 20 to expose the sacrificial layer 20, so as to better remove the sacrificial layer 20, and since the fourth sub-protection layer 64 is disposed on the surface of the gate gap 44, the gate gap 44 may be prevented from being affected when the sacrificial layer 20 is removed.
Please refer to fig. 34-35 together. Fig. 34 is a process flow diagram of a method for fabricating a three-dimensional memory according to yet another embodiment of the present application. Fig. 35 is a schematic structural diagram corresponding to S530 in fig. 34. In this embodiment, the memory layer 43 includes a tunneling layer 46, a memory layer 47, and a blocking layer 48, which are stacked in this order in a direction away from the channel layer 42; s530 is also included after S500 "removing the sacrificial layer 20 to form the voids 21". The details of S530 are as follows.
Referring to fig. 35, in S530, the second passivation layer 80 and the blocking layer 48 are removed.
The memory layer 43 provided in this embodiment includes a tunneling layer 46, a memory layer 47, and a blocking layer 48, which are stacked in this order in a direction away from the channel layer 42. Alternatively, the material of the tunneling layer 46 may include at least one of silicon oxide and silicon nitride. The material of the memory layer 47 may include at least one of silicon nitride, silicon oxynitride, and silicon. The material of barrier layer 48 may be silicon oxide, silicon nitride, a high dielectric constant insulating material, or a combination thereof.
The second protective layer 80 that protects the substrate 10 may be subsequently removed after the sacrificial layer 20 is removed. In addition, the present application may also remove barrier layer 48 first in NAND strings 40 located within voids 21. Optionally, the second protection layer 80 and the barrier layer 48 are made of the same material, such as silicon oxide. The second protective layer 80 and the barrier layer 48 may be removed at the same time.
Please refer to fig. 36-39 together. Fig. 36 is a process flow diagram of a method for fabricating a three-dimensional memory according to yet another embodiment of the present application. Fig. 37-39 are schematic structural diagrams corresponding to S610, S620, and S630 in fig. 36, respectively. In this embodiment, S600 "removing a portion of the memory layer 43" located in the gap 21 includes S610, S620, and S630. The details of S610, S620, and S630 are as follows.
Referring to fig. 37, S610, the fourth sub-passivation layer 64 is removed.
Referring to fig. 38, S620, the third sub-passivation layer 63 and a portion of the memory layer 47 are removed.
Referring to fig. 39, in S630, a portion of the tunneling layer 46 is removed to expose the channel layer 42, and a portion of the second sub-protection layer 62 is removed.
The present application may remove the memory layer 43 and the channel layer 42 together with each sub-protection layer in the second protection layer 80, thereby improving the manufacturing effect. For example, the aluminum oxide layer of the fourth sub-protection layer 64 may be removed first. Optionally, the fourth sub-passivation layer 64 and the first passivation layer 81 are made of the same material, and the fourth sub-passivation layer 64 and the first passivation layer 81 can be removed at the same time. The third sub-protective layer 63 and a portion of the memory layer 47 are subsequently removed. Optionally, the third sub-protection layer 63 and the memory layer 47 are made of the same material, for example, silicon nitride, so that the third sub-protection layer 63 and a portion of the memory layer 47 can be removed at the same time. The tunneling layer 46 and the second sub-protection layer 62 are then removed. Optionally, the second sub-protection layer 62 and the tunneling layer 46 are made of the same material, such as silicon oxide, so that a portion of the tunneling layer 46 and the second sub-protection layer 62 can be removed at the same time. In addition, only a portion of the second sub-protection layer 62 may be removed, that is, a portion of the second sub-protection layer 62 is also included. This prevents semiconductor material layer 50 from growing on the sidewalls of gate gap 44 during the subsequent formation of semiconductor material layer 50. The second sub-protection layer 62 may cause the semiconductor material layer 50 not to grow on the second sub-protection layer 62.
Alternatively, the remaining second sub-protection layer 62 may be removed after the first semiconductor material layer 51 and the second semiconductor material layer 52 are formed. The first sub-passivation layer 61 and the replacement layer 33 may be removed together, and the gate layer 34 may be formed on the replacement layer 33.
In addition to the above method for manufacturing the three-dimensional memory 1, the present embodiment also provides a three-dimensional memory 1. The three-dimensional memory 1 and the method for manufacturing the three-dimensional memory 1 of the present application can achieve the advantages of the present application, and the two can be used together or independently, and the present application is not particularly limited thereto. For example, as an alternative, the three-dimensional memory 1 below may be prepared using the preparation method of the three-dimensional memory 1 provided above.
Referring to fig. 40, fig. 40 is a schematic structural diagram of a three-dimensional memory according to an embodiment of the present disclosure. The present embodiment provides a three-dimensional memory 1, the three-dimensional memory 1 including:
a substrate 10.
A first layer of semiconductor material 51 provided on said substrate 10.
A stack structure 70 is disposed on the first semiconductor material layer 51.
The NAND strings 40 extend through the stack structure 70 and the layers of semiconductor material 50.
The NAND string 40 has a protrusion 400 within the first layer of semiconductor material 51, the protrusion 400 protruding in a radial direction. It is also understood that the surface of the substrate 10 on which the first semiconductor material layer 51 is disposed is defined as a formation surface 11, and the width of the NAND strings 40 extending through the stack structure 70 is smaller than the width of the NAND strings 40 extending through the first semiconductor material layer 51 in a direction parallel to the formation surface 11.
The three-dimensional memory 1 provided herein is formed by providing the NAND string 40 with a protrusion 400 located within the first layer of semiconductor material 51, the protrusion 400 protruding in a radial direction. It can also be understood that making the width of the NAND string 40 across the stack structure 70 smaller than the width of the NAND string 40 across the first semiconductor material layer 51, even though the width of the NAND string 40 at the first semiconductor material layer 51 is wider, can make the memory layer 43 in an "L" shape, make the memory layer 43 occupy the edge area of the first semiconductor material layer 51, can make the memory layer 43 better removed during the manufacturing process, thereby controlling the thickness of the bottom insulating layer 32 and greatly improving the stability of the threshold voltage of the bottom select gate. In addition, since the uniformity of the thickness of the bottom insulating layer 32 can be controlled, this also keeps the furthest distance of the bottom select gate from the channel layer 42 in the NAND string 40 fixed, thereby further improving the stability of the bottom select gate current.
Referring again to fig. 40, in the present embodiment, a first protection layer 81 is interposed between the protruding portion 400 of the NAND string 40 and the stack structure 70. It can also be understood that a first protective layer 81 is sandwiched between the NAND string 40 at the stack structure 70 and the stack structure 70.
When the width of the NAND string 40 penetrating the stack structure 70 is smaller than the width of the NAND string 40 penetrating the first semiconductor material layer 51, the present embodiment may remove only a portion of the first protection layer 81, so as to leave a portion of the first protection layer 81, that is, the first protection layer 81 is further interposed between the NAND string 40 in the gap 21 and the stacked structure 30, so as to further protect the uniformity of the thickness of the insulating layer 32 at the edge.
Referring to fig. 41, fig. 41 is a schematic structural diagram of a three-dimensional memory according to another embodiment of the present application. In this embodiment, the three-dimensional memory 1 further includes a second semiconductor material layer 52 passing through the first semiconductor material layer 51 and the substrate 10. It can also be understood that the first semiconductor material layer 51 and the substrate 10 have a receiving groove 13, and the three-dimensional memory 1 further includes a second semiconductor material layer 52 disposed in the receiving groove 13.
This embodiment can form a P-N junction in the three-dimensional memory 1 to better control the electrical signals of the three-dimensional memory 1. Alternatively, the present application utilizes substrate 10, first layer of semiconductor material 51, and second layer of semiconductor material 52 subsequently formed within recess 12 to form the P-N. Alternatively, in one embodiment, the substrate 10 of the present application may be a P-type semiconductor layer, the first semiconductor material layer 51 may also be a P-type semiconductor layer, and the second semiconductor material layer 52 may be an N-type semiconductor layer. Of course, the substrate 10 may be an N-type semiconductor layer, the first semiconductor material layer 51 may also be an N-type semiconductor layer, and the second semiconductor material layer 52 may be a P-type semiconductor layer. In the present embodiment, the second semiconductor material layer 52 is formed in the accommodating groove 13, which can reduce the difficulty in preparing the second semiconductor material layer 52 and effectively increase the height of the second semiconductor material layer 52.
Referring again to fig. 41, in the present embodiment, the three-dimensional memory 1 further includes an array common source 49 extending through the stack structure 70, wherein the array common source 49 is connected to the second semiconductor material layer 52.
The present application may also have the surface of the array common source 49 near the substrate 10 flush with the surface of the stack structure 70 near the substrate 10. This also controls the structure of the array common source 49, since the array common source 49 is connected to the second layer of semiconductor material 52. Optionally, the surface of the array common source 49 near the substrate 10 is flush with the surface of the stack structure 70 near the substrate 10
Please refer to fig. 42, fig. 42 is a schematic structural diagram of a three-dimensional memory according to another embodiment of the present application. In this embodiment, the orthographic projection of the array common source 49 on the substrate 10 is located within the second semiconductor material layer 52. It will also be appreciated that the width of the second layer of semiconductor material 52, in a direction parallel to the formation surface 11, is greater than the width of the array of common sources 49.
This embodiment can make the width of the second semiconductor material layer 52 larger than the width of the array common source 49, which not only increases the size of the second semiconductor material layer 52, but also reduces the alignment difficulty of the array common source 49 to the receiving groove 13 (i.e. the recess 12).
The present application further provides an electronic device, which includes a three-dimensional memory 1 as provided in the above embodiments of the present application, and a processor, which is used for writing data into the three-dimensional memory 1 and reading data.
The application also provides an electronic device comprising the three-dimensional memory 1 provided by the application. Specifically, the electronic device may be an electronic computer, a smart phone, a smart television, a smart set-top box, a smart router, an electronic digital camera, or the like having a storage device. The electronic device of the present application typically further includes a processor, an input-output device, a display device, and the like. The three-dimensional memory 1 provided by the application is manufactured by processes such as packaging and the like to form a storage device such as a flash memory, and the storage device is used for storing files or data and is called by a processor. Specifically, the processor may write data into the storage device, i.e., the three-dimensional memory 1 provided in the present application, or may read data from the storage device, i.e., the three-dimensional memory 1 provided in the present application. The input and output device is used for inputting instructions or outputting signals, and the display device visualizes the signals to realize various functions of the electronic equipment. According to the electronic device provided by the application, by adopting the three-dimensional memory 1 provided by the above embodiment of the application, the stability of the electrical performance of the three-dimensional memory 1 and the electronic device can be improved, and the quality of the electronic device can be improved.
The foregoing detailed description has provided for the embodiments of the present application, and the principles and embodiments of the present application have been presented herein for purposes of illustration and description only and to facilitate understanding of the methods and their core concepts; meanwhile, for a person skilled in the art, according to the idea of the present application, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present application.
Claims (18)
1. A method for preparing a three-dimensional memory, the method comprising:
providing a substrate, and forming a sacrificial layer covering the substrate;
forming a first protective layer covering the sacrificial layer;
forming a laminated structure covering the first protective layer;
forming a NAND string through the stacked structure, the first protective layer, and the sacrificial layer, the NAND string including a channel layer and a memory layer disposed at a periphery of the channel layer;
forming a gate gap penetrating through the laminated structure and the first protective layer;
removing the sacrificial layer to form a void;
removing a portion of the memory layer located within the void to expose the channel layer;
a first layer of semiconductor material is formed within the void.
2. The method of claim 1, wherein forming a NAND string through the stack structure, the first protective layer, and the sacrificial layer comprises:
forming a channel hole penetrating through the laminated structure and the sacrificial layer; the channel hole has a protruding region located within the sacrificial layer, the protruding region protruding in a radial direction;
a NAND string is formed within the channel hole.
3. The method of claim 2, further comprising, prior to forming the first layer of semiconductor material within the void:
removing at least a portion of the first protective layer.
4. The method of claim 1, wherein providing a substrate and forming a sacrificial layer overlying the substrate comprises:
providing a substrate, wherein a groove is formed in the substrate;
and forming a sacrificial layer covering the substrate and the groove.
5. The method of claim 4, wherein forming a gate gap through the stack structure and the first protective layer comprises:
and forming a gate gap penetrating through the laminated structure and the first protective layer, so that the orthographic projection of the gate gap on the substrate is positioned in the groove.
6. The production method according to claim 4 or 5, further comprising, after "forming the first semiconductor material layer in the void":
removing a portion of the first semiconductor material layer in the void and a portion of the first semiconductor material layer in the recess;
forming a second layer of semiconductor material on the first layer of semiconductor material within the recess and within the void.
7. The method of claim 6, wherein forming a second layer of semiconductor material over the first layer of semiconductor material within the recess and within the void comprises:
and forming a second semiconductor material layer on the first semiconductor material layer in the groove and the gap, and enabling the surface of one side, close to the substrate, of the laminated structure to be flush with the surface of one side, away from the substrate, of the second semiconductor material layer.
8. The method of claim 1, wherein providing a substrate and forming a sacrificial layer overlying the substrate comprises:
providing a substrate;
forming a second protective layer covering the substrate;
and forming a sacrificial layer covering the second protective layer.
9. The method of claim 8, further comprising, after forming a gate gap through the stack structure and the first protective layer:
forming a third protective layer covering the side wall of the gate gap; the third protective layer comprises a first sub protective layer, a second sub protective layer, a third sub protective layer and a fourth sub protective layer which are sequentially arranged along the direction far away from the side wall of the gate gap in a stacking mode.
10. The method of manufacturing according to claim 9, further comprising, before "removing the sacrificial layer to form a void":
and removing at least part of the third protective layer close to one side of the sacrificial layer to expose the sacrificial layer.
11. The method according to claim 10, wherein the memory layer comprises a tunneling layer, a memory layer and a blocking layer which are sequentially arranged in a direction away from the channel layer in a stacked manner; after "removing the sacrificial layer to form a void", further comprising:
and removing the second protective layer and the barrier layer.
12. The method of claim 11, wherein removing the portion of the memory layer located within the void comprises:
removing the fourth sub-protection layer;
removing the third sub-protection layer and part of the storage layer;
and removing part of the tunneling layer to expose the channel layer, and removing part of the second sub-protection layer.
13. A three-dimensional memory, the three-dimensional memory comprising:
a substrate;
a first layer of semiconductor material disposed on the substrate;
a stack structure disposed on the first semiconductor material layer;
a NAND string extending through the stack structure and the layers of semiconductor material;
the NAND string has a protrusion within the first layer of semiconductor material, the protrusion protruding in a radial direction.
14. The three-dimensional memory of claim 13, wherein a first protective layer is sandwiched between the protrusions of the NAND string and the stack structure.
15. The three-dimensional memory according to claim 13, further comprising: a second layer of semiconductor material passing through the first layer of semiconductor material and the substrate.
16. The three-dimensional memory of claim 15, further comprising an array common source through the stack structure, the array common source connecting the second layer of semiconductor material.
17. The three-dimensional memory of claim 16, wherein an orthographic projection of the array common sources on the substrate is located within the second layer of semiconductor material.
18. An electronic device, characterized in that the electronic device comprises a three-dimensional memory according to any of claims 13-17 and a processor for writing data into the three-dimensional memory and reading data.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112331660A (en) * | 2020-10-23 | 2021-02-05 | 长江存储科技有限责任公司 | Three-dimensional memory and manufacturing method thereof |
| CN113488479A (en) * | 2021-06-29 | 2021-10-08 | 长江存储科技有限责任公司 | Three-dimensional memory, preparation method thereof and electronic equipment |
| WO2022083678A1 (en) * | 2020-10-21 | 2022-04-28 | 长江存储科技有限责任公司 | Three-dimensional memory and manufacturing method therefor |
Citations (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105470260A (en) * | 2015-12-03 | 2016-04-06 | 中国科学院微电子研究所 | Three-dimensional semiconductor device and method for manufacturing the same |
| CN105977257A (en) * | 2015-03-11 | 2016-09-28 | 爱思开海力士有限公司 | Semiconductor device and manufacturing method thereof |
| CN106856198A (en) * | 2015-12-08 | 2017-06-16 | 爱思开海力士有限公司 | The manufacture method of semiconductor devices |
| CN106992184A (en) * | 2016-01-18 | 2017-07-28 | 爱思开海力士有限公司 | Semiconductor devices |
| CN107527915A (en) * | 2016-06-22 | 2017-12-29 | 三星电子株式会社 | Memory device |
| CN107996000A (en) * | 2015-09-28 | 2018-05-04 | 桑迪士克科技有限责任公司 | Epitaxial source area for the uniform threshold voltage of the vertical transistor in 3D storage component parts |
| CN109148457A (en) * | 2017-06-16 | 2019-01-04 | 爱思开海力士有限公司 | Semiconductor devices and its manufacturing method |
| CN109494226A (en) * | 2017-09-11 | 2019-03-19 | 爱思开海力士有限公司 | Semiconductor devices and its manufacturing method |
| CN110088905A (en) * | 2016-11-03 | 2019-08-02 | 桑迪士克科技有限责任公司 | Bulb-shaped memory heap stack structure for source contact direct in three dimensional memory device |
| CN110289267A (en) * | 2018-03-19 | 2019-09-27 | 三星电子株式会社 | Wherein with the memory device and its manufacturing method of vertically extending channel structure |
| US20190333929A1 (en) * | 2016-05-23 | 2019-10-31 | SK Hynix Inc. | Semiconductor device and manufacturing method thereof |
| CN111223869A (en) * | 2018-11-27 | 2020-06-02 | 三星电子株式会社 | Method of manufacturing vertical memory device |
-
2020
- 2020-06-18 CN CN202010563701.1A patent/CN111785731A/en active Pending
Patent Citations (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105977257A (en) * | 2015-03-11 | 2016-09-28 | 爱思开海力士有限公司 | Semiconductor device and manufacturing method thereof |
| CN107996000A (en) * | 2015-09-28 | 2018-05-04 | 桑迪士克科技有限责任公司 | Epitaxial source area for the uniform threshold voltage of the vertical transistor in 3D storage component parts |
| CN105470260A (en) * | 2015-12-03 | 2016-04-06 | 中国科学院微电子研究所 | Three-dimensional semiconductor device and method for manufacturing the same |
| CN106856198A (en) * | 2015-12-08 | 2017-06-16 | 爱思开海力士有限公司 | The manufacture method of semiconductor devices |
| CN106992184A (en) * | 2016-01-18 | 2017-07-28 | 爱思开海力士有限公司 | Semiconductor devices |
| US20190333929A1 (en) * | 2016-05-23 | 2019-10-31 | SK Hynix Inc. | Semiconductor device and manufacturing method thereof |
| CN107527915A (en) * | 2016-06-22 | 2017-12-29 | 三星电子株式会社 | Memory device |
| CN110088905A (en) * | 2016-11-03 | 2019-08-02 | 桑迪士克科技有限责任公司 | Bulb-shaped memory heap stack structure for source contact direct in three dimensional memory device |
| CN109148457A (en) * | 2017-06-16 | 2019-01-04 | 爱思开海力士有限公司 | Semiconductor devices and its manufacturing method |
| CN109494226A (en) * | 2017-09-11 | 2019-03-19 | 爱思开海力士有限公司 | Semiconductor devices and its manufacturing method |
| CN110289267A (en) * | 2018-03-19 | 2019-09-27 | 三星电子株式会社 | Wherein with the memory device and its manufacturing method of vertically extending channel structure |
| CN111223869A (en) * | 2018-11-27 | 2020-06-02 | 三星电子株式会社 | Method of manufacturing vertical memory device |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2022083678A1 (en) * | 2020-10-21 | 2022-04-28 | 长江存储科技有限责任公司 | Three-dimensional memory and manufacturing method therefor |
| CN112331660A (en) * | 2020-10-23 | 2021-02-05 | 长江存储科技有限责任公司 | Three-dimensional memory and manufacturing method thereof |
| CN113488479A (en) * | 2021-06-29 | 2021-10-08 | 长江存储科技有限责任公司 | Three-dimensional memory, preparation method thereof and electronic equipment |
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