CN111756354A - Multiphase multi-duty-ratio clock generation circuit - Google Patents
Multiphase multi-duty-ratio clock generation circuit Download PDFInfo
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
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Abstract
The invention discloses a multiphase multi-duty cycle clock generation circuit, comprising: the input end of the input buffer module receives an input signal, and the output end of the input buffer module is connected with the input end of the frequency divider; the output end of the frequency divider is connected with the input ends of the two first-stage inverters; the output end of the second primary phase inverter is connected with the input ends of the second and fourth secondary phase inverters and the input end of the second primary clock output phase inverter; the output end of each secondary phase inverter is connected with the input ends of the two tertiary phase inverters; the eight three-level inverters are connected with four AND gates, the four AND gates, and the output ends of the eight three-level inverters are respectively connected with the first-level clock output inverter, the second-level clock output inverter and the fourth-level clock output inverter; four secondary clock output inverters. The circuit overcomes the defects of low signal frequency, narrow bandwidth and single duty ratio of the multiphase clock generation circuit.
Description
Technical Field
The invention relates to the technical field of integrated circuits, in particular to a multiphase multi-duty-cycle clock generation circuit.
Background
At present, a multi-phase clock generating circuit can generate a plurality of paths of frequency-halved signals or frequency-doubled signals thereof with fixed phase difference and fixed duty ratio by using a clock signal with a fixed phase, and the frequency-halved signals or the frequency-doubled signals are often used as the front end of an interleaving circuit.
In the prior art, almost all multiphase clock generating circuits are built by using CMOS (Complementary Metal oxide semiconductor) devices, generally only clock signals with constant duty ratio can be generated, and the bandwidth and speed are often limited by the device performance. Patent document "a multiphase clock generating circuit" (application No. CN201910502897.0, publication No. CN110299911A) discloses a multiphase clock generating circuit with low power consumption and fixed duty ratio built by CMOS devices according to digital logic, which has the advantages that a clock recovery module is added to the circuit, a clock recovery signal is generated, and the circuit bandwidth is expanded. The disadvantages are that the operating frequency range is still limited, the bandwidth is still narrow and the duty cycle is single. The patent document of the southeast university wujiahui et al (application number CN201610622753.5, publication number CN106257835A) in which the clock signal generation circuit with 25% duty ratio is applied also discloses a four-phase clock generation circuit with 25% duty ratio built by a CMOS, which generates a four-phase clock by using the phase difference of signals of a frequency divider.
Disclosure of Invention
The embodiment of the disclosure provides a multiphase multi-duty cycle clock generation circuit. The following presents a simplified summary in order to provide a basic understanding of some aspects of the disclosed embodiments. This summary is not an extensive overview and is intended to neither identify key/critical elements nor delineate the scope of such embodiments. Its sole purpose is to present some concepts in a simplified form as a prelude to the more detailed description that is presented later.
In some optional embodiments, a multiphase, multi-duty cycle clock generation circuit, comprising:
the input end of the input buffer module receives an input signal, and the output end of the input buffer module is connected with the input end of the frequency divider;
the output end of the frequency divider is connected with the input ends of the two first-stage inverters;
the output end of the second primary phase inverter is connected with the input ends of the second and fourth secondary phase inverters and the input end of the second primary clock output phase inverter;
a first primary clock output inverter and a second primary clock output inverter;
the output end of each secondary phase inverter is connected with the input ends of two tertiary phase inverters with different structures; the output end of the first two-stage phase inverter is connected with the input ends of the first and third-stage phase inverters, the output end of the second two-stage phase inverter is connected with the input ends of the second and fourth-stage phase inverters, the output end of the third two-stage phase inverter is connected with the input ends of the fifth and seventh-stage phase inverters, and the output end of the fourth two-stage phase inverter is connected with the input ends of the sixth and eighth-stage phase inverters;
the output ends of the first and second three-level inverters are input into a first AND gate, the output ends of the third and fourth three-level inverters are input into a second AND gate, the output ends of the fifth and sixth three-level inverters are input into a third AND gate, and the output ends of the seventh and eighth three-level inverters are input into a fourth AND gate;
and the output ends of the four AND gates are respectively connected with the first-fourth secondary clock output inverters.
Further, the frequency divider is a double-emitter double-power ECL frequency divider and is used for generating I/Q two-frequency-divided signals with the phase difference of 90 degrees and the duty ratio of 50 percent.
Further, the first primary output inverter and the second primary output inverter are used for outputting four-phase I/Q two-frequency-divided signals with the phase difference of 90 degrees and the duty ratio of 50 percent.
Further, the first-fourth two-stage clock output inverters are used for outputting four-phase two-division differential clock signals with the phase difference of 90 degrees and the duty ratio of 25%/75%.
Further, the input buffer module, the two primary inverters, the four secondary inverters, and the two primary and four secondary clock output inverters all include an emitter follower circuit and a C-type inverter buffer circuit.
Further, the three-level inverter includes an a-type inverter buffer circuit and a B-type inverter buffer circuit.
Further, a frequency divider circuit, comprising:
the base electrode of the first transistor is a signal input end, the collector electrode of the first transistor is grounded, and the emitter electrodes of the first transistor are respectively connected with the base electrode of the second transistor and a-2.5V power supply through a resistor;
a second transistor, the collector of which is connected with the emitter of the differential pair, the emitter of which is connected with the emitter of the third transistor, and the second transistor is connected with a-3.5V power supply through a resistor;
a third transistor having a collector connected to the emitters of the set of differential pairs;
a fourth transistor, the base of which is the input end of the signal, the collector of which is grounded, the emitter of which is connected with the base of the third transistor and is connected with a-2.5V power supply through a resistor;
a fifth transistor, the base of which is the input end of the signal, the collector of which is grounded, the emitter of which is connected with the base of the sixth transistor and is connected with a-2.5V power supply through a resistor;
a collector of the sixth transistor is connected with the emitters of the differential pairs, and the emitter of the sixth transistor is connected with the emitter of the seventh transistor and then is connected to a-3.5V power supply through a resistor;
a seventh transistor having a collector connected to the emitters of the one set of differential pairs;
the base electrode of the eighth transistor is a signal input end, the collector electrode of the eighth transistor is grounded, the emitter electrodes of the eighth transistor are respectively connected with the base electrode of the seventh transistor and the-2.5V power supply through a resistor;
the collector electrodes of four groups of differential pairs connected with the second transistor, the third transistor, the sixth transistor and the seventh transistor are respectively connected with four resistors with the same resistance value, the base electrodes are respectively connected with the emitter electrodes of one emitter following transistor, the collector electrodes of the emitter following transistors are grounded, and the base electrodes are respectively connected with four resistors with the same resistance value after being correspondingly connected in pairs.
Further, the transistors in the circuit are InP DHBT transistors.
The technical scheme provided by the embodiment of the disclosure can have the following beneficial effects:
the embodiment of the disclosure provides a multiphase multi-duty-ratio clock generating circuit based on an InP DHBT (InP double heterojunction bipolar transistor) process, which includes a signal input buffer module, an emitter duplicate supply ECL (emitter coupled logic) frequency divider, two-way first-level signal inverter buffers, four-way second-level signal inverter buffers, eight-way third-level signal inverter buffers, and four and gate logic circuits, wherein the two-way duty ratio is 50%, the phase difference is 90 ° in the single-ended signal first-level clock output buffer module, the duty ratio is 25%/75%, and the phase difference is 90 ° in the four-way differential signal second-level clock output buffer module. Through the above arrangement, compared with the prior art, the embodiment of the present disclosure has the following advantages:
(1) the broadband high-frequency clock generating circuit disclosed by the embodiment of the invention has the advantages that a fully differential circuit structure is adopted, so that the broadband high-frequency clock generating circuit disclosed by the embodiment of the invention overcomes interference signals such as power supply disturbance and the like, and has better common-mode noise suppression capability;
(2) the InP DHBT transistor is adopted in the embodiment of the invention, so that the problem of poor frequency characteristics of a CMOS device in the prior art is solved, and the excellent cut-off frequency and material mobility of the InP DHBT transistor enable the multiphase multi-duty-cycle clock generation circuit provided by the embodiment of the invention to have the advantages of ultrahigh frequency and ultra-wide band initially;
(3) the embodiment of the disclosure adopts double power supplies to supply power, and partial circuits greatly improve the performance of the ECL frequency divider and each output buffer on the premise of increasing less power consumption, further expand the bandwidth generated by the circuit clock, and improve the power of the output clock and the high-frequency performance of the circuit;
(4) according to the embodiment of the invention, a large amount of phase inverter amplification buffers are inserted between the output of the frequency divider and the AND gate logic, and ECL emitter current mode logic is adopted, so that the influence of coupling feedback among all paths of clock signals is greatly reduced, a purer multiphase clock signal is obtained, the driving capability of a circuit on high-frequency signals is enhanced, and the ultrahigh frequency performance of the circuit is improved;
(5) the embodiment of the disclosure respectively outputs four single-ended four-phase clock signals with 50% duty ratio and 90-degree phase difference and four-phase differential clock signals with 25%/75% duty ratio and 90-degree phase difference, and solves the problem that the current multi-phase clock circuit has single and fixed duty ratio output;
(6) the embodiment of the disclosure is the first multiphase multi-duty-cycle clock generation circuit built by utilizing InP DHBT in China.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention, as claimed.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the invention and together with the description, serve to explain the principles of the invention.
FIG. 1 is a schematic diagram illustrating a multiphase, multi-duty cycle clock generation circuit in accordance with an exemplary embodiment;
FIG. 2 is a schematic diagram illustrating the structure of an emitter follower circuit and a C-inverter buffer circuit in accordance with an exemplary embodiment;
FIG. 3 is a schematic diagram illustrating the structure of a three-level inverter circuit and an AND gate circuit in accordance with an exemplary embodiment;
FIG. 4 is a schematic diagram illustrating the structure of a C-inverter buffer circuit and emitter follower circuit in accordance with an exemplary embodiment;
FIG. 5 is a schematic diagram of a divider circuit according to an exemplary embodiment;
FIG. 6 illustrates a 25%/75% duty cycle clock generation schematic in accordance with an exemplary embodiment;
FIG. 7 is a diagram illustrating simulation results of a multiphase multiple duty cycle clock generation circuit in accordance with an exemplary embodiment.
Detailed Description
So that the manner in which the features and elements of the disclosed embodiments can be understood in detail, a more particular description of the disclosed embodiments, briefly summarized above, may be had by reference to the embodiments, some of which are illustrated in the appended drawings. In the following description of the technology, for purposes of explanation, numerous details are set forth in order to provide a thorough understanding of the disclosed embodiments. However, one or more embodiments may be practiced without these details. In other instances, well-known structures and devices may be shown in simplified form in order to simplify the drawing.
The embodiment of the disclosure builds a high-frequency multiphase multi-duty-cycle clock generation circuit based on an InP DHBT transistor, and the structure of the circuit comprises a dual-power ECL static frequency divider, an ECL inverter, an ECL primary clock output buffer with a duty ratio of 50%, an AND gate logic circuit and an ECL secondary clock output buffer with a duty ratio of 25%/75%. Most of traditional multiphase clock generation circuits are built by CMOS devices, but due to the limitation of material characteristics and the fixed framework of a frequency divider circuit, multiphase clock signals with high frequency and broadband cannot be realized, and the duty ratio of an output clock is single. The invention utilizes the advantages of high mobility and high cut-off frequency of the material of the InP DHBT device, and each module adopts an ECL structure with double power supplies and high driving capability, and performs multi-stage amplification and logic and processing on the I/Q signals obtained by frequency division and having a 90-degree difference, thereby realizing multi-duty ratio multiphase clock output, and overcoming the defects of low signal frequency, narrow bandwidth and single duty ratio of a multiphase clock generating circuit used for the front end of an interweaving circuit in the prior art.
The first embodiment is as follows:
the present disclosure provides a multiphase multi-duty cycle clock generation circuit, which will be described in detail below with reference to fig. 1 to 6.
Fig. 1 is a schematic diagram illustrating a multiphase multi-duty cycle clock generation circuit according to an exemplary embodiment. As shown in fig. 1, a multiphase, multi-duty cycle clock generation circuit includes:
the input end of the input buffer module receives an input signal, and the output end of the input buffer module is connected with the input end of the frequency divider; in some exemplary scenarios, a clock signal with a duty ratio of 50% is input, and after being buffered and amplified by the input buffer module, the signal is sent to the input end of the frequency divider.
Specifically, the input buffer module is composed of EF + C and C + EF circuits and shares one C inverter, where EF is an emitter follower circuit, C is a C-type inverter buffer circuit, and the specific circuit connection relationship is as shown in fig. 2 and 4, fig. 2 is a schematic structural diagram of an emitter follower circuit and a C-type inverter buffer circuit shown according to an exemplary embodiment, and fig. 4 is a schematic structural diagram of a C-type inverter buffer circuit and an emitter follower circuit shown according to an exemplary embodiment.
The frequency divider optionally adopts a double-emitter double-power-supply ECL frequency divider, and by adopting double power supplies, the performance of the ECL frequency divider is greatly improved on the premise that a part of circuits are increased with less power consumption, the bandwidth of the circuits is further expanded, and the power of an output clock and the high-frequency performance of the circuits are improved. The input end of the frequency divider is connected with the input buffer module and used for receiving input signals, and the output end of the frequency divider is connected with the input ends of the two first-stage inverters and used for amplifying I/Q two-frequency-division signals with the phase difference of 90 degrees and the duty ratio of 50 percent. The I signal output by the frequency divider is transmitted to the first one-stage inverter for buffering, and the Q signal output by the frequency divider is transmitted to the second one-stage inverter for buffering.
Fig. 5 is a schematic diagram illustrating a structure of a frequency divider circuit according to an exemplary embodiment, and as shown in fig. 5, the connection relationship of the frequency divider circuit includes: a first transistor Q1, the base of which is the input end of the signal, the collector of which is grounded, and the emitter of which is respectively connected with the base of the second transistor and the-2.5V power supply through a resistor; a second transistor Q2, the collector of which is connected to the emitters of one set of differential pairs, the emitter of which is connected to the emitter of the third transistor, and which is connected to a-3.5V supply via a resistor; a fourth transistor Q4, the base of which is the input terminal of the signal, the collector of which is grounded, the emitter of which is connected with the base of the third transistor, and is connected with the-2.5V power supply through a resistor; a third transistor Q3, the collector of which is connected to the emitters of a set of differential pairs; a fifth transistor Q5, the base of which is the input terminal of the signal, the collector of which is grounded, the emitter of which is connected with the base of the sixth transistor, and is connected with the-2.5V power supply through a resistor; a sixth transistor Q6, the collector of which is connected with the emitter of the differential pair, and the emitter of which is connected with the emitter of the seventh transistor Q7 and then connected with a-3.5V power supply through a resistor; an eighth transistor Q8, the base of which is the input terminal of the signal, the collector of the eighth transistor Q8 is grounded, the emitters are respectively connected with the base of the seventh transistor Q7, and connected with the-2.5V power supply through a resistor; and a seventh transistor Q7 having its collector connected to the emitters of one of the differential pairs.
The collectors of four groups of differential pairs connected with the second transistor Q2, the third transistor Q3, the sixth transistor Q6 and the seventh transistor Q7 are respectively connected with four resistors with the same resistance value, the bases of the four groups of differential pairs are respectively connected with the emitter of one emitter following transistor, the collector of the emitter following transistor is grounded, and the bases of the four groups of differential pairs are respectively connected with the four resistors with the same resistance value after being correspondingly connected in pairs.
In the circuit, the frequency divider adopts a double-emitter ECL structure, the resistors connected with the emitters of the switching transistors Q2, Q3, Q6 and Q7 adopt a-3.5V power supply for power supply, and other parts all adopt a-2.5V power supply for power supply, so that the high-frequency switching performance of the switching transistors in the circuit is improved on the premise of ensuring the correct working state of the frequency divider circuit. The divider transistors Q1, Q4, Q5 and Q8 are emitter follower transistors of the ECL divider, and are important parts constituting a dual emitter circuit, also for the purpose of improving the driving capability of the circuit and expanding the bandwidth range.
The output end of the first one-level phase inverter is connected with the input ends of the first and third two-level phase inverters and the input end of the first one-level clock output phase inverter, the output end of the second one-level phase inverter is connected with the input ends of the second and fourth two-level phase inverters and the input end of the second one-level clock output phase inverter, the first one-level phase inverter on the left side is the first one-level phase inverter, and the first one-level phase inverter on the right side is the second one-level phase inverter.
The two primary phase inverters are connected with the four secondary phase inverters to buffer and amplify the two-phase frequency division signals generated by the frequency divider, the amplified signals are transmitted to the four secondary phase inverters, and the two primary phase inverters are connected with the two primary clock output phase inverters to output four-phase I/Q two-phase frequency division signals with the phase difference of 90 degrees and the duty ratio of 50 percent.
The first-stage clock output inverter and the second-stage clock output inverter are used for outputting four-phase I/Q two-frequency-division signals with the phase difference of 90 degrees and the duty ratio of 50 percent.
Specifically, the left output inverter is a first primary clock output inverter, the right output inverter is a second primary clock output inverter, the first primary clock output inverter and the second primary clock output inverter are both composed of EF + C type circuits, wherein EF is an emitter follower circuit, C is a C type inverter buffer circuit, and power is supplied by a-2.5V power supply, and as the phase difference of the differential output ends of the C inverters is 180 degrees, and the phase difference of the two paths of differential output buffer signals is 90 degrees, the total four single-ended outputs of the two paths of differential ports just form four paths of single-ended output clock signals with the phase difference of 90 degrees, and the duty ratio is 50%.
The four two-level inverters are respectively a first two-level inverter, a second two-level inverter, a third two-level inverter and a fourth two-level inverter from left to right as shown in FIG. 1, wherein the output end of each secondary phase inverter is respectively connected with the input ends of two tertiary phase inverters with different structures, the output end of the first secondary phase inverter is connected with the input ends of the first and third tertiary phase inverters, the output end of the second secondary phase inverter is connected with the input ends of the second and fourth tertiary phase inverters, the output end of the third secondary phase inverter is connected with the input ends of the fifth and seventh tertiary phase inverters, the output end of the fourth secondary phase inverter is connected with the input ends of the sixth and eighth tertiary phase inverters for continuously buffering and amplifying signals sent by the primary phase inverters, thereby reducing the influence of the signal output on the subsequent stage circuit and transmitting the buffered and amplified signal to the three-stage inverter.
Eight three-level inverters, as shown in fig. 1, from left to right, are a first three-level inverter, a second three-level inverter, a third three-level inverter, a fourth three-level inverter, a fifth three-level inverter, a sixth three-level inverter, a seventh three-level inverter, and an eighth three-level inverter, respectively, wherein the output ends of the first and second three-level inverters are input to the first and gate, the output ends of the third and fourth three-level inverters are input to the second and gate, the output ends of the fifth and sixth three-level inverters are input to the third and gate, and the output ends of the seventh and eighth three-level inverters are input to the fourth and gate; and the buffer amplifier is used for continuously buffering and amplifying the signals transmitted by the secondary inverter so as to increase the driving capability of high-frequency signals and sending the buffered and amplified signals to the four AND gate logic operation circuits.
Specifically, the eight three-level inverters are composed of an A-type inverter buffer circuit and a B-type inverter buffer circuit, the first three-level inverter includes the A-type inverter buffer circuit, the second three-level inverter includes the B-type inverter buffer circuit, the third three-level inverter includes the A-type inverter buffer circuit, the fourth three-level inverter includes the B-type inverter buffer circuit, the fifth three-level inverter includes the A-type inverter buffer circuit, the sixth three-level inverter includes the B-type inverter buffer circuit, the seventh three-level inverter includes the A-type inverter buffer circuit, the eighth three-level inverter includes the B-type inverter buffer circuit, the A-type inverter buffer circuit and the B-type inverter buffer circuit are connected to an AND gate, and the specific circuit connection relationship is shown in FIG. 3, FIG. 3 is a schematic diagram illustrating a three-level inverter circuit and an AND gate circuit in accordance with an exemplary embodiment.
In the circuit, the reason that the buffer structures of the A-type inverter, the B-type inverter and the C-type inverter are different is that the high-frequency performance of the inverters is improved by adding the butted transistors, the driving capability of two paths of phase and signals is stronger, and the working state of a post-stage circuit is ensured to be correct.
And the four AND gates are used for carrying out AND gate logic operation on the signals sent by the three-level inverters, and because the duty ratio of each path of the signals of the two-level inverters is 50% and the phase difference between every two paths of the signals is 90 degrees, the AND gate logic operation can be carried out by utilizing the difference between the phases of the signals to obtain the two-frequency-division differential clock signals with the duty ratio of 25%/75% and the phase difference of 90 degrees.
FIG. 6 is a schematic diagram illustrating clock generation at a 25%/75% duty cycle in accordance with an exemplary embodiment. As shown in fig. 6, two clock signals with 90 ° phase difference and 50% duty ratio generated by the frequency divider are logically operated, as shown in the figure, the I signal generated by the frequency divider is anded with the Q signal, so as to obtain a clock signal with 0 ° phase difference and 25%/75% duty ratio, the I non-signal is anded with the Q signal, so as to obtain a clock signal with 90 ° phase difference and 25%/75% duty ratio, the I non-signal is anded with the Q non-signal, so as to obtain a clock signal with 180 ° phase difference and 25%/75% duty ratio, the I signal is anded with the Q non-signal, so as to obtain a clock signal with 270 ° phase difference and 25%/75% duty ratio, and the above operation can completely generate a four-phase clock signal.
Further, the output ends of the four and gates are respectively connected to first to fourth two-stage multiphase clock output inverters, as shown in fig. 1, the first to fourth two-stage clock output inverters are respectively arranged from left to right, and are used for buffering and amplifying the four-phase two-division differential clock signal with a phase difference of 90 ° and a duty ratio of 25%/75% obtained after the logical operation of the and gates, and outputting the four-phase two-division differential clock signal with a phase difference of 90 ° and a duty ratio of 25%/75%.
In a possible implementation manner, the two primary inverters, the four secondary inverters, and the two primary clock output and four secondary clock output inverters are all composed of an EF + C type circuit, where EF is an emitter follower circuit, C is a C type inverter buffer circuit, a specific circuit connection relationship is as shown in fig. 2, and fig. 2 is a schematic structural diagram of an emitter follower circuit and a C type inverter buffer circuit according to an exemplary embodiment.
Further, the circuit connection relationship of each block of the multiphase multi-duty cycle clock generation circuit In the embodiment of the disclosure includes that the output terminals Dn, Dp of the input buffer block are connected to the input terminals Inn and Inp of the frequency divider, and the output terminals In, Ip, Qn, Qp of the frequency divider are respectively connected to the input terminals Cn, Cp of the two primary inverters; the output terminals Op, On of the first-stage inverters are connected to the input terminals Cn, Cp of the first and second first-stage clock output inverters and the input terminals Mn, Mp of the four second-stage inverters; the outputs Dn and Dp of each path of the four-path two-level inverter are respectively connected to the input ends An and Ap, Bn and Bp of the two-path three-level A and B inverters, and then are connected with AND gate logic, the specific modules are connected as shown in figure 1, and the circuits are connected as shown in figure 3; outputs Andn and Andp of the four and gates are connected to input terminals Cn, Cp of the first to fourth two-stage clock output inverters, and finally On, Op outputs four-phase signals.
In a possible implementation manner, a transistor in a circuit is an InP DHBT transistor, the embodiment of the disclosure uses the InP DHBT transistor to build a multiphase multi-duty cycle clock generation circuit, and uses higher cut-off frequency, higher material mobility and low noise performance of the InP DHBT transistor to overcome the problem of poor frequency characteristic of a CMOS device in the prior art and good cut-off frequency and material mobility, so that the multiphase multi-duty cycle clock generation circuit provided by the invention has the advantages of ultrahigh frequency and ultra wide bandwidth primarily, and meanwhile, compared with the CMOS circuit, the multiphase clock generation circuit using a compound DHBT device has good matching characteristic between a base electrode and an emitter electrode, which is more favorable for realizing low noise, low jitter and high purity multiphase clock signal output.
According to the multiphase multi-duty-cycle clock generation circuit provided by the embodiment of the disclosure, a fully differential circuit structure is adopted, so that the clock generation circuit provided by the embodiment of the disclosure has better common-mode noise suppression capability; by adopting the InP DHBT transistor, the circuit disclosed by the embodiment of the disclosure has the advantages of ultrahigh frequency and ultra-wide band initially; by adopting double power supplies for power supply, the performance of the ECL frequency divider and each output buffer is greatly improved, the clock bandwidth of the circuit is further expanded, and the power of an output clock is improved; by inserting a large amount of phase inverters between the output of the frequency divider and the AND gate logic and adopting ECL emitter current mode logic, the influence of coupling feedback between each path of clock signals is greatly reduced, purer multiphase clock signals are obtained, the driving capability of the circuit on high-frequency signals is enhanced, and the ultrahigh frequency performance of the circuit is improved; the embodiment of the disclosure respectively outputs four single-ended four-phase clock signals with 50% duty ratio and 90-degree phase difference and four-phase differential clock signals with 25%/75% duty ratio and 90-degree phase difference, and solves the problem that the output of the duty ratio of the existing multi-phase clock circuit is single and fixed.
Example two:
the embodiment of the disclosure provides an analog simulation example of a multiphase multi-duty-cycle clock generation circuit.
FIG. 7 is a diagram illustrating simulation results of a multiphase multiple duty cycle clock generation circuit in accordance with an exemplary embodiment.
In one possible implementation, the characteristics of the multiphase clock generation circuit of the embodiments of the present disclosure are simulated in ADS software using a 0.8 μm InP DHBT device process library.
Specifically, the circuit characteristics include a clock frequency range applied at the time of input, including the highest frequency and the lowest frequency, and the highest output frequency spectrum of the clocks with different duty ratios, and output waveforms corresponding to the lowest frequency and the highest frequency respectively of the clocks with different duty ratios generated by the analog input signal.
Fig. 7(a) is a single-channel signal spectrum diagram of a multiphase clock generation circuit according to an embodiment of the present disclosure, where the input is 93GHz, the output is 46.5GHz, the duty ratio is 50%, and the phase difference is 90 °, and the highest output power is 1.32dBm at a power of 0 dBm. Fig. 7(b) is a spectrum diagram of a differential signal having a duty ratio of 25%/75% and a phase difference of 90 ° at an input of 93GHz and an output of 46.5GHz, in which the multiphase clock generating circuit of the present invention has a maximum output power of 4.35dBm at a power of 0dBm input. The abscissa in fig. 7(a) and (b) represents a frequency range, and the ordinate represents the power of the output clock signal. It can be seen that the embodiment of the present disclosure has a good power driving performance for the output of different phase and different duty cycle signals, and can realize the multi-phase generation of a high frequency clock signal with an input 93GHz output of 46.5 GHz.
Fig. 7(c) is a time domain waveform diagram of the multiphase clock generation circuit of this embodiment with an output of 46.5GHz at an analog input signal 93GHz, a duty cycle of 50%, and a phase difference of 90 °, that is, an amplitude change of the output multiphase clock signal of the circuit with time. FIG. 7(d) is a time domain waveform diagram showing the output of the multiphase clock generation circuit of this embodiment at an analog input signal 93GHz at 46.5GHz, a duty cycle of 25%/75%, and a phase difference of 90 °. As can be seen from the time domain waveform diagrams in fig. 7(c) and (d), the circuit can realize the function of multiphase multi-duty cycle generation with 50% duty cycle, 90 ° phase difference and 25%/75% duty cycle, 90 ° phase difference at an analog input clock frequency of 93GHz, and thus the disclosed embodiment can realize multiphase multi-duty cycle clock signals up to 46.5GHz, which can meet the requirement of a four-way interleaving circuit within 186GHz of the highest frequency for extremely high frequency and extremely high speed of multiphase clock.
Fig. 7(e) is a time domain waveform diagram of the multiphase clock generation circuit according to the embodiment of the present disclosure at an input signal of 0.5GHz, an output of 0.25GHz, a duty cycle of 50%, and a phase difference of 90 °. FIG. 7(f) is a time domain waveform diagram of the multiphase clock generating circuit at an input of 0.5GHz, an output of 0.25GHz, a duty cycle of 25%/75%, and a phase difference of 90 °. The difference between signals with different duty cycles can be clearly seen compared to high frequencies, and 0.25GHz is the lowest clock signal frequency that can be generated by the disclosed embodiments.
From the above simulation, it can be seen that the analog input bandwidth of the embodiment is 0.5GHz to 93GHz, the output bandwidth of the multiphase clock is 0.25GHz to 46.5GHz, and the duty ratio of the output clock is 50%, 25%/75%.
The above description is only for the preferred embodiment of the present invention, but the scope of the present invention is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present invention are included in the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the appended claims.
Claims (8)
1. A multiphase, multi-duty cycle clock generation circuit, comprising:
the input end of the input buffer module receives an input signal, and the output end of the input buffer module is connected with the input end of the frequency divider;
the output end of the frequency divider is connected with the input ends of the two first-stage inverters;
the output end of the second primary phase inverter is connected with the input ends of the second and fourth secondary phase inverters and the input end of the second primary clock output phase inverter;
two primary clock output inverters;
the output end of each secondary phase inverter is connected with the input ends of two tertiary phase inverters with different structures; the output end of the first two-stage phase inverter is connected with the input ends of the first and third-stage phase inverters, the output end of the second two-stage phase inverter is connected with the input ends of the second and fourth-stage phase inverters, the output end of the third two-stage phase inverter is connected with the input ends of the fifth and seventh-stage phase inverters, and the output end of the fourth two-stage phase inverter is connected with the input ends of the sixth and eighth-stage phase inverters;
the output ends of the first and second three-level inverters are connected with the input end of the first AND gate, the output ends of the third and fourth three-level inverters are input to the second AND gate, the output ends of the fifth and sixth three-level inverters are input to the third AND gate, and the output ends of the seventh and eighth three-level inverters are input to the fourth AND gate;
the output ends of the four AND gates are respectively connected with the four secondary clock output inverters;
four secondary clock output inverters.
2. The clock generation circuit of claim 1, wherein the frequency divider is a dual emitter dual supply ECL frequency divider for generating I/Q halved signals with 90 ° phase difference and 50% duty cycle.
3. The clock generation circuit of claim 1, wherein the first and second primary clock output inverters are configured to output four-phase single-ended I/Q halved signals having a 90 ° phase difference and a 50% duty cycle.
4. The clock generation circuit of claim 1, wherein the first-fourth secondary clock output inverters are configured to output a four-phase, two-divide-by-two differential clock signal having a phase difference of 90 ° and a duty cycle of 25%/75%.
5. The clock generation circuit of claim 1, wherein the input buffer module, the two primary inverters, the four secondary inverters, and the two primary and four secondary clock output inverters each comprise an emitter follower circuit and a C-type inverter buffer circuit.
6. The clock generation circuit of claim 1, wherein the three-level inverter comprises an a-type inverter buffer circuit and a B-type inverter buffer circuit.
7. The clock generation circuit of claim 1, wherein the frequency divider comprises:
the base electrode of the first transistor is the input end of a signal, the collector electrode of the first transistor is grounded, and the emitter electrodes of the first transistor are respectively connected with the base electrode of the second transistor and a-2.5V power supply through a resistor;
a second transistor, the collector of which is connected with the emitter of the differential pair, the emitter of which is connected with the emitter of the third transistor, and the second transistor is connected with a-3.5V power supply through a resistor;
a third transistor having a collector connected to the emitters of the set of differential pairs;
a fourth transistor, the base of which is the input end of the signal, the collector of which is grounded, the emitter of which is connected with the base of the third transistor and is connected with a-2.5V power supply through a resistor;
a fifth transistor, the base of which is the input end of the signal, the collector of which is grounded, the emitter of which is connected with the base of the sixth transistor and is connected with a-2.5V power supply through a resistor;
a sixth transistor, the collector of which is connected with the emitter of the differential pair, the emitter of which is connected with the emitter of the seventh transistor, and is connected with a-3.5V power supply through a resistor;
a seventh transistor having a collector connected to the emitters of the one set of differential pairs;
the base electrode of the eighth transistor is a signal input end, the collector electrode of the eighth transistor is grounded, the emitter electrodes of the eighth transistor are respectively connected with the base electrode of the seventh transistor and the-2.5V power supply through a resistor;
the collector electrodes of four groups of differential pairs connected with the second transistor, the third transistor, the sixth transistor and the seventh transistor are respectively connected with four resistors with the same resistance value, the base electrodes are respectively connected with the emitter electrodes of the emitter following transistors, the collector electrodes of the emitter following transistors are grounded, and the base electrodes are respectively connected with the four resistors with the same resistance value after being correspondingly connected in pairs.
8. The clock generation circuit of any of claims 1-7, wherein the transistors in the circuit are InPDHBT transistors.
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| JPH0879029A (en) * | 1994-09-08 | 1996-03-22 | Sony Corp | Four-phase clock pulse generating circuit |
| US20040260963A1 (en) * | 2003-06-20 | 2004-12-23 | Law Hon-Mo Raymond | Method and apparatus to construct a fifty percent (50%) duty cycle clock signal across power domains |
| CN106257835A (en) * | 2016-08-01 | 2016-12-28 | 东南大学 | A kind of 25% duty cycle clock signal produces circuit |
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| CN110214417A (en) * | 2019-04-18 | 2019-09-06 | 香港应用科技研究院有限公司 | Orthogonal output (QIQO) 3 frequency dividing circuit of the orthogonal input of 50% duty ratio |
| CN110299911A (en) * | 2019-06-11 | 2019-10-01 | 西安电子科技大学 | A kind of multi-phase clock generation circuit |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| JPH0879029A (en) * | 1994-09-08 | 1996-03-22 | Sony Corp | Four-phase clock pulse generating circuit |
| US20040260963A1 (en) * | 2003-06-20 | 2004-12-23 | Law Hon-Mo Raymond | Method and apparatus to construct a fifty percent (50%) duty cycle clock signal across power domains |
| CN106257835A (en) * | 2016-08-01 | 2016-12-28 | 东南大学 | A kind of 25% duty cycle clock signal produces circuit |
| US10367487B1 (en) * | 2017-02-17 | 2019-07-30 | Marvell International Ltd. | Quadrature clock divider with 25%/75% duty cycle |
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