CN111755342B - Method for packaging wafer-level chip - Google Patents
Method for packaging wafer-level chip Download PDFInfo
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- CN111755342B CN111755342B CN202010559444.4A CN202010559444A CN111755342B CN 111755342 B CN111755342 B CN 111755342B CN 202010559444 A CN202010559444 A CN 202010559444A CN 111755342 B CN111755342 B CN 111755342B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/11—Manufacturing methods
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/11011—Involving a permanent auxiliary member, i.e. a member which is left at least partly in the finished device, e.g. coating, dummy feature
- H01L2224/11013—Involving a permanent auxiliary member, i.e. a member which is left at least partly in the finished device, e.g. coating, dummy feature for holding or confining the bump connector, e.g. solder flow barrier
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/114—Manufacturing methods by blanket deposition of the material of the bump connector
- H01L2224/11444—Manufacturing methods by blanket deposition of the material of the bump connector in gaseous form
- H01L2224/1145—Physical vapour deposition [PVD], e.g. evaporation, or sputtering
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/118—Post-treatment of the bump connector
- H01L2224/11848—Thermal treatments, e.g. annealing, controlled cooling
- H01L2224/11849—Reflowing
Abstract
The invention relates to the field of semiconductor packaging, in particular to a method for packaging a wafer-level chip, which comprises the steps of determining the number of prepared solder balls and the radius of the prepared solder balls; determining a target size of a target under-bump metallurgy (UBM) of a target solder ball in a target packaging wafer; providing a wafer to be packaged with a chip bonding pad, and forming a first protective layer on the wafer to be packaged; forming a conductive through hole, and exposing the chip bonding pad through the conductive through hole; forming a metal seed layer; forming a UBM having a target size over the metal seed layer; and placing the determined prepared solder ball on the UBM, and performing reflux treatment on the prepared solder ball to form a target solder ball. The invention prepares the solder balls by determining the reflow number and the reflow radius based on the determined UBM size and carries out merging and reflow treatment, thereby obtaining the solder ball size meeting the user requirement.
Description
Technical Field
The invention relates to the field of semiconductor packaging, in particular to a method for packaging a wafer-level chip.
Background
The popularization of intelligent electronic devices has promoted the rapid development of wafer-level chip packaging technology. Currently, wafer level chip packaging technology is widely applied to the field of intelligent chip packaging such as flash memories, EEPROMs, high-speed DRAMs, SRAMs, LCD drivers, radio frequency devices, logic devices, power/battery management devices, and analog devices (voltage regulators, temperature sensors, controllers, operational amplifiers, power amplifiers).
At present, because the size of the conventional solder ball is determined, in the process of packaging a wafer-level chip, according to the solder ball with the conventional size in the market, the size of the reflowed solder ball obtained according to a solder ball reflow simulation formula is relatively large, only the size of the solder ball in a certain range can be obtained, and the requirement of the solder ball size specified by a customer cannot be met, so that how to obtain the solder ball with a non-standard size to meet the requirements of different customers on the solder balls with different sizes is one of the problems to be solved at present.
Disclosure of Invention
The technical problem to be solved by the invention is that the solder ball in the prior art can not meet the size requirement of the solder ball specified by a customer.
In order to solve the technical problem, the invention discloses a method for packaging a wafer level chip, which comprises the following steps:
determining the number of prepared solder balls and the radius of the prepared solder balls, wherein the radius of each prepared solder ball is equal;
determining a target size of a target under-ball metal layer UBM, wherein the target under-ball metal layer is a metal layer below a target solder ball in a target packaging wafer;
providing a wafer to be packaged, wherein a plurality of chip bonding pads are formed on the first surface of the wafer to be packaged;
forming a first protective layer at least covering the first surface and the surface of the chip bonding pad;
forming a conductive through hole, and exposing the chip bonding pad through the conductive through hole;
forming a metal seed layer covering the inner surface of the conductive via and the exposed surface of the die pad;
forming the target under-ball metal layer (UBM) with the target size above the metal seed layer;
and placing the prepared solder balls on the target under-bump-metallurgy (UBM), and performing reflux treatment on the prepared solder balls to form the target solder balls, wherein the quantity of the placed prepared solder balls is equal to the determined quantity of the prepared solder balls, and the radius of the placed prepared solder balls is equal to the determined radius of the prepared solder balls.
Specifically, the determining the number of the prepared solder balls and the radius of the prepared solder balls comprises:
obtaining a target volume of a target tin ball in a target packaging wafer;
and determining the quantity of the prepared solder balls and the radius of the prepared solder balls according to the target volume of the target solder balls in the target packaging wafer, wherein the radius of each prepared solder ball is equal.
Specifically, the obtaining of the target volume of the target solder ball in the target package wafer includes:
obtaining the target radius and the target ball height of a target solder ball in the target packaging wafer;
and determining the target volume of the target solder ball in the target packaging wafer according to the target radius, the target ball height and a first formula.
Specifically, the determining the number of the prepared solder balls and the radius of the prepared solder balls according to the target volume of the target solder balls in the target packaging wafer comprises:
taking the target volume of the target solder ball in the target packaging wafer as the total volume of the prepared solder ball;
determining the number of the prepared solder balls according to the total volume of the prepared solder balls and a second formula;
and determining the radius of the prepared solder balls according to the quantity of the prepared solder balls and a third formula.
Specifically, the determining the target size of the target UBM includes:
and determining the target size of the UBM according to the target radius, the target ball height and a fourth formula.
In an implementation scheme, the material of the first protection layer is silicon dioxide or silicon nitride.
In an implementation scheme, a second surface of the wafer to be packaged is covered with a back gold layer, and the second surface is a surface opposite to the first surface.
In an implementation, the forming of the conductive via, through which the chip pad is exposed, includes:
and forming a conductive through hole on the first protection layer, wherein the conductive through hole penetrates through the first protection layer and exposes the chip bonding pad through the conductive through hole.
In another practical solution, the forming of the conductive via, through which the chip pad is exposed, includes:
and forming a reinforced protective layer on the first protective layer, forming a conductive through hole on the reinforced protective layer, wherein the conductive through hole penetrates through the reinforced protective layer and the first protective layer, and the chip bonding pad is exposed through the conductive through hole.
In one embodiment, the forming the metal seed layer includes:
forming a metal seed layer by sputtering or physical vapor deposition coating technology, so that the metal seed layer covers the inner surface of the conductive through hole and the exposed surface of the chip bonding pad, wherein the metal seed layer is of a single-layer structure or a multi-layer structure, and the thickness of the metal seed layer is 0.2-1 um.
The method for packaging the wafer-level chip determines the target size of the target UBM and the number and the radius of the prepared solder balls required by preparing the target solder ball according to the known size of the target solder ball required by a customer in the wafer packaging process, and places the determined prepared solder ball on the UBM with the determined target size for reflux treatment, so that the size of the solder ball required by the customer is obtained, and the purpose of obtaining the target solder ball required by the customer according to the solder ball with the conventional size in the prior art is achieved.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
FIG. 1 is a schematic structural diagram of a target solder ball according to the present invention;
FIG. 2 is a schematic flow chart of a packaged wafer level chip according to an embodiment of the present invention;
FIG. 3 is a schematic view showing the process of determining the number of solder balls to be prepared and the radius of the solder balls to be prepared;
FIG. 4 is a schematic flow chart of packaging wafer level chips according to another embodiment of the present invention;
FIGS. 5 a-g are schematic views illustrating a process flow of packaging wafer level chips according to an embodiment of the present invention;
FIG. 6A-K is a schematic process flow diagram of packaging wafer level chips according to another embodiment of the present invention;
in the figure, 1-a wafer to be packaged, 2-a back gold layer, 3-a chip pad, 4-a first protective layer, 5-a metal seed layer, 6-a target solder ball, 7-a back gold protective layer, 8-a strengthening protective layer, 9-a conductive through hole, 10-a preparation solder ball, 11-a soldering flux, and 12-an under ball metal layer UBM.
Detailed Description
In order to make those skilled in the art better understand the technical solutions of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Reference herein to "one embodiment" or "an embodiment" means that a particular feature, structure, or characteristic may be included in at least one implementation of the invention. In the description of the present invention, it is to be understood that the terms "upper", "top", "bottom", and the like refer to orientations or positional relationships based on orientations or positional relationships shown in the drawings, which are used for convenience in describing the present invention and to simplify the description, and do not indicate or imply that the referenced devices or elements must have a particular orientation, be constructed in a particular orientation, and be operated in a particular orientation, and thus, are not to be construed as limiting the present invention. Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. Moreover, the terms "first," "second," and the like are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used is interchangeable under appropriate circumstances such that the embodiments of the invention described herein are capable of operation in other sequences than those illustrated or described herein.
It can be understood that the sizes of the raw solder balls in the current market are determined, for example, 100um, 170um, 250um, etc., during the wafer level chip packaging process, the solder balls are reflowed to obtain the solder balls for packaging with a certain size range, for example, the solder balls for packaging with a size of 120um to 140um can be obtained after the solder balls for raw material of 100um are reflowed, the solder balls for packaging with a size of 180um to 190um can be obtained after the solder balls for raw material of 170um are reflowed, obviously, the solder balls for packaging with a size of 150um in the middle can not be obtained, and the diversified requirements of customers can not be met. Therefore, a method for meeting the diversified demands of customers on solder balls is needed to be found so as to prepare the solder balls for packaging with different sizes and meet the demands of customers.
To solve the above technical problem, as shown in fig. 1, fig. 2 and fig. 5, the present invention provides a method for packaging a wafer level chip, and fig. 1 shows a schematic structural diagram of a target solder ball; fig. 2 shows a schematic flow diagram of a packaged wafer level chip, fig. 5 shows a process flow diagram of a packaged wafer level chip, as shown, the method comprises:
s100, determining the number of the prepared solder balls 10 and the radius of the prepared solder balls 10;
specifically, the preparation of the solder ball 10 is a raw material solder ball for obtaining the target solder ball 6, and the determined preparation solder ball 10 is subjected to reflow processing, so as to obtain the final target solder ball 6. It is understood that in some practical embodiments, the material for preparing the solder ball 10 is a metal or a metal alloy with conductive property, for example, silver, copper or an alloy containing copper and silver, etc.
The determination of the number of the prepared solder balls 10 and the radius of the prepared solder balls 10 can be realized by the following method, specifically, as shown in fig. 3, the method for determining the number of the prepared solder balls 10 and the radius of the prepared solder balls 10 specifically includes:
s200, obtaining the target radius and the target ball height of a target solder ball 6 in a target packaging wafer;
and the target wafer is the finally packaged wafer. Specifically, the target solder balls 6 in the target package wafer are shown in fig. 1, where R represents the target radius and H represents the target ball height. It will be appreciated that the target radius R, as well as the target ball height H, are each of the desired dimensions specified by the customer.
S202, determining the target volume of the target solder ball 6 in the target packaging wafer according to the target radius, the target ball height and a first formula.
Specifically, the first formula is as follows:
wherein, the first and the second end of the pipe are connected with each other,
v is the target volume of the target solder ball in the target packaging wafer;
r is the target radius of the target tin ball in the target packaging wafer;
h is the target ball height of the target solder ball in the target package wafer.
S204, taking the target volume of the target solder ball 6 in the target packaging wafer as the total volume of the prepared solder ball 10;
s206, determining the number of the prepared solder balls 10 according to the total volume of the prepared solder balls 10 and a second formula;
specifically, the second formula is:
V＝nV 1 ；
wherein V is the target volume of the target solder ball in the target packaging wafer;
n is the number of prepared solder balls;
V 1 volume of solder balls for single preparation;
nV 1 the total volume of the solder ball is prepared.
S208, determining the radius of the prepared solder balls 10 according to the number of the prepared solder balls 10 and a third formula, wherein the radius of each prepared solder ball 10 is equal;
specifically, the third formula is:
wherein the content of the first and second substances,
V 1 volume of solder balls for single preparation;
r is the radius of the prepared solder ball.
S102, determining the target size of the UBM 12 under the target ball;
it can be understood that the target UBM 12 is a metal layer under the target solder ball 6 in the target package wafer, the target UBM 12 is an UBM size of the UBM in the determination process of the solder ball, the size of the UBM will determine the radius and height of the solder ball, and under the condition that the target radius and the target height of the target solder ball 6 requested by the customer are known, it is required to ensure that the target size of the target UBM 13 under the target solder ball 6 is correct, otherwise, the size of the UBM will affect the target radius and the target height of the target solder ball finally formed. For example, in the same volume, if the determined target size of the target UBM 12 is too large, the transverse size of the reflowed target solder ball 6 is too large to meet the target radius required by the customer, and the obtained target height is smaller than the height required by the customer, so that the accurate target size of the target UBM 12 determined according to the target radius required by the customer and the target height is the premise of enabling the reflowed target solder ball to be attached to the target radius and the target height.
Specifically, the target size of the target UBM 12 may be determined as follows.
And determining the target size of the UBM 12 under the target ball according to the target radius, the target ball height and a fourth formula.
Specifically, the fourth formula is:
wherein the content of the first and second substances,
L UBM the target size of the UBM is the target size of the UBM;
r is the target radius of the target tin ball in the target packaging wafer;
h is the target ball height of the target solder ball in the target packaging wafer.
S104, providing a wafer 1 to be packaged;
specifically, a plurality of chip pads 3 are formed on the first surface of the wafer 1 to be packaged, and in an implementation scheme, the material of the wafer 1 to be packaged may be a semiconductor material, such as silicon, silicon germanium, and the like.
The chip bonding pad 3 is used for realizing the electrical connection between the chip and the outside. In some practical solutions, the material of the die pad 3 may be a metal or a metal alloy with conductive properties, for example, aluminum, copper, or an alloy containing copper and aluminum. The thickness of the chip bonding pad 3 is 0.5um-1um.
S106, forming a first protective layer 4;
specifically, the first protective layer 4 may cover the first surface and the surface of the die pad 3; alternatively, the first protective layer 4 may cover the first surface, the surface of the die pad 3, and the circumferential surface of the wafer.
In some implementations, the first protection layer 4 is a passivation layer, and plays a role in protecting the first surface and the chip pad 3 on the first surface. Damage to the first surface and the die pad 3 during subsequent operations is avoided. In some practical solutions, the material of the first protection layer 4 may be silicon dioxide or silicon nitride.
S108, forming a conductive through hole 9, and exposing the chip bonding pad 3 through the conductive through hole 9;
specifically, a conductive through hole 9 is formed in the first protective layer 4, and the conductive through hole 9 penetrates through the first protective layer 4 to expose the die pad 3 covered under the first protective layer 4. In some practical solutions, the conductive via 9 may be formed by exposure, development, laser etching, or wet etching.
S110, forming a metal seed layer 5;
specifically, the metal seed layer 5 covers the inner surface of the conductive via 9 and the exposed surface of the die pad 3; in some implementations, the metal seed layer 5 may be formed by sputtering or physical vapor deposition coating techniques such that the metal seed layer 5 covers the inner surface of the conductive via 9 and the exposed surface of the die pad 3. The metal seed layer 5 may have a single-layer structure or a multi-layer structure.
In some implementations, the material of the metal seed layer 5 may be titanium or copper, and when the metal seed layer 5 has a single-layer structure, a titanium metal layer or a copper metal layer may be formed on the inner surface of the conductive via 9 and the exposed surface of the chip pad 3, and the titanium metal layer or the copper metal layer serves as the metal seed layer 5. When the metal seed layer 5 has a multilayer structure, a plurality of titanium metal layers may be formed on the inner surface of the conductive via 9 and the exposed surface of the die pad 3 as the metal seed layer 5, or a plurality of copper metal layers may be formed on the inner surface of the conductive via 8 and the exposed surface of the die pad 3 as the metal seed layer 5, or a stack of titanium metal layers and copper metal layers may be formed on the inner surface of the conductive via 9 and the exposed surface of the die pad 3.
It is understood that, in the above process of forming the metal seed layer 5, physical Vapor Deposition coating technology (PVD) can be preferably adopted, and the Physical Vapor Deposition coating technology chamber refers to a process of transferring atoms or molecules from a source to the surface of the substrate by using Physical processes to realize substance transfer. It can spray some particles with special properties, such as high strength, wear resistance, heat radiation and corrosion resistance, onto the matrix with lower performance, so that the matrix has better performance. The method can improve the bonding strength of the coating material and the provided base material, is suitable for various materials, has diversified coatings, reduces the process time, improves the productivity, has lower temperature for operating the coating technology, has small size deformation of parts, and has no pollution to the process environment.
It is understood that the material of the metal seed layer 5 is titanium or copper, which is only an exemplary illustration, and in other implementations, the material is not limited to titanium or copper.
In some implementations, the metal seed layer 5 has a thickness of 0.2um to 1um;
s112, forming the target under-ball metal layer UBM 12 with the target size above the metal seed layer 5;
s114, placing the prepared solder ball 10 on the target under-ball metal layer UBM 12, and performing reflux treatment on the prepared solder ball 10 to form the target solder ball 6.
It is understood that the number of the prepared solder balls 10 to be placed is equal to the determined number of the prepared solder balls 10, and the radius of the prepared solder balls 10 to be placed is equal to the determined radius of the prepared solder balls 10.
Specifically, the target solder ball 6 is electrically connected to the chip pad 3.
The method for packaging the wafer-level chip determines the target size of the target UBM and the number and the radius of the prepared solder balls required by preparing the target solder ball according to the known size of the target solder ball required by a customer in the wafer packaging process, and places the determined prepared solder ball on the UBM with the determined target size for reflux treatment, so that the size of the solder ball required by the customer is obtained, and the purpose of obtaining the target solder ball required by the customer according to the solder ball with the conventional size in the prior art is achieved.
Further, as shown in fig. 1, fig. 4 and fig. 6, the present invention further provides another wafer level chip packaging method, where fig. 1 shows a schematic structural diagram of a target solder ball, fig. 4 shows another flow diagram for packaging a wafer level chip, fig. 6 shows another flow diagram for packaging a wafer level chip, and as shown in the figure, the method includes:
s300, determining the number of the prepared solder balls 10 and the radius of the prepared solder balls 10;
s302, determining the target size of the UBM 12 under the target ball;
s304, providing a wafer 1 to be packaged;
specifically, a plurality of chip bonding pads 3 are formed on a first surface of the wafer 1 to be packaged, a back gold layer 2 covers a second surface of the wafer 1 to be packaged, and the second surface is opposite to the first surface; in an implementation, the material of the wafer 1 to be packaged may be a semiconductor material, such as silicon, silicon germanium, and the like.
S306, forming a first protective layer 4;
s308, forming a reinforced protective layer 8;
specifically, a reinforcing protective layer 8 is formed on the first protective layer 4. The reinforcing protective layer 8 serves to achieve a further protection of the first surface and of the chip pad 3 displaced from the first surface. In an implementation, the material of the reinforcing protection layer 8 may be polyimide.
S310, forming a back gold protective layer 7;
specifically, the back gold protective layer 7 may cover the back gold layer 2, or the back gold protective layer 7 may also cover the back gold layer 2 and the circumferential surface of the wafer. In some implementable schemes, the material of the back gold protective layer 7 that meets the first temperature or the UV tape, where the first temperature is 150 ℃, and the back gold protective layer 7 can play a certain role in protecting the back gold layer 2 to prevent the back gold layer 2 from being damaged in the subsequent operation process, in this embodiment, the back gold protective layer 7 is the UV tape.
S312, forming a conductive through hole 9 in the strengthening protective layer 8, and exposing the chip bonding pad 3 through the conductive through hole 9;
specifically, the conductive through hole 9 penetrates through the reinforcing protective layer 8 and the first protective layer 4, and exposes the die pad 3 covered under the first protective layer 4. In some practical solutions, the conductive via 9 may be formed by exposure, development, laser etching, or wet etching.
S314, forming a metal seed layer 5;
s316, forming the target under-ball metal layer UBM 12 with the target size above the metal seed layer 5;
s318, removing the back gold protective layer 7;
s320, placing the prepared solder ball 10 on the target under-ball metal layer UBM 12, and performing reflux treatment on the prepared solder ball 10 to form the target solder ball 6;
it is understood that, in the present embodiment, the back gold protective layer 7 is not resistant to high temperature. When the reflow process is performed on the solder ball 10, high temperature is generated, and the back gold protection layer 7 that is not resistant to high temperature is damaged, so the back gold protection layer 7 on the surface of the back gold layer 2 needs to be removed before the reflow process.
S322, forming a second protective layer on the back gold layer 2, and taking the second protective layer as a back gold protective layer 7;
and S324, removing the soldering flux 11 and the back gold layer 7.
It will be appreciated that the flux is the fluxing material required for the reflow process. Because the soldering flux 11 needs to be added in the reflow soldering process, the soldering flux 11 needs to be removed after the reflow soldering is completed, and the back gold layer 2 still can be damaged in the process of removing the soldering flux 11, a second protective layer needs to be formed on the back gold layer 2 again before the soldering flux 11 is removed to serve as the back gold protective layer 7 of the back gold layer, so as to protect the back gold layer 2 in the process of removing the soldering flux 11.
Specifically, the final back gold protective layer 7 is removed, so as to obtain a final large-size packaged wafer-level chip with a back gold layer.
It is to be understood that, in the processes of steps S300 to S324, the explanations of the above embodiments may be referred to where not introduced, and details are not described herein.
In the method for packaging the wafer-level chip, the target size of the target UBM and the number and the radius of the prepared solder balls required by the preparation of the target solder balls are determined according to the size of the target solder balls required by a known customer in the wafer packaging process, and the determined prepared solder balls are placed on the UBM with the determined target size for reflux treatment, so that the size of the solder balls meeting the customer requirement is obtained, and the aim of obtaining the target solder balls meeting the customer requirement according to the solder balls with the conventional size in the prior art is fulfilled.
In addition, the invention forms the back gold protective layer on the metal layer in advance, so that the metal layer is prevented from being damaged due to processes such as etching and the like in the processes of forming the conductive through hole, the metal seed layer and the solder ball above the metal seed layer, a good protection effect on the chip can be achieved, and the failure rate or rejection rate of the packaged product is reduced.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and should not be taken as limiting the scope of the present invention, which is intended to cover any modifications, equivalents, improvements, etc. within the spirit and scope of the present invention.
Claims (10)
1. A method of packaging wafer level chips, comprising:
obtaining a target radius and a target ball height of a target solder ball in a target packaging wafer;
determining the number of prepared solder balls and the radius of the prepared solder balls according to the target radius, the target ball height, a first formula, a second formula and a third formula, wherein the radius of each prepared solder ball is equal;
determining a target size of a target under-ball metal layer (UBM) according to the target radius, the target ball height and a fourth formula, wherein the target under-ball metal layer is a metal layer below a target solder ball in a target packaging wafer;
the first formula is:
the second formula is: v = nV 1
The third formula is:
the fourth formula is:
v is the target volume of a target tin ball in a target packaging wafer, R is the target radius of the target tin ball in the target packaging wafer, H is the target ball height of the target tin ball in the target packaging wafer, n is the number of prepared tin balls, V1 is the volume of a single prepared tin ball, R is the radius of the prepared tin ball, and LUBM is the target size of a UBM (metal under target ball) layer;
providing a wafer to be packaged, wherein a plurality of chip bonding pads are formed on the first surface of the wafer to be packaged;
forming a first protective layer at least covering the first surface and the surface of the chip bonding pad;
forming a conductive through hole, and exposing the chip bonding pad through the conductive through hole;
forming a metal seed layer covering the inner surface of the conductive via and the exposed surface of the die pad;
forming the target UBM having the target size over the metal seed layer; the target under-ball metal layer UBM is used for limiting the radius of the target solder ball obtained after the prepared solder ball reflows to be matched with the target radius and limiting the ball height of the target solder ball obtained after the prepared solder ball reflows to be higher than the target ball height;
placing the prepared solder balls on the target under-ball metal layer UBM, and performing reflux treatment on the prepared solder balls to form the target solder balls, wherein the quantity of the placed prepared solder balls is equal to the determined quantity of the prepared solder balls, and the radius of the placed prepared solder balls is equal to the determined radius of the prepared solder balls.
2. The method of claim 1, wherein the determining the number of solder balls to be fabricated and the radius of the solder balls to be fabricated comprises:
obtaining a target volume of a target tin ball in a target packaging wafer;
and determining the quantity of the prepared solder balls and the radius of the prepared solder balls according to the target volume of the target solder balls in the target packaging wafer, wherein the radius of each prepared solder ball is equal.
3. The method of packaging wafer level chips of claim 2, wherein said determining the number of solder balls to be prepared and the radius of the solder balls to be prepared according to the target radius, the target ball height, the first formula, the second formula, and the third formula comprises:
and determining the target volume of the target solder ball in the target packaging wafer according to the target radius, the target ball height and a first formula.
4. The method of packaging wafer level chips of claim 2, wherein said determining the number of solder balls to prepare and the radius of the solder balls to prepare based on the target volume of the target solder balls in the target packaged wafer comprises:
taking the target volume of the target solder ball in the target packaging wafer as the total volume of the prepared solder ball;
determining the number of the prepared solder balls according to the total volume of the prepared solder balls and a second formula;
and determining the radius of the prepared solder balls according to the quantity of the prepared solder balls and a third formula.
5. The method of packaging wafer level chips of claim 1, wherein said determining a target dimension of a target UBM comprises:
and determining the target size of the UBM according to the target radius, the target ball height and a fourth formula.
6. The method of packaging wafer level chips of claim 1, wherein the material of said first protective layer is silicon dioxide or silicon nitride.
7. The method of claim 1, wherein a second surface of the wafer to be packaged is covered with a back gold layer, the second surface being opposite to the first surface.
8. The method of packaging wafer level chips of claim 1, wherein said opening conductive vias through which said chip pads are exposed comprises:
and forming a conductive through hole on the first protective layer, wherein the conductive through hole penetrates through the first protective layer and exposes the chip bonding pad through the conductive through hole.
9. The method of packaging wafer level chips of claim 1, wherein said opening conductive vias through which said chip pads are exposed comprises:
and forming a reinforced protective layer on the first protective layer, forming a conductive through hole on the reinforced protective layer, wherein the conductive through hole penetrates through the reinforced protective layer and the first protective layer and exposes the chip bonding pad through the conductive through hole.
10. The method of packaging wafer level chips of claim 1, wherein said forming a metal seed layer comprises:
forming a metal seed layer by sputtering or physical vapor deposition coating technology, so that the metal seed layer covers the inner surface of the conductive through hole and the exposed surface of the chip bonding pad, wherein the metal seed layer is of a single-layer structure or a multi-layer structure, and the thickness of the metal seed layer is 0.2-1 um.
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