CN111739871A - Double-sided chip packaging structure and double-sided chip packaging process - Google Patents
Double-sided chip packaging structure and double-sided chip packaging process Download PDFInfo
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- CN111739871A CN111739871A CN202010708382.9A CN202010708382A CN111739871A CN 111739871 A CN111739871 A CN 111739871A CN 202010708382 A CN202010708382 A CN 202010708382A CN 111739871 A CN111739871 A CN 111739871A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
- H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
- H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
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Abstract
The invention provides a double-sided chip packaging structure and a double-sided chip packaging process, and relates to the technical field of chip packaging. The double-sided chip packaging structure comprises a circuit board, a first chip and a second chip; the circuit board comprises a first surface and a second surface which are oppositely arranged, the first surface is provided with a first accommodating groove and a first bonding pad, and the second surface is provided with a second accommodating groove and a second bonding pad; the first chip is arranged in the first accommodating groove and electrically connected with the circuit board, and the second chip is arranged in the second accommodating groove and electrically connected with the circuit board. One of the first and second pads is used for disposing a metal ball, and the other is used for connecting with a testing device or for stacking packaged products on a circuit board. The double-sided chip packaging structure is convenient for testing packaged products or realizing the stacking of the packaged products, the testing is more convenient, and the integration level of the products is also improved.
Description
Technical Field
The invention relates to the technical field of chip packaging, in particular to a double-sided chip packaging structure and a double-sided chip packaging process.
Background
In the conventional double-sided chip packaging structure and method, if a packaged product needs to be subjected to back-end O/S (open and Short test, open circuit test and Short circuit test), a solder ball point test is required, and once the packaged product is mounted on a board, namely after the solder ball point is connected with a circuit board, the packaged product cannot realize O/S test analysis. Under the condition, the solder balls of the upper board need to be independently melted, and then the packaged product is disassembled from the board to carry out the O/S test, so the operation flow is complicated and tedious, and the packaged product can be damaged in the disassembling process.
Disclosure of Invention
The invention provides a double-sided chip packaging structure, which can facilitate the test of packaged products, simplify the test operation flow and improve the product yield. Moreover, the packaged products can be stacked, so that the integration level of the products is improved.
The present invention also provides a double-sided chip packaging process, which can simplify the testing process of packaged products, facilitate the testing operation, and improve the yield of packaged products. Meanwhile, the packaged products manufactured by the process can be stacked, and the integration level of the products is improved.
Embodiments of the invention may be implemented as follows:
in a first aspect, an embodiment of the present invention provides a double-sided chip package structure, including a circuit board, a first chip, and a second chip; the circuit board comprises a first surface and a second surface which are oppositely arranged, the first surface is provided with a first accommodating groove, and the second surface is provided with a second accommodating groove; the first chip is arranged in the first accommodating groove and is electrically connected with the circuit board, and the second chip is arranged in the second accommodating groove and is electrically connected with the circuit board;
a first packaging body is arranged in the first accommodating groove and used for packaging the first chip; a second packaging body is arranged in the second accommodating groove and used for packaging the second chip;
the first surface is provided with a first bonding pad, and the second surface is provided with a second bonding pad; one of the first bonding pad and the second bonding pad is used for arranging metal balls, and the other bonding pad is used for connecting with a testing device or stacking packaged products on the circuit board.
In an optional embodiment, the first pad is disposed at a periphery of the first receiving groove; the second bonding pad is arranged on the periphery of the second accommodating groove.
In an alternative embodiment, the first pad is electrically connected to the circuit board for disposing the metal ball; the second pad is electrically connected with the circuit board and used for being connected with a testing device or used for stacking packaged products.
In an alternative embodiment, the first pad and the second pad are electrically connected.
In an optional embodiment, the number of the first pads is equal to the number of the second pads, and the first pads are disposed corresponding to the second pads, that is, the wiring design of the first pads is consistent with that of the second pads.
In an optional embodiment, the height of the first package body is equal to the depth of the first receiving groove, and the height of the second package body is equal to the depth of the second receiving groove.
In a second aspect, an embodiment of the present invention provides a double-sided chip packaging process, including:
providing a circuit board: the circuit board comprises a first surface and a second surface which are oppositely arranged; the first surface is provided with a first accommodating groove and a first bonding pad, and the second surface is provided with a second accommodating groove and a second bonding pad; the first bonding pad is used for arranging metal balls, and the second bonding pad is used for being connected with a testing device or used for stacking packaged products;
chip mounting: a first chip is mounted in the first accommodating groove, and a second chip is mounted in the second accommodating groove;
packaging the chip: forming a first packaging body in the first accommodating groove to package the first chip; and forming a second packaging body in the second accommodating groove to package the second chip.
In an optional embodiment, in the step of providing a circuit board, the method further includes:
electrically connecting the first pad and the second pad.
In an alternative embodiment, the step of packaging the chip further comprises:
and forming the first packaging body in the first accommodating groove by adopting a printing backflow mode, and forming the second packaging body in the second accommodating groove by adopting a printing backflow mode.
In an optional embodiment, after the step of packaging the chip, the method further includes:
and (4) checking: and carrying out open circuit test and short circuit test on the packaged double-sided chip packaging structure.
The double-sided chip packaging structure and the double-sided chip packaging process provided by the embodiment of the invention have the beneficial effects that:
in the double-sided chip package structure provided by the embodiment of the invention, the first bonding pad is arranged on the first surface of the substrate, the second bonding pad is arranged on the second surface, one of the first bonding pad and the second bonding pad is used for arranging the metal ball, and the other bonding pad is used for connecting with a testing device or stacking other package products on a circuit board. The double-sided chip packaging structure is convenient for testing packaged products or realizing the stacking of the packaged products, simplifies the testing process in the traditional structure and method, is more convenient to test, and is also beneficial to improving the integration level of the products.
The double-sided chip packaging process provided by the embodiment of the invention can enable the structure of a packaged product to be more convenient for test analysis and improve the test efficiency. Meanwhile, the integration level of the product is improved, and the functions of the packaged product are enriched.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the embodiments will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present invention and therefore should not be considered as limiting the scope, and for those skilled in the art, other related drawings can be obtained according to the drawings without inventive efforts.
Fig. 1 is an overall schematic view of a double-sided chip package structure according to a first embodiment of the invention;
fig. 2 is a schematic diagram of a circuit board of a double-sided chip package structure according to a first embodiment of the invention;
fig. 3 is a schematic block diagram of a process flow of a double-sided chip packaging process according to a second embodiment of the present invention;
fig. 4 is a schematic diagram illustrating a step of mounting a first chip in a double-sided chip packaging process according to a second embodiment of the invention;
fig. 5 is a schematic diagram illustrating a first chip packaging step in a double-sided chip packaging process according to a second embodiment of the invention;
fig. 6 is a schematic diagram illustrating a second chip mounting step in a double-sided chip packaging process according to a second embodiment of the invention;
fig. 7 is a schematic diagram illustrating a step of packaging a second chip in a double-sided chip packaging process according to a second embodiment of the invention.
Icon: 100-double-sided chip packaging structure; 101-line; 110-a circuit board; 120-a first surface; 121-a first receiving groove; 123-a first pad; 130-a second surface; 131-a second accommodating groove; 133-a second pad; 140-a first chip; 141-connecting lines; 145-a first package; 150-a second chip; 155-a second package; 160-metal ball.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. The components of embodiments of the present invention generally described and illustrated in the figures herein may be arranged and designed in a wide variety of different configurations.
Thus, the following detailed description of the embodiments of the present invention, presented in the figures, is not intended to limit the scope of the invention, as claimed, but is merely representative of selected embodiments of the invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures.
In the description of the present invention, it should be noted that if the terms "upper", "lower", "inside", "outside", etc. indicate an orientation or a positional relationship based on that shown in the drawings or that the product of the present invention is used as it is, this is only for convenience of description and simplification of the description, and it does not indicate or imply that the device or the element referred to must have a specific orientation, be constructed in a specific orientation, and be operated, and thus should not be construed as limiting the present invention.
Furthermore, the appearances of the terms "first," "second," and the like, if any, are used solely to distinguish one from another and are not to be construed as indicating or implying relative importance.
It should be noted that the features of the embodiments of the present invention may be combined with each other without conflict.
In the traditional double-sided chip packaging structure and method, if the packaged product needs to be subjected to back-end O/S (open and Short test), the test needs to be carried out through solder ball points, and once the packaged product is mounted on a board, namely the solder ball points are connected with a circuit board, the packaged product cannot be subjected to O/S test analysis. Under the condition, the O/S test can be realized only by independently melting the solder balls of the upper plate and then disassembling the packaged product from the plate, the operation flow is complicated, the packaged product can be damaged in the disassembling process, and the yield of the packaged product is reduced.
In order to overcome the defects of the prior art, the embodiment of the invention provides a double-sided chip packaging structure 100 and a double-sided chip packaging process, which can simplify the operation flow of testing, facilitate the O/S test analysis of the packaging structure, improve the testing efficiency, facilitate the improvement of the integration level of a packaged product, and have a wider application range.
First embodiment
Fig. 1 is an overall schematic view of a double-sided chip package structure 100 according to a first embodiment of the invention, and fig. 2 is a schematic view of a circuit board 110 of the double-sided chip package structure 100 according to the first embodiment of the invention; please refer to fig. 1 and fig. 2.
The embodiment provides a double-sided chip package structure 100, which includes a circuit board 110, a first chip 140 and a second chip 150; the circuit board 110 includes a first surface 120 and a second surface 130 disposed oppositely, the first surface 120 is provided with a first receiving slot 121, and the second surface 130 is provided with a second receiving slot 131; the first chip 140 is disposed in the first receiving groove 121, the first chip 140 is electrically connected to the circuit board 110, the second chip 150 is disposed in the second receiving groove 131, and the second chip 150 is electrically connected to the circuit board 110. A first package 145 is disposed in the first receiving groove 121 and is used for packaging the first chip 140; the second receiving cavity 131 is provided with a second package body 155 for packaging the second chip 150. The first surface 120 is further provided with a first pad 123, and the second surface 130 is further provided with a second pad 133. Both the first pads 123 and the second pads 133 are used for disposing the metal balls 160, and the other is used for connection with a testing device or for stacking packaged products on the circuit board 110. This two-sided chip package structure 100 sets up first pad 123 and second pad 133 respectively in the both sides of circuit board 110, can be convenient for package structure carries out the O/S test, improves package structure 'S efficiency of software testing and product yield, simultaneously, is favorable to piling up other electron device or encapsulation product on package structure to realize the diversification of package structure function, improve package structure' S integrated level.
Optionally, in this embodiment, the first pad 123 is electrically connected to the circuit 101 on the circuit board 110, and is used to dispose the metal ball 160, that is, the metal ball 160 may be planted on the first pad 123, and the double-sided chip package structure 100 may be electrically connected to another circuit substrate or an electronic component, for example, when the double-sided chip package structure 100 is applied to an electronic device, the metal ball 160 may be connected to a motherboard of the electronic device. The number of the first pads 123 may be one or more, and is not particularly limited herein, depending on the actual requirement. The second pads 133 are electrically connected to the wiring 101 on the circuit board 110 for connection with a test apparatus or for stacking packaged products. It is easy to understand that the testing device includes, but is not limited to, an O/S testing machine, and if the second pad 133 is electrically connected to the O/S testing machine, it can be easily detected whether there is an open circuit and/or a short circuit on the circuit board 110, and it can be checked whether the package structure meets the product requirements. Of course, without being limited thereto, the testing apparatus may also be other testing instruments for testing the circuit board 110 and the whole package except for open and/or short circuit conditions, such as testing the functions of the first chip 140 and the second chip 150, which is not limited herein. In addition, the second pads 133 may be used for stacking other packaged products. For example, when a plurality of package structures are included in one electronic device, the package structures may be stacked, and the second pads 133 may be used for connecting two adjacent package structures, so as to stack products. Set up like this, can be in the same place the integrated packaging structure of a plurality of different functions, compact structure, small, the function is various, improves the integrated level of product. The number of the second pads 133 may be one or more, and may be set according to actual test requirements or stacking requirements, and is not particularly limited herein.
In this embodiment, the first bonding pad 123 is disposed at the periphery of the first receiving groove 121; the second pad 133 is disposed at the periphery of the second receiving groove 131. With this arrangement, after the first package 145 is formed in the first receiving groove 121, the first pad 123 is exposed on the first surface 120 of the circuit board 110, that is, the first package 145 does not cover the first pad 123, so that the ball mounting operation is performed on the first pad 123. Similarly, the second pads 133 are disposed at the periphery of the second receiving groove 131, after the second package body 155 is completed, the second pads 133 are still exposed on the second surface 130 of the circuit board 110, and the second package body 155 does not cover the second pads 133, which is beneficial to performing a test on the dual-sided chip package structure 100 or stacking other packaged products, electronic devices, and the like on the dual-sided chip package structure 100.
It should be noted that, in the conventional process, the first receiving groove 121 and the second receiving groove 131 are not provided on the circuit board, so that the first chip 140 or the second chip 150 and the ball-planting pad on the surface of the circuit board are on the same surface, the low-temperature solder ball is planted at the ball-planting pad on the surface of one side of the circuit board, the package is formed on the surface of the circuit board by pressure injection molding, the chip, the ball-planting pad on the surface and the low-temperature solder ball are buried in the package, after the ball-planting pad and the low-temperature solder ball on the surface of the circuit board are packaged, the subsequent ball-planting operation will increase the operation process of slotting the package to expose the low-temperature solder ball on the surface, the low-temperature solder ball is melted by high temperature, and new solder balls are planted. If the quantity of planting the ball is a plurality of, then slotted quantity on the packaging body is also a plurality of, so not only the ball planting troublesome poeration, also can not ensure that the size and the depth dimension of many places flutings are unanimous, if many places flutings size is inconsistent, still can lead to follow-up ball planting size and height inequality, lead to packaging structure yield to descend. In addition, when the solder balls are melted at high and low temperatures, voids and solder ball cracks are easily generated, which seriously affects the quality of the packaging structure. Therefore, in the present embodiment, the first pads 123 are disposed at the periphery of the first receiving groove 121, so as to avoid the above defects, and similarly, the second pads 133 are disposed at the periphery of the second receiving groove 131, so as to avoid the second pads 133 being covered by the second package body 155, so as to facilitate performing a test or stacking operation on the second pads 133, and overcome the defects in the prior art.
Optionally, the first pad 123 and the second pad 133 are electrically connected, so that the O/S test of the circuit board 110 and the function test of the first chip 140 and the second chip 150 can be directly performed after the double-sided chip package structure 100 is mounted on the board, thereby simplifying the test procedure and improving the test efficiency. It is easy to understand that the first chip 140 is electrically connected to the circuit board 110, the second chip 150 is electrically connected to the circuit board 110, the first pads 123 are connected to the circuit board 110, and the first pads 123 are used for disposing the metal balls 160, and the metal balls 160 are connected to circuit substrates of other structures, so as to communicate the first chip 140 and the second chip 150 with circuit substrates of other structures. If the second pad 133 is electrically connected to the first pad 123, the test analysis of the second pad 133 is the same as the test analysis of the first pad 123, so that even after the first pad 123 is mounted with balls and mounted on the board, the package structure does not need to be detached from the board, and the test analysis is performed by connecting the test machine with the second pad 133, thereby simplifying the test flow.
Further, the number of the first pads 123 is equal to the number of the second pads 133, and the first pads 123 are disposed corresponding to the second pads 133. It should be noted that, the first pads 123 and the second pads 133 are correspondingly disposed, it is understood that each second pad 133 corresponds to each first pad 123 one by one, and the circuit wiring designs are completely consistent. Therefore, when the ball mounting process is carried out, the first surface 120 or the second surface 130 can be selected optionally, and balls can be mounted on the first bonding pads 123 or the second bonding pads 133, so that the universality of the packaging structure is improved, the flexibility is higher, and the process requirement is reduced.
It should be noted that, if the O/S test is performed before the upper board, the testing machine may also optionally select the first surface 120 or the second surface 130 for the test analysis, for example, the testing machine is connected to the metal balls 160 of the first pads 123 on the first surface 120, or the testing machine may also be connected to the second pads 133 on the second surface 130, so as to implement the double-sided O/S test of the product. If the O/S test is performed after the upper board, the test machine is directly connected with the second bonding pad 133 on the second surface 130, so that the problems that the O/S test analysis cannot be realized after the traditional double-sided chip packaging product is mounted on the board, the solder balls of the upper board need to be independently melted, the O/S test is performed after the solder balls are detached, and the process is complex and tedious are solved.
In this embodiment, the height of the first package body 145 is equal to the depth of the first receiving groove 121, and the height of the second package body 155 is equal to the depth of the second receiving groove 131, that is, the first package body 145 and the second package body 155 are flush with the first surface 120 and the second surface 130 of the circuit board 110, respectively. By the arrangement, the structure is compact, the volume is small, and the surface of the double-sided chip packaging structure 100 is flat, so that the double-sided chip packaging structure is convenient to mount or use for stacking.
The double-sided chip packaging structure 100 provided by the embodiment of the invention has the following advantages:
the double-sided chip package structure 100 is provided with a first receiving groove 121 and a first bonding pad 123 on a first surface 120 of a circuit board 110, a second receiving groove 131 and a second bonding pad 133 on a second surface 130, wherein the first bonding pad 123 is disposed outside the first receiving groove 121, and the second bonding pad 133 is disposed outside the second receiving groove 131. The first chip 140 is disposed in the first receiving cavity 121, and the first package 145 is disposed in the first receiving cavity 121 to package and protect the first chip 140 and the circuit 101. The second chip 150 is disposed in the second receiving groove 131, and the second package 155 is disposed in the second receiving groove 131 to package and protect the second chip 150 and the circuit 101. The first pads 123 are used for disposing the metal balls 160 to electrically connect the double-sided chip package structure 100 with other circuit substrates, and the second pads 133 are used for performing O/S testing or other product function testing, and also can be used for stacking other package products on the double-sided chip package structure 100. This two-sided chip package structure 100 can make things convenient for the rear end test demand, simplifies the test flow, and it is more convenient to test, improves efficiency of software testing, still is favorable to improving package structure's integrated level simultaneously, and the function is abundanter various.
Second embodiment
Fig. 3 is a schematic block diagram of a double-sided chip packaging process according to a second embodiment of the present invention, and fig. 3 is combined with fig. 1 and fig. 2.
The embodiment of the invention provides a double-sided chip packaging process which mainly comprises the following steps:
s10: a circuit board 110 is provided. Referring to fig. 2, the circuit board 110 includes a first surface 120 and a second surface 130 disposed opposite to each other; the first surface 120 is provided with a first receiving groove 121 and a first pad 123, and the second surface 130 is provided with a second receiving groove 131 and a second pad 133; the first pads 123 are used to dispose the metal balls 160, and the second pads 133 are used to connect with a test apparatus or to stack packaged products. Alternatively, the first pads 123 are electrically connected to the second pads 133, and the number and wiring design of the first pads 123 are identical to those of the second pads 133, respectively. The circuit board 110 is manufactured in a board factory, and includes the arrangement of the first receiving groove 121 and the first receiving groove 121, the arrangement of the first pad 123 and the second pad 133, and the wiring on the circuit board 110. Alternatively, the first receiving groove 121 and the second receiving groove 131 may be formed by laser grooving or an etching process, which is not particularly limited herein.
S20: the first chip 140 is mounted and packaged.
Fig. 4 is a schematic diagram illustrating a step of mounting a first chip 140 in a double-sided chip packaging process according to a second embodiment of the invention, and fig. 4 is shown.
Mounting: the first chip 140 is attached to the first receiving groove 121, the first chip 140 is disposed at the bottom of the first receiving groove 121, and the first chip 140 is electrically connected to the circuit board 110. It should be noted that the first chip 140 may be mounted by a front-mount or a flip-chip manner, and if the front-mount mounting is adopted, the first chip 140 and the circuit board 110 may be electrically connected by bonding the connection line 141, and the connection line 141 may be a gold wire, a copper wire, or another wire. If the flip chip is used, the first chip 140 and the circuit board 110 may be electrically connected by providing solder balls on the first chip 140. In this embodiment, the first chip 140 is mounted by a normal mounting method, and one end of the connecting wire 141 is soldered to the circuit board 110, and the other end is soldered to the first chip 140.
Fig. 5 is a schematic diagram illustrating a step of packaging the first chip 140 in a double-sided chip packaging process according to a second embodiment of the invention, and fig. 5 is combined with fig. 4.
Packaging: by using a printing method, a liquid molding compound is printed by using a steel mesh, the molding compound is filled into the first receiving groove 121 of the circuit board 110, and the first chip 140, the circuit board 110 and the circuit 101 are protected by reflow baking to form the first package 145. The first container 121 can be filled with the first encapsulant 145 by a printing encapsulation method, that is, the height of the first encapsulant 145 is equal to the height (depth) of the first container 121, and the surface of the first encapsulant 145 is flush with the first surface 120. The traditional pressure injection molding and encapsulating mode is replaced by a mode of filling the steel mesh printing liquid plastic encapsulating material, so that the defects of glue overflow, line arc flash, mold blockage and the like caused by large injection molding pressure and mold closing pressure and difficult control of process parameters (mold flow and pressure) can be avoided. Moreover, if a pressure injection molding process is adopted, different molds need to be purchased for different height sizes of the plastic package body, and the cost is high. In addition, the pressure injection molding process requires purchasing injection molding machines and molds, and the cost is high. Therefore, in the present embodiment, the first package 145 is formed by printing, which can overcome the defects of the conventional injection molding.
S30: the second chip 150 is mounted and packaged.
Fig. 6 is a schematic diagram illustrating a step of mounting a second chip 150 in a double-sided chip packaging process according to a second embodiment of the invention, and fig. 6 is shown.
Mounting: the circuit board 110 is turned over by 180 degrees, and the second chip 150 is mounted in the second receiving groove 131. The second chip 150 is disposed at the bottom of the second receiving groove 131, and the second chip 150 is electrically connected to the circuit board 110. Optionally, the second chip 150 is connected to the circuit board 110 by wire bonding. The second chip 150 is mounted in a manner similar to that of the first chip 140, and will not be described in detail here.
Fig. 7 is a schematic diagram of a step of packaging the second chip 150 in the double-sided chip packaging process according to the second embodiment of the invention, and fig. 6 and 7 are shown.
Packaging: a second package body 155 is formed in the second receiving groove 131 to package the second chip 150. By using a printing method, a liquid molding compound is printed by using a steel mesh, the molding compound is filled into the second receiving groove 131 of the circuit board 110, reflowing and baking are performed, the connected second chip 150, the circuit board 110 and the circuit 101 are protected, a second package body 155 is formed, and the height of the second package body 155 is equal to the depth of the second receiving groove 131. The packaging method of the second chip 150 is similar to that of the first chip 140, and is not described herein again.
It should be noted that the sequence of steps S20 and S30 may be exchanged or adjusted appropriately, that is, the first chip 140 may be mounted and packaged first, and then the second chip 150 may be mounted and packaged second. Alternatively, the second chip 150 may be mounted and packaged first, and then the first chip 140 may be mounted and packaged. Alternatively, the first chip 140 and the second chip 150 are mounted first, and then the first chip 140 and the second chip 150 are packaged, which is not limited herein.
S40: and (5) planting balls.
Referring to fig. 1, metal balls 160 are implanted on the first pads 123, optionally, solder balls are implanted on the first surface 120 of the circuit board 110 and then reflowed to form solder balls on the surface of the circuit board 110, and the structure after ball implantation is as shown in fig. 1. The solder balls may be used for electrical connection to other circuit substrates, such as a motherboard of an electronic device.
S50: printing, cutting and packaging. As needed, characters and icons are printed on the first package 145 or the second package 155, but it is needless to say that the first package 145 and the second package 155 may be printed at the same time. Alternatively, laser inscription may be employed. And after printing, cutting the blocked packaging structure, cutting the packaging structure into single products by using a cutting machine or a cutter, and packaging and delivering the single products out of the warehouse.
S60: and (6) checking. And performing open circuit test and short circuit test on the packaged single double-sided chip packaging structure 100. Alternatively, before the double-sided chip package structure 100 is mounted on a board, the first surface 120 or the second surface 130 of the circuit board 110 may be arbitrarily selected for test analysis. If the double-sided chip package structure 100 is mounted on the board, the testing machine can be directly connected to the second pad 133 for O/S testing and analysis of the circuit board 110. Further, if the number and the wiring design of the second pads 133 are consistent with those of the first pads 123, the second pads 133 may be used for performing O/S test analysis and test verification of the functions of the first chip 140 and the second chip 150.
In the double-sided chip packaging process provided by the embodiment, the first packaging body 145 and the second packaging body 155 are formed in the first accommodating groove 121 and the second accommodating groove 131 of the circuit board 110 by adopting a printing mode respectively, and the defects of difficult control of process parameters, high cost and the like in the traditional pressure injection molding can be avoided by adopting a printing plastic packaging mode. The first bonding pad 123 and the second bonding pad 133 are respectively arranged on the first surface 120 and the second surface 130, the first bonding pad 123 is arranged outside the first accommodating groove 121, so that balls can be conveniently planted on the first bonding pad 123, the whole packaging process only needs to adopt one-time ball planting, and the defect caused by multiple ball planting in the traditional process is avoided. The second pad 133 is arranged to facilitate testing of the package structure, simplify a testing process, and improve testing efficiency. Meanwhile, the second pads 133 can also be used for continuously stacking other electronic devices on the package structure, so that the integration level of the packaged product is improved, and the functions are diversified.
The contents of other parts not mentioned in this embodiment are similar to those described in the first embodiment, and are not described again here.
In summary, the double-sided chip package structure 100 and the double-sided chip package process provided by the embodiment of the invention have the following beneficial effects:
in this double-sided chip package structure 100, through setting up first pad 123 and second pad 133, be convenient for to package structure' S test, especially behind the package structure upper plate, can also directly carry out O/S test analysis to package structure, need not to dismantle the back test, simplified the test flow greatly, improve efficiency of software testing. Secondly, the number and the wiring of the first bonding pads 123 and the second bonding pads 133 are designed to be consistent, and bonding pads on any surface can be selected for ball bonding in the ball bonding process. When testing, the first pads 123 on the first surface 120 or the second pads 133 on the second surface 130 can be optionally selected for testing, so that the universality is better, and the flexibility is higher. In addition, the stacking of packaged products can be realized through the arrangement of the second bonding pads 133, the product integration level is improved, and the functions are more abundant and diversified.
The above description is only for the specific embodiment of the present invention, but the scope of the present invention is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present invention are included in the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the appended claims.
Claims (10)
1. A double-sided chip packaging structure is characterized by comprising a circuit board, a first chip and a second chip; the circuit board comprises a first surface and a second surface which are oppositely arranged, the first surface is provided with a first accommodating groove, and the second surface is provided with a second accommodating groove; the first chip is arranged in the first accommodating groove and is electrically connected with the circuit board, and the second chip is arranged in the second accommodating groove and is electrically connected with the circuit board;
a first packaging body is arranged in the first accommodating groove and used for packaging the first chip; a second packaging body is arranged in the second accommodating groove and used for packaging the second chip;
the first surface is provided with a first bonding pad, and the second surface is provided with a second bonding pad; one of the first bonding pad and the second bonding pad is used for arranging metal balls, and the other bonding pad is used for connecting with a testing device or stacking packaged products on the circuit board.
2. The dual-sided chip package structure of claim 1, wherein the first bonding pad is disposed at a periphery of the first receiving groove; the second bonding pad is arranged on the periphery of the second accommodating groove.
3. The double-sided chip package structure according to claim 1, wherein the first pads are electrically connected to the circuit board for disposing the metal balls; the second pad is electrically connected with the circuit board and used for being connected with a testing device or used for stacking packaged products.
4. The dual sided chip package structure of claim 3, wherein the first and second pads are electrically connected.
5. The double-sided chip package structure of claim 4, wherein the number of the first pads is equal to the number of the second pads, and the first pads are disposed corresponding to the second pads.
6. The dual-sided chip package structure of any one of claims 1 to 5, wherein a height of the first package body is equal to a depth of the first receiving groove, and a height of the second package body is equal to a depth of the second receiving groove.
7. A double-sided chip packaging process is characterized by comprising the following steps:
providing a circuit board: the circuit board comprises a first surface and a second surface which are oppositely arranged; the first surface is provided with a first accommodating groove and a first bonding pad, and the second surface is provided with a second accommodating groove and a second bonding pad; the first bonding pad is used for arranging metal balls, and the second bonding pad is used for being connected with a testing device or used for stacking packaged products;
chip mounting: a first chip is mounted in the first accommodating groove, and a second chip is mounted in the second accommodating groove;
packaging the chip: forming a first packaging body in the first accommodating groove to package the first chip; and forming a second packaging body in the second accommodating groove to package the second chip.
8. The double-sided chip packaging process of claim 7, wherein the step of providing a circuit board further comprises:
electrically connecting the first pad and the second pad.
9. The double-sided chip packaging process of claim 7, wherein the step of packaging the chip further comprises:
and forming the first packaging body in the first accommodating groove by adopting a printing backflow mode, and forming the second packaging body in the second accommodating groove by adopting a printing backflow mode.
10. The double-sided chip packaging process of claim 7, further comprising, after the step of packaging the chip:
and (4) checking: and carrying out open circuit test and short circuit test on the packaged double-sided chip packaging structure.
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| Application Number | Priority Date | Filing Date | Title |
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| CN2020104150427 | 2020-05-15 | ||
| CN202010415042 | 2020-05-15 |
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| CN111739871A true CN111739871A (en) | 2020-10-02 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN113438799A (en) * | 2021-06-28 | 2021-09-24 | 海光信息技术股份有限公司 | Aging circuit board, aging test structure and aging test method |
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| JP2002043501A (en) * | 2000-07-19 | 2002-02-08 | Nec Tohoku Ltd | Module and substrate |
| CN109742034A (en) * | 2014-01-26 | 2019-05-10 | 清华大学 | A kind of encapsulating structure, packaging method and the template used in packaging method |
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| CN1211821A (en) * | 1997-09-12 | 1999-03-24 | Lg半导体株式会社 | Semiconductor substrate and stackable semiconductor package and fabrication method thereof |
| JP2002043501A (en) * | 2000-07-19 | 2002-02-08 | Nec Tohoku Ltd | Module and substrate |
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Application publication date: 20201002 |