CN111722095A

CN111722095A - Embedded fault injection module and method and high-speed digital circuit system

Info

Publication number: CN111722095A
Application number: CN202010584608.9A
Authority: CN
Inventors: 吕永乐; 曹子剑
Original assignee: CETC 14 Research Institute
Current assignee: CETC 14 Research Institute
Priority date: 2020-06-24
Filing date: 2020-06-24
Publication date: 2020-09-29
Anticipated expiration: 2040-06-24
Also published as: CN111722095B

Abstract

The invention belongs to the technical field of digital circuit testability verification, and discloses an embedded fault injection module, a high-speed digital circuit system and an embedded fault injection method. The embedded fault injection module of the present invention comprises: the signal path circuit is used for ensuring that the high-speed digital circuit system has the same signal characteristics as before access after the embedded fault injection module is accessed, and can intervene in the signal path during fault injection; the fault injection control circuit is used for controlling the signal path circuit and controlling the implementation of fault injection; the fault mode submodule circuit is used for storing a fault injection sequence according to the fault mode library of the high-speed digital circuit module and generating fault injection data of a low-speed signal; and the data communication circuit is used for receiving and analyzing the fault mode simulation instruction of the upper computer and transmitting information to the fault injection control circuit. The invention can solve the problem of high-speed signal fault injection of the high-speed digital circuit module.

Description

Embedded fault injection module and method and high-speed digital circuit system

Technical Field

The invention belongs to the technical field of radar testability verification, and particularly relates to an embedded fault injection module, a method and a high-speed digital circuit system.

Background

Along with the improvement of production and manufacturing process, the integration level of a digital circuit is higher and higher, along with the development of new technologies such as a high-speed serial bus and the like, the signal speed of the digital circuit is higher and higher, the testability verification of electronic weapon equipment products such as radars and the like is more and more difficult, and the faults can not be simulated by adopting the traditional destructive physical means. Failure modes, failure injection and failure verification increasingly stay in theoretical analysis. The coverage rate of the injectable fault modes is reduced, the high-speed signals and other fault modes cannot be injected actually, the reliability of the testability design evaluation result of the product is low, the actual state of the testability design of the product cannot be reflected, and the improvement of the testability design quality of the product is restricted. The following problems mainly exist in the current testability verification of high-speed digital circuits:

1. high-speed signals such as RapidIO and PCIE can not be subjected to fault injection, because the high-speed serial bus signals such as RapidIO can only adopt a point-to-point communication mode, the interference from the outside is difficult, and the fault injection is difficult to realize;

2. high-speed signals such as RapidIO and PCIE can not be tested and verified, and the high-speed serial bus signals such as RapidIO can not cause faults, so that the testing and verification can not be implemented;

3. the testability design evaluation of the high-speed digital circuit module lacks reliable basis, fault injection is difficult to implement, and the testability verification means is deficient, so that the testability design evaluation is low in credibility.

4. Software platforms for testability verification of high-speed digital circuits are complex. For a fault library for testability verification of a high-speed digital circuit, a complex database and various functions are adopted to realize management and calling, a software platform is mostly used to generate a fault mode, and then external auxiliary equipment is used to realize fault injection.

Chinese patent application No. CN201620008336.7 discloses an embedded fault injection control system, which is connected between an SRU-level module of a tested product and a backplane bus of the tested product, and includes: the bus interface module receives a backboard bus signal and an internal signal sent by the SRU-level module; a core control module, generating fault analog signal according to the internal signal or the backboard bus signal output by the bus interface module, transmitting to the bus interface module, and transmitting to the SRU level module by the bus interface module for fault injection; the core control module is connected with the bus interface module through a standard input/output interface. The fault injection control system comprises a computer, a core control module, a standard interface and the like, and relates to complex upper computer function software and the like; the fault injection is fault injection of various types of buses, and the problem of fault injection of high-speed buses such as RapidIO, PCIE, SERDES and the like cannot be solved.

Disclosure of Invention

The invention aims to: aiming at the defects of the prior art, an embedded fault injection module, a method and a high-speed digital circuit system are provided, which can solve the problem of high-speed signal fault injection of the high-speed digital circuit module.

Specifically, the invention is realized by adopting the following technical scheme.

In one aspect, the present invention provides an embedded fault injection module for performing fault simulation and fault injection on a high-speed digital circuit module of a high-speed digital circuit system, including:

the signal path circuit is used for ensuring that the high-speed digital circuit system normally transmits and communicates signals when the embedded fault injection module is accessed into the high-speed digital circuit system, has the same signal characteristics as the embedded fault injection module before the embedded fault injection module is accessed, and can intervene in the signals of the signal path circuit when the fault is injected;

the fault injection control circuit is used for controlling the signal path circuit and controlling the implementation of fault injection;

the fault mode submodule circuit is used for establishing a fault mode submodule according to a fault mode library of the high-speed digital circuit module and storing a fault injection sequence, the fault mode submodule receives an instruction of the fault injection control circuit, reads the stored fault injection sequence, generates fault injection data of a low-speed signal and sends the fault injection data into a related low-speed signal channel;

and the data communication circuit is used for receiving and analyzing the fault mode simulation instruction of the upper computer and transmitting corresponding fault injection information to the fault injection control circuit.

Further, the signal path circuit includes a high speed signal path circuit and a low speed signal path circuit; the high-speed signal path circuit completes transmission and communication of high-speed serial signals and is realized by adopting a high-performance digital cross point switch chip, and a control bus signal of the digital cross point switch chip is controlled by an FPGA chip; the low-speed signal path circuit is realized by adopting an FPGA (field programmable gate array), so that the original signal characteristics are unchanged after input and output signals of the low-speed signal path pass through the FPGA.

Further, the fault injection control circuit comprises a high-speed signal fault injection control circuit, a low-speed signal fault injection control circuit and a fault mode control logic circuit; the high-speed signal fault injection control circuit is used for realizing a control bus logic circuit of the digital cross-point switch chip; the low-speed signal fault injection control circuit is used for controlling a low-speed signal path by the FPGA; and the fault mode control logic circuit is used for controlling the fault mode submodule.

Further, the MCU writes data for controlling the working mode of the digital cross-point switch chip into a latch memory unit of the digital cross-point switch chip by using the FPGA control bus, thereby realizing the programmable control of high-speed channel connectivity output forbidding and equal output current level and input.

Further, the data transmission rate of the various signals does not exceed the highest data transmission rate of each channel of the digital cross-point switch chip.

Further, a plurality of digital cross point switch chips are grouped, and each group processes high-speed signals of different types; the FPGA controls each digital cross-point switch chip corresponding to each high-speed signal independently and sets each signal mode according to the characteristics of each signal bus.

Further, the data communication circuit comprises an upper computer communication interface circuit and a fault injection control communication circuit; the upper computer communication interface circuit receives a fault mode simulation instruction of the upper computer through the MCU; the fault injection control communication circuit is realized by the MCU and the FPGA, and the MCU analyzes a fault mode simulation instruction of the upper computer and transmits related fault injection information to the FPGA. .

On the other hand, the invention also provides a high-speed digital circuit system, which realizes fault injection on the high-speed digital circuit module therein, and comprises the embedded fault injection module, wherein the high-speed digital circuit module for fault injection is connected with other circuit modules of the high-speed digital circuit system through the embedded fault injection module.

Further, the embedded fault injection module is powered by an independent direct current power supply.

In another aspect, the present invention further provides an embedded fault injection method implemented by the high-speed digital circuit system, including the following steps:

the MCU of the embedded fault injection module receives the fault mode simulation instruction and completes instruction analysis, and a fault injection control instruction is generated and sent to the FPGA;

the FPGA completes fault injection data configuration according to the received fault injection control instruction, realizes fault simulation, completes signal path control and fault injection control corresponding to the fault injection control instruction, and implements fault injection;

completing the verification of the failure mode, comprising: after fault injection is carried out, the high-speed digital circuit system injected with the fault has abnormal work, and whether the working state of the high-speed digital circuit system meets the expected effect of the injected fault mode or not is checked; restoring the high-speed digital circuit module to a fault-free state, and checking whether the high-speed digital circuit system works normally;

and repeating the steps until all the failure modes to be verified and the failure types in the failure library are completely verified.

The embedded fault injection module and method of the high-speed digital circuit and the high-speed digital circuit system have the following beneficial effects:

the embedded fault injection module adopts the structural design of MCU + FPGA + digital cross point switch chips; high-speed serial signals such as RapidIO, PCIE, SERDES and the like adopt a digital cross-point switch chip to realize high-speed data transmission and communication, and a control bus signal of the digital cross-point switch chip is realized by the design of an FPGA chip, so that the working state and the data transmission state of the digital cross-point switch chip can be controlled by the FPGA chip, and the purposes of fault simulation and fault injection of the high-speed signals such as RapidIO and the like are realized by controlling a high-speed data transmission channel of the digital cross-point switch chip; the use of the digital cross-point switch chip can ensure the integrity and the mode of the signal of the high-speed serial signal passing through the chip to be unchanged, and can successfully realize the intervention and fault injection of the high-speed serial signal; the problem that high-speed signals such as RapidIO and the like cannot be subjected to fault injection is solved, effective testability verification means and method are provided for the high-speed signals such as RapidIO and the like, and effective data support is provided for testability design evaluation of a high-speed digital circuit.

The fault mode submodule of the invention presets the fault mode in the FPGA, namely, according to the fault mode library of the digital circuit module to be injected, the fault mode which can be partially realized is designed by utilizing the internal logic of the FPGA, and fault coding is carried out on the fault modes which are realized by all the logics; when a fault is injected, the upper computer software platform sends a fault coding instruction to the embedded fault injection module, analyzes the instruction and executes the operation related to the instruction, and then fault simulation and fault injection can be completed; the FPGA logic design method of the fault mode submodule is mainly oriented to a low-speed signal mode, embedded fault simulation and fault injection of a low-speed signal are achieved through design and control of the FPGA, software and hardware design of a testability verification system is optimized, design of an upper computer software platform is simplified, and use of external auxiliary equipment is reduced.

Drawings

Fig. 1 is a schematic diagram of a rigid-flexible board form of the PCB of the present embodiment.

Fig. 2 is a top view of the embedded fault injection structure of the present embodiment.

Fig. 3 is a front view of the embedded fault injection structure of the present embodiment.

Fig. 4 is a schematic view of a usage scenario of the high-speed digital circuit embedded fault injection method of the present embodiment.

Fig. 5 is a functional block diagram of an embedded fault injection module of the present embodiment.

Fig. 6 is a functional block diagram of various high-speed bus control in the present embodiment.

Fig. 7 is an internal functional block diagram of the FPGA of the present embodiment.

The labels in the figure are: 1-a first rigid PCB, 2-a flexible PCB, 3-a second rigid PCB, 4-a first connector, 5-a second connector, 6-an embedded fault injection module mounting part, 7-a flexible PCB protection part, 8-a high-speed digital module mounting part, and 9-a rotatable mechanism.

Detailed Description

The present invention will be described in further detail with reference to the following examples and the accompanying drawings.

Example 1:

the embodiment of the invention discloses an embedded fault injection module and a method, which are used for carrying out fault simulation and fault injection on a radar high-speed digital circuit module and providing reliable basis for test verification and evaluation of the radar high-speed digital circuit.

As shown in fig. 1, the embedded fault injection module of the high-speed digital circuit adopts a rigid-flexible PCB, two ends of the PCB are respectively provided with a first rigid PCB 1 and a second rigid PCB 3, and a flexible PCB 2 electrically connected to the first rigid PCB 1 and the second rigid PCB 3 is arranged between the first rigid PCB 1 and the second rigid PCB 3. The free end of the first rigid PCB board 1 is provided with a first connector 4 which is used for connecting a back plate of a working plug box of a radar digital circuit system; one end of the second rigid PCB 3 is provided with a second connector 5 for connecting a high-speed digital circuit module which needs fault injection. As shown in fig. 2 and 3, the embedded fault injection module is installed in the embedded fault injection structure and then connected to the backplane of the radar digital circuit system plug box. The embedded fault injection structure comprises an embedded fault injection module mounting part 6, a flexible PCB protection part 7, a high-speed digital module mounting part 8 and a rotatable mechanism 9. The embedded fault injection module mounting part 6 is used for fixing and mounting the part of the connecting system plug-in box back plate of the embedded fault injection module, the flexible PCB protection part 7 is used for protecting the flexible PCB 2, and the rotatable mechanism 9 is used for adjusting the angle between the embedded fault injection module mounting part 6 and the high-speed digital module mounting part 8, so that the high-speed digital circuit module can be conveniently mounted, debugged and tested. Before fault injection, the embedded fault injection module is installed in the embedded fault injection structure. During fault injection, as shown in fig. 4, the high-speed digital circuit module is pulled out from the slot position of the radar digital circuit system working plug box, the embedded fault injection module of the embodiment is installed in the embedded fault injection module installation part 5 of the embedded fault injection structure, the embedded fault injection structure is inserted in the original slot position, the embedded fault injection module is connected with the back plate of the radar digital circuit system working plug box through the first connector 4, the high-speed digital circuit module is installed in the high-speed digital circuit module installation part 8 of the embedded fault injection structure, and the embedded fault injection module is connected through the second connector 5. Therefore, the signal connection is changed from the mode of interconnecting the backboard and the high-speed digital circuit module into the mode of connecting the backboard and the high-speed digital circuit module through the embedded fault injection module. The embedded fault injection module adopts an independent 12V direct current power supply for power supply, and the power consumption of a radar digital circuit system is not increased. After the installation is completed, the first rigid PCB (printed circuit board) 1 of the embedded fault injection module partially extends out of the work plug-in box, the extending part is provided with an RS232 interface for communicating with an upper computer, and the RS232 control design is simple and practical. It can be understood that the communication interface with the upper computer can also be realized by adopting other common communication interface designs such as LAN and the like. The embedded fault injection module adopts a mode of combining the rigid PCB and the flexible PCB, so that signal switching is easy to realize, the signal switching frequency is minimum, the high-speed signal quality and the signal integrity are ensured, and the obvious reduction of the signal quality caused by excessive switching frequency is avoided as much as possible. The flexible PCB protection part 7 can provide a good protection function when the flexible PCB 2 is bent. The rotatable mechanism 9 enables the embedded fault injection module to be conveniently installed in a working plug box of the radar digital circuit system, and debugging and testing of the embedded fault injection module and the high-speed digital circuit module are facilitated. The high-speed digital module mounting part 8 provides necessary slots and guide rails for the high-speed digital circuit module, and is convenient to mount and fix.

The embedded fault injection module of the high-speed digital circuit adopted in this embodiment realizes fault simulation and fault injection for the high-speed digital circuit module, and is mainly realized by adopting an MCU, an FPGA, a digital cross-point switch chip and the like based on a VPX standard 6U bus interface, as shown in fig. 5. MCU realizes processing and control function, FPGA realizes logic function, high-performance digital cross point switch chip is the key to realize high-speed serial signal fault injection such as RapidIO, PCIE, SERDES, can both guarantee signal integrality and signal mode invariant after high-speed serial signal passes through high-performance digital cross point switch chip, can successfully realize high-speed serial signal's intervention and fault injection again.

The embedded fault injection module of the high-speed digital circuit of the embodiment is mainly divided into a signal path circuit, a fault injection control circuit, a fault mode sub-module circuit and a data communication circuit according to circuit functions.

The signal path circuit can ensure that the module can maintain the normal work of the system under the condition of no fault, and is a precondition for ensuring the effectiveness of fault injection; the fault injection control circuit realizes the core functions of the embedded fault injection module, namely fault simulation and fault injection; the fault module type sub-module circuit is used for generating fault injection data; the data communication circuit realizes the functions of transmission control of test instructions, test data and test results and the like.

Signal path circuit

The signal path circuit is used for ensuring that the system can normally transmit and communicate signals when no fault exists after the embedded fault injection module is connected to the radar digital circuit system, and the embedded fault injection module can intervene in the signals of the signal path circuit when the fault is injected. The signal path circuit is divided into a high-speed signal path circuit and a low-speed signal path circuit. The transmission and control modes of the high-speed signal and the low-speed signal are different. The high-speed signal path circuit completes data transmission and communication of high-speed serial signals such as RapidIO, PCIE, SERDES and the like, and is realized by adopting a high-performance digital cross-point switch chip, so that the integrity of the signals of the high-speed serial signals passing through the high-performance digital cross-point switch chip and the working mode of the signals are ensured to be unchanged. The control bus signal of the digital cross point switch chip is controlled by the FPGA chip. The low-speed signal path realizes other signal communication and data transmission of the high-speed digital circuit module, and ensures complete switching and butt joint of interface signals of the whole PCB of the high-speed digital circuit module which needs fault injection. The low-speed signal path circuit is realized by adopting the FPGA, so that the original signal characteristics are unchanged after the input and output signals of the low-speed signal path pass through the FPGA, the normal communication and data transmission of the low-speed signals of the high-speed digital circuit module are ensured, and the fault simulation and fault injection can be conveniently completed through instructions.

The key point of the fault simulation of high-speed serial signals such as RapidIO, PCIE, SERDES and the like is to adopt a digital cross-point switch chip to realize high-speed data exchange. In this embodiment, a digital cross-point switch chip AD8156 with an equalizer from ADI corporation is used. The digital cross-point switch chip supports the configuration of a fully differential 4 x 4 input channel and can also be configured as a dual 2 x 2 input channel; the high-speed serial signal can be directly output according to the double 2 x 2 channels. The data transmission rate of each input channel of the digital cross-point switch chip can reach 6.25Gbps at most, and the chip power consumption is low. Each input channel has an equalizer that compensates for signal transmission line losses. The digital cross-point switch chip controls the signal output mode in a programmable manner.

High-speed serial signals such as RapidIO, PCIE, SERDES and the like accord with the alternating current CML level standard, and can be directly connected into the digital cross-point switch chip or connected into the digital cross-point switch chip through a coupling capacitor. The data transmission rates of signals such as RapidIO, PCIE, SERDES and the like are different, and the data transmission rates of various signals do not exceed the highest data transmission rate (6.25Gbps) of each channel of the digital cross-point switch chip. For different kinds of signals such as RapidIO, PCIE, SERDES, etc., a plurality of digital crosspoint switch chips may be grouped, and each group processes different kinds of signals, as shown in fig. 6. The FPGA controls each digital cross point switch chip corresponding to each high-speed signal independently, and sets respective signal modes such as 4 multiplied by 4 or double 2 multiplied by 2 according to respective signal bus characteristics so as to meet the requirements of different types of high-speed serial signals. Signal compensation is achieved by an equalizer in the digital cross-point switch chip to ensure signal quality and high-speed signal integrity.

It is understood that the functions of the MCU of the present invention can also be implemented using an IP core design of an ARM, DSP, CPU chip or similar functional chip. The chips and the MCU belong to the same type of processor, and have different capabilities and similar functions.

It can be understood that the low-speed signal path of the present invention can be implemented by a dedicated chip or a switch chip, and the fault injection can be implemented by an external input design.

Second, fault injection control circuit

The fault injection modes of the high-speed signal and the low-speed signal are different. The fault injection control circuit mainly comprises a high-speed signal fault injection control circuit, a low-speed signal fault injection control circuit and a fault mode control logic circuit. The high-speed signal fault injection control circuit is a control bus logic circuit of the digital cross-point switch chip by the FPGA chip, and realizes the ordered control of the digital cross-point switch chip; the low-speed signal fault injection control circuit is used for controlling a low-speed signal path; and the fault mode control logic circuit is used for controlling the fault mode submodule, and all functions are realized by the design of an FPGA chip, as shown in FIG. 7.

Three, fault mode submodule circuit

The fault mode sub-module circuit is used for generating fault injection data. And when the fault mode submodule works, the fault mode submodule receives an instruction of a fault mode control logic circuit, generates fault injection data by reading the stored fault injection sequence and sends the fault injection data to a related low-speed signal channel to realize low-speed signal fault injection.

Each high-speed digital circuit module required by fault verification comprises a limited fault mode library, and according to the characteristics of each low-speed signal fault mode, the FPGA simulates and realizes the fault characteristics of the fault mode, so that the stored fault injection sequence is encoded and used for quickly calling the encoded fault injection sequence. For example, if the fault mode of a certain low-speed signal is a continuous low-level fault, a normal working channel of the low-speed signal, namely a low-speed signal channel, is designed first when an embedded fault injection module of the low-speed signal is designed, so that the requirement of normal working of a high-speed digital circuit module and a radar digital circuit system where the low-speed signal is located can be met; then designing a circuit of the fault mode submodule, and requiring to realize the grounding processing of the signal, namely realizing the continuous low-level fault mode of the signal; meanwhile, a logic control unit is designed to serve as a control circuit for signal fault injection of the path, namely a low-speed signal fault injection control circuit and a fault mode control logic circuit, so that switching between a working mode and a fault mode of the path of signals is realized; and the writing control of the logic control unit is realized by adopting a control coding mode, and the fault injection of the low-speed signal is completed by utilizing the control coding. The embedded fault injection design of multiple fault modes such as high level, open circuit, short circuit and the like can be realized in the same way. If the same signal has multiple fault modes or multiple signals have similar fault modes, multiple fault modes can be designed in advance, multiple codes are adopted to simultaneously control each fault mode, fault injection sequence signals are read through the control code sequence according to the requirement of simulating fault injection, fault injection data are generated, and fault injection of multiple modes is achieved.

Four, data communication circuit

The data communication circuit is divided into an upper computer communication interface and a fault injection communication circuit. The upper computer communication interface is realized through an RS232 serial port of the MCU chip and is used for receiving a fault mode simulation instruction of the upper computer. The fault injection communication circuit is jointly realized by the MCU and the FPGA, and the MCU receives and analyzes a fault mode simulation instruction of the upper computer and transmits related fault injection information to the FPGA. The communication interfaces between the MCU and the upper computer and between the MCU and the FPGA are different in communication mode and communication protocol.

The MCU writes data for controlling the working mode of the digital cross-point switch chip into a latch memory unit of the digital cross-point switch chip by using the FPGA control bus, thereby realizing programmable control of high-speed channel connectivity output forbidding and equal output current level and input, and further realizing the purposes of fault simulation and fault injection.

After the high-speed digital circuit system which needs to be subjected to fault mode verification is electrified, the default state of the embedded fault injection module is no fault, and the system can normally run. The implementation process of the embedded fault injection method of the high-speed digital circuit of the embodiment is as follows:

(1) and according to the requirement of the fault library verified by the fault mode, when the fault is injected, the upper computer sends a fault mode simulation instruction to the MCU of the embedded fault injection module according to the requirement of the fault library.

(2) And the MCU receives the fault mode simulation instruction, completes instruction analysis and generates a fault injection control instruction to the FPGA.

(3) And the FPGA completes fault injection data configuration according to the received fault injection control instruction, realizes fault simulation, completes signal path control and fault injection control corresponding to the fault injection control instruction, and implements fault injection.

(4) Completing the verification of the failure mode, comprising: after fault injection is carried out, the high-speed digital circuit system injected with the fault has abnormal work, and whether the working state of the high-speed digital circuit system meets the expected effect of the injected fault mode or not is checked; and restoring the high-speed digital circuit module to a fault-free state, and checking whether the high-speed digital circuit system works normally.

(5) And repeating the steps until all the failure modes to be verified and the failure types in the failure library are completely verified.

According to the fault injection requirement, the FPGA chip carries out working mode control and on-off control on the digital cross point switch according to a fault mode simulation instruction in the fault simulation of the high-speed signal, so that the fault injection of the high-speed signal is realized, and the problem that the fault injection of the conventional high-speed serial signal cannot be implemented is solved. The fault simulation of the low-speed signal is directly completed by the FPGA chip, and according to the fault mode simulation instruction, the fault mode submodule is called to generate fault injection data, so that the fault injection is completed on the low-speed signal.

In some embodiments, certain aspects of the techniques described above may be implemented by one or more processors of a processing system executing software. The software includes one or more sets of executable instructions stored or otherwise tangibly embodied on a non-transitory computer-readable storage medium. The software may include instructions and certain data that, when executed by one or more processors, manipulate the one or more processors to perform one or more aspects of the techniques described above. The non-transitory computer-readable storage medium may include, for example, a magnetic or optical disk storage device, a solid state storage device such as flash memory, cache, Random Access Memory (RAM), etc., or other non-volatile memory device. Executable instructions stored on a non-transitory computer-readable storage medium may be in source code, assembly language code, object code, or other instruction format that is interpreted or otherwise executed by one or more processors.

A computer-readable storage medium may include any storage medium or combination of storage media that is accessible by a computer system during use to provide instructions and/or data to the computer system. Such storage media may include, but is not limited to, optical media (e.g., Compact Discs (CDs), Digital Versatile Discs (DVDs), blu-ray discs), magnetic media (e.g., floppy disks, tape, or magnetic hard drives), volatile memory (e.g., Random Access Memory (RAM) or cache), non-volatile memory (e.g., Read Only Memory (ROM) or flash memory), or micro-electromechanical systems (MEMS) -based storage media. The computer-readable storage medium can be embedded in a computing system (e.g., system RAM or ROM), fixedly attached to a computing system (e.g., a magnetic hard drive), removably attached to a computing system (e.g., an optical disk or Universal Serial Bus (USB) based flash memory), or coupled to a computer system via a wired or wireless network (e.g., Network Accessible Storage (NAS)).

Note that not all of the activities or elements in the general description above are required, that a portion of a particular activity or device may not be required, and that one or more further activities or included elements may be performed in addition to those described. Still further, the order in which the activities are listed need not be the order in which they are performed. Moreover, these concepts have been described with reference to specific embodiments. However, one of ordinary skill in the art appreciates that various modifications and changes can be made without departing from the scope of the present disclosure as set forth in the claims below. Accordingly, the specification and figures are to be regarded in an illustrative rather than a restrictive sense, and all such modifications are intended to be included within the scope of present disclosure.

Benefits, other advantages, and solutions to problems have been described above with regard to specific embodiments. However, the benefits, advantages, solutions to problems, and any feature(s) that may cause any benefit, advantage, or solution to occur or become more pronounced are not to be construed as a critical, required, or essential feature of any or all the claims in any or all respects. Moreover, the particular embodiments disclosed above are illustrative only, as the disclosed subject matter may be modified and practiced in different but equivalent manners apparent to those skilled in the art having the benefit of the teachings herein. No limitations are intended to the details of construction or design herein shown, other than as described in the claims below. It is therefore evident that the particular embodiments disclosed above may be altered or modified and all such variations are considered within the scope of the disclosed subject matter. Accordingly, the protection sought herein is as set forth in the claims below.

Claims

1. An embedded fault injection module for fault simulation and fault injection in a high speed digital circuit module of a high speed digital circuitry, comprising:

the fault mode submodule circuit is used for establishing a fault mode submodule according to a fault mode library of the high-speed digital circuit module and storing a fault injection sequence; the fault mode submodule receives an instruction of the fault injection control circuit, reads a stored fault injection sequence, generates fault injection data of a low-speed signal and sends the fault injection data into a related low-speed signal channel;

2. The embedded fault injection module of claim 1, wherein the signal path circuitry comprises high speed signal path circuitry and low speed signal path circuitry; the high-speed signal path circuit completes transmission and communication of high-speed serial signals and is realized by adopting a high-performance digital cross point switch chip, and a control bus signal of the digital cross point switch chip is controlled by an FPGA chip; the low-speed signal path circuit is realized by adopting an FPGA (field programmable gate array), so that the original signal characteristics are unchanged after input and output signals of the low-speed signal path pass through the FPGA.

3. The embedded fault injection module of claim 1, wherein the fault injection control circuit comprises a high-speed signal fault injection control circuit, a low-speed signal fault injection control circuit, and a fault mode control logic circuit; the high-speed signal fault injection control circuit is used for realizing a control bus logic circuit of the digital cross-point switch chip; the low-speed signal fault injection control circuit is used for controlling a low-speed signal path by the FPGA; and the fault mode control logic circuit is used for controlling the fault mode submodule.

4. The embedded fault injection module of claim 2, wherein the MCU writes data controlling the operating mode of the digital cross-point switch chip into the latched memory cells of the digital cross-point switch chip using the FPGA control bus to implement programmable control of high speed channel connectivity output disable, output current level and input equalization.

5. The embedded fault injection module of claim 2, wherein the data transfer rate of the various signals does not exceed a highest data transfer rate of each channel of the digital cross-point switch chip.

6. The embedded fault injection module of claim 2, wherein a plurality of digital crosspoint switch chips are grouped, each group processing a different type of high speed signal; the FPGA controls each digital cross-point switch chip corresponding to each high-speed signal independently and sets each signal mode according to the characteristics of each signal bus.

7. The embedded fault injection module of claim 1, wherein the data communication circuit comprises an upper computer communication interface circuit and a fault injection control communication circuit; the upper computer communication interface circuit receives a fault mode simulation instruction of the upper computer through the MCU; the fault injection control communication circuit is realized by the MCU and the FPGA, and the MCU analyzes a fault mode simulation instruction of the upper computer and transmits related fault injection information to the FPGA.

8. A high-speed digital circuit system for fault injection of a high-speed digital circuit module therein, comprising an embedded fault injection module according to claim 1, wherein the fault injection-enabled high-speed digital circuit module is connected to other circuit modules of the high-speed digital circuit system via the embedded fault injection module.

9. The high-speed digital circuitry according to claim 8, wherein said embedded fault injection module is powered by an independent dc power supply.

10. A high-speed digital circuit embedded fault injection method implemented using a high-speed digital circuitry according to any of claims 8 to 9, comprising the steps of: