CN1117175A - Two-dimensional inverse discrete cosine transformer - Google Patents
Two-dimensional inverse discrete cosine transformer Download PDFInfo
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- CN1117175A CN1117175A CN95101261A CN95101261A CN1117175A CN 1117175 A CN1117175 A CN 1117175A CN 95101261 A CN95101261 A CN 95101261A CN 95101261 A CN95101261 A CN 95101261A CN 1117175 A CN1117175 A CN 1117175A
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Abstract
A novel inverse discrete cosine transformation(IDCT) apparatus performs a two-dimensional IDCT operation on an input signal comprising a data signal and an information signal, wherein said data signal includes a plurality of blocks of transformed coefficients and a multiplicity of time gaps of variable duration, each of said blocks having a multiple number of transformed coefficients and each of said time gaps being inserted between two successive macroblocks and said information signal includes a plurality of block start signal each of which indicates the start of each block. The IDCT apparatus comprises a first one-dimensional IDCT block for performing a one-dimensional IDCT operation on each of the input blocks, to thereby provide each of intermediate blocks; a transposition memory block for storing each of the intermediate blocks and providing each of the transposed intermediate blocks; and a second one-dimensional IDCT block for performing a one-dimensional IDCT operation on each of the transposed intermediate blocks.
Description
The present invention relates to be used for two-dimensional inverse discrete cosine conversion (IDCT) device of digital image processing system, particularly, relate to the IDCT device that to handle by a plurality of block of video data and insert betwixt that the different time intervals forms through the vision signal of conversion.
As everyone knows, the transmission of digitized video can produce than the higher-quality video image of transmission of analogue signal.When the picture intelligence that comprises a series of images " frame " was represented with digital form, producing mass data will transmit, particularly in the high-definition television system occasion.Yet, because the spendable frequency span of normal transmission channel is limited, in order to transmit a large amount of numerical datas by limited channel width, unavoidably to compress or reduce transmit the capacity of data.
Picture intelligence can be compressed and the not serious integrality that influences it usually, because have certain correlativity or redundancy between some pixels of single width frame and between the pixel of each consecutive frame usually.Therefore, image signal encoding method adopts to be based upon and utilizes or dwindle various compress techniques (or coding method) on this redundant notion in most prior aries.
This coding method of one class is relevant with the converter technique that utilization is present in the redundancy in the single width frame.One of this transform method is two-dimension discrete cosine transform (DCT), and it is at Chen and Pratt " Scene Adaptive Coder ", IEEE Transactions on Communication, and Com-32, No.3 has narration in (March 1984).
In resembling the such scheme of ISO/IEC mpeg standard, DCT and other coding methods are used together, as differential pulse code modulation (DPCM) and motion compensated predictive coding method, the latter adopts motion estimation and prediction (to see MPEG Video Simulation Model Three, International Organization for Standardization, Coded Representation of Picture and Audio Information, 1990, ISO-IEC/JTC1/SC2/WG8 MPEG90/041).
In common image encoding system, each frame image signal is divided into several earlier, and its each piece comprises the pixel data of predetermined number, and for example 64, and on the basis of block-by-block, do for example discrete cosine transform and handle.Picture intelligence further processes again, for example, and motion estimation and prediction.The additional signals that is comprised for example, can be inserted between certain two piece that continue about the information of encoding process.After this, the picture intelligence of coding further processes again, as the chnnel coding that is used to send.
On the other hand, in common image decoding system, the picture intelligence that receives by transmission channel is subjected to a series of decoding processing, for example comprises, the re-quantization before channel-decoding, elongated degree decoding, run-length coding and IDCT operation are done.In other words, the signal that is input to the IDCT device is by the vision signal through conversion that inverse quantizer provided that for example is included in the image decoding system.Input signal can comprise a data-signal, and it contains a plurality of, and each piece has the data through conversion of predetermined number, and these data are presented the device to IDCT with fixing speed.To some piece, the time interval of a plurality of different lengths can be inserted between two consecutive blocks of respective number, and wherein gap length can depend on system corresponding to described each additional signal that is inserted in scrambler each time interval.Therefore, data-signal also comprises a plurality of time intervals, and each time interval is inserted between two pieces that continue.
Outside the divisor number of it is believed that, the information signal relevant with the timing of data-signal also is included among the input signal and supplies with the IDCT device.The general example of sort signal is the BOB(beginning of block) signal, and it located to be energized in first input cycle of each piece.
As is generally known common IDCT processor is that the IDCT operation is carried out on the basis with the block-by-block, therefore, have at the form of input or some restrictions regularly.Typically, the data of this conversion should sequentially be added to the IDCT processor with the fixed rate of one of each clock period input data and the time interval should be satisfied some condition.For example, the time interval should be input data number in the clock period multiple or should be greater than the stand-by period.Here the stand-by period of Shi Yonging refers to the beginning the time interval between beginning to its output and defined by the characteristic of IDCT processor of input of piece.
If input signal does not satisfy the described condition that is applied by the IDCT processor, the inside of IDCT processor becomes synchronously and is upset, and the IDCT processor can not produce correct result.
Therefore, because to input signal constraint regularly, IDCT processor of the prior art may become and can not handle the time interval of the different interval length that is inserted between some piece.
Having proposed different schemes overcomes input signal constraint regularly.For example, handle the time interval of inserting the different length between each piece with 2 IDCT processors.Yet, use 2 IDCT processors to bring the price of system to raise.
So fundamental purpose of the present invention provides a kind of IDCT device, it can be handled economically effectively and be inserted into elongated in the middle of one group two pieces that continue and spend the time interval.
According to the present invention, provide a kind of input signal with data-signal and information signal has been carried out two-dimentional IDCT operation to produce the IDCT device of inverse transformation data-signal, wherein said data-signal comprises the time interval of a plurality of transformation coefficient blocks and a plurality of elongated degree, each described has many conversion coefficients, each described time interval is inserted between two pieces that continue, described information signal comprises a plurality of BOB(beginning of block) signals, each this kind signal is indicated the beginning of each piece, and this device comprises:
(a) one first one dimension (1-D) IDCT module is used for responding each BOB(beginning of block) signal each input block is done one dimension IDCT operation, thereby an intermediate mass is provided;
(b) transposition memory module is used for storing intermediate mass and provides intermediate mass through transposition with the response block commencing signal, and it comprises:
(b1) transposition memory controller is used for the response block commencing signal alternately to produce one first group of control signal and one second group of control signal;
(b2) first memory storage, being used to store the odd number intermediate mass and responding described first group of control signal provides odd number intermediate mass through transposition;
(b3) second memory storage, being used to store the even number intermediate mass and responding described second group of control signal provides even number intermediate mass through transposition; And
(b4) device, be used in conjunction with provide by described first memory storage and second memory storage through the intermediate mass of the odd number of transposition with through the intermediate mass of the even number of transposition, thereby intermediate mass through transposition is provided; With
(c) one second one dimension IDCT module is used for responding each BOB(beginning of block) signal each is done one dimension IDCT operation through the intermediate mass of transposition, thereby the inverse transformation data are provided.
Above and other purposes of the present invention and characteristics will become clearer by the narration of the preferred embodiment that provides below in conjunction with accompanying drawing, and these accompanying drawings are:
Fig. 1 represents the block scheme of IDCT device of the present invention;
Fig. 2 is the detailed diagram that is shown in the first one dimension IDCT module of Fig. 1;
Fig. 3 has described the block diagram of the transposition memory module that is shown in Fig. 1;
The draw block diagram of the transposition memory controller that is shown in Fig. 3 of Fig. 4;
Fig. 5 represents the example waveform of various signals used according to the invention.
Giving the input signal of IDCT device 1 of the present invention is the vision signal through conversion of standard form, and it can provide from another parts of the image decoding system as inverse quantizer (end illustrates), and it comprises data-signal and BOB(beginning of block) signal.Data-signal with " input data " representative, has comprised the piece of a plurality of data through conversion in Fig. 1 and Fig. 5, the BOB(beginning of block) signal is represented with DBS, and indication is included in the beginning of each piece in the data-signal.Each piece has predetermined number, and for example 64 transform data has the time interval of different length to be inserted into therebetween to some two pieces that continue.For example, gap length is to be inserted in time interval of G among Fig. 5 between the 2nd and the 3rd.
Data-signal is imported into the first one dimension IDCT module 100, does the one dimension inverse transformation there.Particularly, the predetermined IDCT matrix of coefficients of the first one dimension IDCT module, 100 usefulness takes advantage of input block to carry out one dimension IDCT, thereby an intermediate mass is provided, and this will make an explanation according to Fig. 2.
The intermediate mass that provides by the first one dimension IDCT module 100 in transposition memory module 300 by transposition to be coupled to the second one dimension IDCT module 200.
The work of the second one dimension IDCT module 200 is the same with the first one dimension IDCT module 100 basically, just the IDCT matrix of coefficients be multiply by the intermediate mass rather than the input block of transposition.That is, from the intermediate mass of the transposition of transposition memory module 300 input be the second one dimension IDCT module 200 by the one dimension inverse transformation to form two-dimentional inverse transform block.This piece through two-dimentional inverse transformation is provided for other parts of the decode system as motion compensator.
The BOB(beginning of block) signal also is transfused to being included in each module in the IDCT device 1 to control each module, and this will lay down a definition below.
Referring to Fig. 2, that is the detailed diagram that is shown in the first one dimension IDCT module 100 among Fig. 1.In this first one dimension IDCT module 100, a predetermined IDCT matrix of coefficients multiply by an input block.For matrix-matrix multiple, the first one dimension IDCT module 100 comprises: the module 110 that multiplies each other is used for each IDCT coefficient in the IDCT matrix of coefficients and each input data are multiplied each other; Accumulative total module 120 is used for predetermined number, and for example 8, the long-pending one dimension inverse transformation data of adding up mutually and being included in the intermediate mass that provide by the module 110 that multiplies each other to form; Coefficient generator 115 is used to provide the multiply each other IDCT coefficient of module 110 of suitable being used to; And accumulative total controller 125, be used for producing the control signal that is used to accumulative total module 120.The first one dimension IDCT module 100 also has Postponement module D1117 and D2127, is used to provide the BOB(beginning of block) signal DBS1 and the DBS2 that have postponed a schedule time.DBS1 and DBS2 are used in coefficient generator 115 and accumulative total controller 125 respectively, the timing controlled of be used to multiply each other module 110 and accumulative total module 120.
Referring to Fig. 5, the illustrative waveforms of DBS, DBS1 and DBS2 has been expressed in the there.DBS has been delayed preset time T1 and then has postponed T2 and formed DBS1 and DBS2 respectively, and wherein T1 is the time interval between the starting point of the starting point of input block and the coefficient that is added to the module 110 that multiplies each other.Therefore, coefficient generator 115 response DBS1 begin to provide IDCT coefficient to the module 110 that multiplies each other.In other words, the running of the coefficient generator 115 and the module 110 that multiplies each other is controlled by DBS1.
T2 be input to the module 110 that multiplies each other coefficient starting point and be input to time interval between the long-pending starting point of accumulative total module 120 by the module 110 that multiplies each other.Response DBS2, the content of accumulative total module 120 is eliminated the long-pending accumulative total running of implementing then new input block.So the running of accumulative total module 120 and accumulative total controller 125 is controlled by DBS2.T1 and T2 are scheduled to by system design.The operation of module 110 and accumulative total module 120 owing to multiply each other, each input block is fed to transposition memory module 300 by the one dimension inverse transformation with the formation intermediate mass and with line 150 in each one dimension IDCT100.
Referring to Fig. 3, the there is the block diagram that is shown in the transposition memory module 300 of Fig. 1.The intermediate mass that provides by the first one dimension IDCT module 100 by transposition in transposition memory module 300 to be provided for the second one dimension IDCT module 200.Transposition memory module 300 comprises: two 8 * 8 transposition RAM (random access memory) 310 and 320 are used for alternately storing intermediate mass; Transposition memory controller 330 is used to the write and read operation of two transposition RAM310 and 320 to produce various control signals; And of being used for from transposition RAM of traffic pilot 350 selects output and provides it to the second one dimension IDCT module 200.It also comprises Postponement module D3335, is used to provide DBS3.As shown in Figure 3, DBS3 is produced by DBS delay scheduled time (T1+T2+T3), and wherein (T1+T2+T3) is meant and piece imported the starting point of the first one dimension IDCT module 100 and from the time interval between the starting point of the corresponding intermediate mass of the first one dimension IDCT module 100 output.
For the running of explaining above can be carried out, various control signals, for example AD1, AD2, W/R1 and W/R2 are to producing in transposition memory controller 330 in DBS3.AD1 and AD2 are address signals, be used for the read and write operation of two transposition RAM310 and 320, and Writing/Reading select signal W/R1 and W/R2 to determine the work of transposition RAM310 and 320 respectively.Transposition RAM310 and 320 Be Controlled must make have only transposition RAM to carry out read operation another then does write operation simultaneously.Signal is selected in the address signal that application is narrated above and Writing/Reading, annotates in Fig. 5 to what the intermediate mass through the one-dimensional transform data was deposited in transposition RAM and offers traffic pilot 350 with the order of transposition in the lump.
For example, the first or the 3rd intermediate mass is deposited among the transposition RAM310; And the second or the 4th intermediate mass is deposited among the transposition RAM320.When second intermediate mass is deposited among the transposition RAM320, be provided for traffic pilot 350 through first intermediate mass of transposition.Can see easily that from the oscillogram of the intermediate mass of the intermediate mass that is shown in Fig. 5 and transposition second intermediate mass of transposition is removed therefrom once depositing transposition RAM320 in.So when being fed to transposition RAM310 corresponding to the part of the invalid data of time interval G ' and the 3rd intermediate mass, second intermediate mass of transposition is just taken out from the second transposition RAM320.On the other hand, when the remainder of the 3rd intermediate mass is deposited in transposition RAM310, corresponding to time interval G " invalid data taken out from transposition RAM320, as shown in Figure 5.The transposition data that the selection signal that traffic pilot 350 response warps 340 are provided by transposition memory controller 330 selects the read operation by one of transposition RAM to provide.
W/R2 can be used as the selection signal, wherein, and when W/R2 selects the output of transposition RAM310 during for excited state, and when the output of W/R1 selection transposition RAM320 during for excited state.
The intermediate mass through transposition that is provided by traffic pilot 350 is imported into the second one dimension IDCT module 200.Also comprise as shown in Figure 5 time interval between the second and the 3rd intermediate mass for the input of the second one dimension IDCT module.The 2nd IDCT module 200 is carried out the running the same with the first one dimension IDCT module 100 in fact.
Referring to Fig. 4, the there is the detailed diagram that is shown in the transposition memory controller 330 of Fig. 3.
As previously explained, transposition memory controller 330 produces address signals, the Writing/Reading that is used for two transposition RAM310 and 320 selects signal and be used for the selection signal of traffic pilot 350.Particularly, transposition memory controller 330 comprises demultiplexer 10, is used for DBS3 is divided into DBS30 and the DBS3E that is shown in Fig. 5; And first and second address generation module 50 and 60, being used for responding respectively DBS30 and DBS3E is that transposition RAM310 and 320 produces address signal AD1, AD2 and signal W/R1, W/R2 are selected in Writing/Reading.As shown in FIG. 5, DBS30 indicates the starting point DBS3E of each odd number intermediate mass then to indicate the starting point of each even number intermediate mass.
Refer back to Fig. 5, various signal above-mentioned has drawn.As explained above, the data-signal of representing with " input data " comprises a plurality of data blocks through conversion, and time interval G is inserted between second and the 3rd.The first one dimension IDCT module 100 that is shown in Fig. 1 is carried out one dimension IDCT operation and is produced the intermediate mass that is shown in Fig. 5 in response to DBS1 and DBS2.Because the input data are included in the time interval G between second and the 3rd, the time interval G ' of same length is present between the second and the 3rd intermediate mass, as shown in Figure 5.
DBS30 and DBS3E indicate the initial of odd number and intermediate mass even number respectively.When W/R1 and W/R2 are " 1 " respectively, odd number deposited in the transposition memory module 300 shown in Fig. 1 with intermediate mass even number.When the Writing/Reading of correspondence selects signal be " 0 ", as among Fig. 5 the last capable shown in, intermediate mass is by with the taking out in turn of transposition, and is provided for the second one dimension IDCT module 200.It should be noted that and be designated as G " the invalid data in time interval place be provided for the second one dimension IDCT module 200.Such processing this time interval that the second one dimension IDCT module 200 is explained with reference Fig. 2.As explained above, the second one dimension IDCT module 200 that is shown in Fig. 2 is carried out and the same operation of explaining with reference to Fig. 2 and 5 of the first one dimension IDCT module 100, and provides through two-dimentional inverse transformation data other parts to decode system.
The present invention has described certain embodiments, but those skilled in the art can not deviate from make various changes and modification under the spirit and scope of the present invention defined in claims.
Claims (3)
1, inverse discrete cosine transform (IDCT) device, be used for the input signal with data-signal and information signal is done two-dimentional IDCT operation so that produce the inverse transformation data-signal, wherein said data-signal comprises the time interval of the piece and the multiple elongated degree of a plurality of conversion coefficients, each described has a plurality of conversion coefficients, each described time interval is inserted between two pieces that continue, described information signal comprises a plurality of BOB(beginning of block) signals, and each this kind commencing signal is indicated the beginning of each piece, and this device comprises:
(a) the first one dimension IDCT module is used to respond each BOB(beginning of block) signal each input block is carried out one dimension IDCT operation, thereby intermediate mass is provided;
(b) transposition memory module, being used to store intermediate mass provides intermediate mass through transposition with the response block commencing signal, and it comprises:
(b1) transposition memory controller is used for alternately producing first group of control signal and second group of control signal according to the BOB(beginning of block) signal;
(b2) first memory storage is used to respond the intermediate mass of described first group of control signal storage odd number and intermediate mass through the odd number of transposition is provided;
(b3) second memory storage is used to respond the intermediate mass of described second group of control signal storage even number and intermediate mass through the even number of transposition is provided; With
(b4) device, be used in conjunction with provide by described first and second memory storages through the intermediate mass of the odd number of transposition and through the intermediate mass of the even number of transposition, thereby intermediate mass through transposition is provided; And
(c) the second one dimension IDCT module is used to respond each BOB(beginning of block) signal each is done one dimension IDCT operation through the intermediate mass of transposition, thereby the inverse transformation data are provided.
2, according to the device of claim 1, wherein said first group of control signal comprises having a plurality of predetermined write addresses and a plurality of predetermined first address signal of reading the address and be used to select first of the described first memory storage work to select signal; And described second group of control signal comprises having a plurality of predetermined write addresses and a plurality of predetermined second address signal of reading the address and be used to select second of the described second memory storage work to select signal.
3, according to the device of claim 2, wherein said transposition memory controller has:
Be used to postpone each BOB(beginning of block) signal, thereby the device of a plurality of intermediate mass commencing signals is provided, each respectively beginning of this intermediate mass of intermediate mass commencing signal indication;
The intermediate mass commencing signal is divided into the device of first group of intermediate mass commencing signal and second group of intermediate mass commencing signal, and respectively this first group of signal indicated the beginning of each odd number intermediate mass, and respectively this second group of signal indicated the beginning of each even number intermediate mass;
Module takes place in first address, and being used for responding each intermediate mass commencing signal that is included in first group provides first address signal and first to select signal; And
Module takes place in second address, and being used for responding each intermediate mass commencing signal that is included in second group provides second address signal and second to select signal.
Applications Claiming Priority (2)
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KR1019940000751A KR0130446B1 (en) | 1994-01-18 | 1994-01-18 | Two-dimensional inverse discrete cosine transformer |
KR751/94 | 1994-01-18 |
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CN1117175A true CN1117175A (en) | 1996-02-21 |
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CN95101261A Pending CN1117175A (en) | 1994-01-18 | 1995-01-16 | Two-dimensional inverse discrete cosine transformer |
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EP (1) | EP0667583B1 (en) |
JP (1) | JPH0844709A (en) |
KR (1) | KR0130446B1 (en) |
CN (1) | CN1117175A (en) |
DE (1) | DE69417208T2 (en) |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
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US5894430A (en) | 1996-05-20 | 1999-04-13 | Matsushita Electric Industrial Co., Ltd. | Orthogonal transform processor |
JPH10341438A (en) | 1997-06-09 | 1998-12-22 | Sharp Corp | Image processor |
US6496199B1 (en) * | 1999-10-01 | 2002-12-17 | Koninklijke Philips Electronics N.V. | Method for storing and retrieving data that conserves memory bandwidth |
JP4536109B2 (en) * | 2007-12-26 | 2010-09-01 | 富士通株式会社 | Semiconductor device and signal processing method |
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US4791598A (en) * | 1987-03-24 | 1988-12-13 | Bell Communications Research, Inc. | Two-dimensional discrete cosine transform processor |
DE3837328A1 (en) * | 1988-11-03 | 1990-05-10 | Bosch Gmbh Robert | TRANSFORMATION CIRCUIT |
EP0566184A3 (en) * | 1992-04-13 | 1994-11-17 | Philips Electronics Nv | Picture transformer and television system with a transmitter and a receiver comprising a picture transformer. |
US5289577A (en) * | 1992-06-04 | 1994-02-22 | International Business Machines Incorporated | Process-pipeline architecture for image/video processing |
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1994
- 1994-01-18 KR KR1019940000751A patent/KR0130446B1/en not_active IP Right Cessation
- 1994-12-28 JP JP6338810A patent/JPH0844709A/en active Pending
- 1994-12-29 DE DE69417208T patent/DE69417208T2/en not_active Expired - Fee Related
- 1994-12-29 EP EP94120916A patent/EP0667583B1/en not_active Expired - Lifetime
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1995
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KR950024094A (en) | 1995-08-21 |
KR0130446B1 (en) | 1998-04-15 |
DE69417208T2 (en) | 1999-07-08 |
EP0667583A1 (en) | 1995-08-16 |
JPH0844709A (en) | 1996-02-16 |
DE69417208D1 (en) | 1999-04-22 |
EP0667583B1 (en) | 1999-03-17 |
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