CN111710642A

CN111710642A - Memory element and method for manufacturing the same

Info

Publication number: CN111710642A
Application number: CN201910202942.0A
Authority: CN
Inventors: 陈皇男
Original assignee: Winbond Electronics Corp
Current assignee: Winbond Electronics Corp
Priority date: 2019-03-18
Filing date: 2019-03-18
Publication date: 2020-09-25
Anticipated expiration: 2039-03-18
Also published as: CN111710642B

Abstract

The present invention provides a memory element and a method of manufacturing the same, the memory element including: the semiconductor device includes a substrate, a plurality of contact windows, and a plurality of air gaps. The substrate has a plurality of active regions. The contact windows are respectively configured on the end points of the active regions. The air gaps respectively surround the side walls of the contact windows.

Description

Memory element and method for manufacturing the same

Technical Field

The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a memory device and a method of manufacturing the same.

Background

A Dynamic Random Access Memory (DRAM), which is a type of volatile memory, each memory cell is mainly composed of a transistor and a capacitor controlled by the transistor, and is electrically connected to a corresponding bit line and a word line.

With the progress of technology, various electronic products are developed towards the trend of being light, thin, short and small. However, under the trend, the critical dimension of DRAM is also gradually reduced, which results in an increase in capacitance between the bit line and the contact, resulting in a slower RC Delay (RC Delay), thereby affecting the operation speed of the device.

Disclosure of Invention

The invention provides a memory element and a manufacturing method thereof, which is provided with an air gap surrounding a contact window so as to reduce the capacitance between a bit line and the contact window and further increase the operating speed of the memory element.

The present invention provides a memory element including: the semiconductor device includes a substrate, a plurality of contact windows, and a plurality of air gaps. The substrate has a plurality of active regions. The contact windows are respectively configured on the end points of the active regions. The air gaps respectively surround the side walls of the contact windows.

The invention provides a method for manufacturing a memory element, which comprises the following steps. Providing a substrate, wherein the substrate is provided with a plurality of first areas and a plurality of second areas; forming a plurality of word line groups in the first region; forming a first dielectric layer on the substrate in the first region; forming a conductor layer on the substrate in the second area, wherein the top surface of the conductor layer is lower than the top surface of the first dielectric layer; forming a sacrificial layer surrounding the conductor layer; conformally forming a second dielectric layer on the substrate; performing an etching process to form an opening in the conductor layer and the second dielectric layer of the second region, wherein the opening exposes the first isolation structure in the substrate of the second region; forming a second isolation structure in the opening; performing a planarization process to expose the sacrificial layer; recessing a portion of the conductive layer to form a first conductive structure and expose the sacrificial layer; removing the sacrificial layer to form an air gap around an upper portion of the first conductor structure; and forming a second conductor structure on the first conductor structure to encapsulate the air gap.

The invention provides another manufacturing method of a memory element, which comprises the following steps. Providing a substrate, wherein the substrate is provided with a plurality of active regions; forming a first dielectric layer on a substrate; forming a plurality of contact window openings in the first dielectric layer, wherein the contact window openings are respectively configured on the end points of the active region; forming a plurality of conductor layers in the contact window openings respectively; forming a sacrificial layer to surround the conductor layer; recessing a portion of the conductor layer to form a first conductor structure; removing the sacrificial layer to form an air gap around an upper portion of the first conductor structure; and forming a second conductor structure on the first conductor structure to encapsulate the air gap.

In view of the above, the memory device of the present invention includes an air gap surrounding the sidewall of the contact, which can reduce the capacitance between the bit line and the contact and reduce the rc delay, thereby increasing the operating speed of the memory device.

In order to make the aforementioned and other features and advantages of the invention more comprehensible, embodiments accompanied with figures are described in detail below.

Drawings

FIG. 1 is a schematic top view of a memory element according to a first embodiment of the present invention;

FIGS. 2A to 2N are schematic cross-sectional views of a manufacturing process of a memory device along line A-A' of FIG. 1;

FIGS. 3A to 3N are schematic cross-sectional views of a manufacturing process of a memory device along line B-B' of FIG. 1;

FIG. 4 is a schematic top view of a memory element according to a second embodiment of the present invention;

FIGS. 5A to 5J are schematic cross-sectional views of a manufacturing process of a memory device along the line C-C' of FIG. 4;

fig. 6A to 6J are schematic cross-sectional views of a manufacturing process of the memory device along the line D-D' of fig. 4.

Detailed Description

The present invention will be described more fully with reference to the accompanying drawings of the present embodiments. The present invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. The thickness of layers and regions in the drawings may be exaggerated for clarity. The same or similar element numbers refer to the same or similar elements, and the description thereof will not be repeated in the following paragraphs.

Referring to fig. 1, the present embodiment provides a memory device 1 including: the memory device includes a substrate 100, an isolation structure 101, a plurality of active regions AA, a plurality of bit line structures 102, a plurality of word line groups 202, and a plurality of capacitor contacts CC. For clarity, fig. 1 only shows the above components, and other structures can be seen in the subsequent cross-sectional views of fig. 2A to 2N and fig. 3A to 3N.

As shown in fig. 1, the substrate 100 includes a plurality of first regions R1 and a plurality of second regions R2. The first region R1 and the second region R2 are arranged with each other along the first direction D1. The isolation structure 101 is disposed in the substrate 100 to define a plurality of Active Areas (AA) in the substrate 100. In other words, there is an isolation structure 101 between two adjacent active regions AA. In one embodiment, only one memory cell is formed on one active area AA, and the memory cells are separated by the isolation structure 101, so as to effectively reduce the interference problem between the memory cells. In detail, the active areas AA are configured in a stripe shape and arranged in an array. In the present embodiment, the active areas AA are arranged in 3 active area columns (active area columns) AC 1-AC 3, and two adjacent active area columns are arranged in a mirror image. For example, the long side direction of the active area row AC3 is non-orthogonal to the first direction D1 with an angle θ, and the long side direction of the active area row AC2 is non-orthogonal to the first direction D1 with an angle (180 ° - θ). The included angle θ may be between 15 degrees and 75 degrees. In other embodiments, two adjacent active region rows may also be of the same configuration.

The bit line structure 102 is disposed on the substrate 100 and traverses the first region R1 and the second region R2. The bit line structures 102 extend along the first direction D1 and are mutually arranged along the second direction D2. The word line group 202 is located in the substrate 100 of the first region R1. The word line groups 202 extend along the second direction D2 and are mutually arranged along the first direction D1. Each word line group 202 has two buried

word lines

202a, 202 b. In one embodiment, the first direction D1 and the second direction D2 are different and substantially perpendicular to each other.

In the present embodiment, each active area AA has a long side L1 and a short side L2, and the long side L1 crosses the corresponding word line group 202(202a, 202 b). Each active area AA has a bit line contact (not shown) at the overlap with the corresponding bit line structure 102. Thus, each bitline structure 102 can electrically connect a corresponding doped region (not shown) between two buried

wordlines

202a, 202b by using a bitline contact while traversing the corresponding set of wordlines 202.

As shown in fig. 1, capacitor contacts CC are disposed at two ends of the long side L1 of the active area AA, respectively, and electrically connect the active area AA and a capacitor (not shown) to be formed later. From another perspective, the bitline structures 102 are respectively disposed between the capacitor contacts CC at two ends of the long side L1 of the active area AA. The word line groups 202 are respectively disposed in the substrate 100 between two capacitor contacts CC adjacent in the transverse direction (i.e., the first direction D1). In addition, dielectric pillars 132 (which may also be referred to as isolation structures) are disposed on the substrate 100 between the bit line structures 102 to separate or electrically isolate the capacitor contacts CC on the adjacent active areas AA. The dielectric pillars 132 correspond to the isolation structures 101. In some embodiments, the bottom area of the dielectric pillar 132 is smaller than or equal to the top area of the isolation structure 101 to ensure the largest contact area between the capacitor contact CC and the active area AA.

Note that the memory element 1 further includes: a plurality of air gaps AG respectively surround the sidewalls of the capacitor contacts CC. The air gap AG surrounds three sidewalls of the capacitor contact CC, and the other sidewall is covered by the dielectric pillar 132. As shown in fig. 1, the air gap AG extends between sidewalls of two bit line structures 102 adjacent to each other in the longitudinal direction (i.e., the second direction D2). That is, the air gap AG extends from one sidewall of the bit line structure 102 and covers to the other sidewall of the longitudinally adjacent bit line structure 102. Since the dielectric constant of the air gap AG approaches 1, the air gap AG can reduce the capacitance between the bit line structure 102 and the capacitor contact CC and reduce the RC delay, thereby increasing the operation speed of the memory device 1. In addition, although the capacitor contact CC is shown as rectangular in fig. 1, the contact formed may be slightly circular and may be sized according to the process requirements. In addition, although the word line group 202 is shown in FIG. 1 to be separated from the air gap AG by a certain distance, the invention is not limited thereto. In other embodiments, the air gap AG or the capacitor contact window CC may partially overlap with the word line group 202 in the top view.

Referring to fig. 1, fig. 2A and fig. 3A, the present embodiment provides a method for manufacturing a memory device 1, which includes the following steps. First, an initial structure is provided, which includes the substrate 100, the isolation structure 101, and the plurality of word line sets 202.

As shown in fig. 1 and 2A, a plurality of word line groups 202 are disposed in the substrate 100 in the first region R1. Each word line group 202 includes two buried

word lines

202a, 202 b. The buried

word lines

202a, 202b include

gates

204a, 204b and gate

dielectric layers

206a, 206 b.

Gate dielectric layers

206a, 206b surround the

gates

204a, 204b to electrically isolate the

gates

204a, 204b from the substrate 100. In addition, the initial structure further includes

dielectric layers

208a and 208b respectively disposed on the embedded

word lines

202a and 202 b.

As shown in fig. 2A, a dielectric layer 212 (which may be referred to as a first dielectric layer) is formed on the initial structure (or substrate 100) of the first region R1. A dielectric layer 210 is also provided between the dielectric layer 212 and the substrate 100. In one embodiment, the material of the

dielectric layers

210, 212 comprises silicon nitride, which may be formed by CVD. The

dielectric layers

210 and 212 expose the substrate 100 and the isolation structure 101 of the second region R2 to form the opening 10.

Referring to fig. 1 and 3A, a plurality of bit line structures 102 are formed on an initial structure. In fig. 3A, the bitline structure 102 includes, from bottom to top, a dielectric layer 104, a bitline 106, and a cap layer 108. The first spacers 110 cover sidewalls of the bit lines 106 and sidewalls of the cap layer 108. The second spacer 112 covers the sidewalls of the first spacer 110 and the sidewalls of the dielectric layer 104. On the other hand, the bitline structure 102 includes, from bottom to top, a bitline contact (not shown), a bitline 110 and a cap layer 108 in a cross-section along the active area AA. The bitline structure 102 may be electrically connected to a source region AA (i.e., a source/drain doped region) through a bitline contact (not shown).

As shown in fig. 3A, after forming the second spacers 112 of the first spacers 110, the bit line structures 102 have a plurality of openings 10 therebetween. The opening 10 exposes at least a top surface of the substrate 100 (or the active area AA). As shown in fig. 2A and 3A, the opening 10 is defined by the substrate 100, the

dielectric layers

210 and 212, and the bit line structure 102.

Referring to fig. 2B and fig. 3B, a conductive material 114 is formed on the initial structure (or the substrate 100). The conductive material 114 fills the opening 10 and extends to cover the top surface of the bit line structure 102 and the top surface of the dielectric layer 212.

Referring to fig. 2B-2C and fig. 3B-3C, an etch-back process is performed to remove a portion of the conductive material 114, so as to form a conductive material 124 (which may be referred to as a first conductive material) with a smaller thickness in the opening 10. In one embodiment, as shown in FIG. 3C, the top surface of conductive material 124 is lower than the bottom surface of bit line 106. In other embodiments, the top surface of conductive material 124 is between the bottom surface of bit line 106 and the top surface of substrate 100.

Referring to fig. 2D and fig. 3D, a sacrificial material 116 is formed on the substrate 100. The sacrificial material 116 conformally covers the dielectric layer 212, the bit line structures 102, and the conductor material 124. In one embodiment, the material of the sacrificial material 116 includes silicon oxide, and the forming method may be Atomic Layer Deposition (ALD).

Referring to fig. 2D-2E and fig. 3D-3E, an etch back process is performed to remove a portion of the sacrificial material 116 to expose the top surface of the conductive material 124 and the top surface of the dielectric layer 212. In this case, as shown in fig. 2E and 3E, the remaining sacrificial material 116a (hereinafter referred to as sacrificial layer 116a) is disposed on the conductive material 124 and extends along the sidewall of the opening 10.

Referring to fig. 2F and fig. 3F, a conductive material 118 is formed on the conductive material 124. Specifically, the conductive material 118 fills the opening 10 and extends to cover the top surface of the bit line structure 102 and the top surface of the dielectric layer 212. The conductor material 118 may be polysilicon and may be formed by CVD.

Referring to fig. 2F-2G and fig. 3F-3G, an etch-back process is performed on the conductive material 118 to remove a portion of the conductive material 118, so as to form a conductive material 128 (which may be referred to as a second conductive material) with a smaller thickness in the opening 10. In this case, a conductor material 128 is formed on the conductor material 124 to form the conductor layer 120. Sacrificial layer 116a is disposed on conductive material 124 and surrounds sidewalls of conductive material 128. As shown in fig. 2G, the top surface of the conductor layer 120 (or the conductor material 128) is lower than the top surface of the dielectric layer 212. On the other hand, as shown in FIG. 3G, the conductor material 128 extends over the top surface of the bit line structure 102.

Referring to fig. 2H and fig. 3H, a dielectric layer 126 (which may be referred to as a second dielectric layer) is conformally formed on the substrate 100. The dielectric layer 126 conformally covers the conductor material 128 and the dielectric layer 212. The top surface of the dielectric layer 126 may be, for example, a continuous concave-convex structure due to the height difference between the top surface of the conductive material 128 and the top surface of the dielectric layer 212. In other words, the dielectric layer 126 has a rugged top surface, and the top surface of the dielectric layer 126 of the second region R2 is lower than the top surface of the dielectric layer 126 of the first region R1. Specifically, the dielectric layer 126 on the dielectric layer 212 is a convex portion; and the dielectric layer 126 over the conductive material 128 is a recess. As shown in fig. 2H, the dielectric layer 126 of the second region R2 has a recess opening 12 thereon, and the recess opening 12 corresponds to the insulating structure 101 in the substrate 100. In one embodiment, the material of the dielectric layer 126 may be silicon nitride.

Referring to fig. 2H-2I and fig. 3H-3I, the opening 12 is extended to form an opening 14 exposing the insulating structure 101. Specifically, an etching process is performed to remove a portion of the dielectric layer 126 and a portion of the conductive layer 120, so as to form an opening 14 in the conductive layer 120a and the dielectric layer 126a of the second region R2. The opening 14 corresponds to and exposes the insulating structure 101 of the second region R2. In addition, the above etching process also includes removing the dielectric layer 126 in the first region R1 to expose the top surface of the dielectric layer 212. In addition, the dielectric layer 126 of fig. 3H is also thinned to the dielectric layer 126a of fig. 3I. On the other hand, the opening 14 separates one conductor layer 120 into two conductor layers 120 a. Since the opening 14 does not require a lithography process to align the insulating structure 101 of the second region R2, the opening 14 can be considered as a self-aligned opening.

Referring to fig. 2J and fig. 3J, a dielectric material 122 is formed on the substrate 100. The dielectric material 122 fills the opening 14 and covers the top surface of the dielectric layer 126 a. In one embodiment, the dielectric material 122 comprises silicon nitride, which may be formed by CVD.

Referring to fig. 2J-2K and fig. 3J-3K, a planarization process is performed to remove a portion of the dielectric material 122, a portion of the dielectric layer 212, the dielectric layer 126a, and a portion of the sacrificial layer 116a to stop on the top surface of the conductive material 128 a. In one embodiment, the planarization process may be a Chemical Mechanical Polishing (CMP) process or a blanket etch back (blanket back) process. In this case, as shown in fig. 2K, the dielectric posts 132 are formed in the openings 14 (shown in fig. 2I). The dielectric pillar 132 (which may be regarded as a second isolation structure) contacts the isolation structure 101 (which may be regarded as a first isolation structure) and separates the conductive layer 120a and the sacrificial layer 116b on the second region R2. In addition, in fig. 2K, the sacrificial layer 116b is exposed from the conductive layer 120 a.

Referring to fig. 2K-2L and fig. 3K-3L, portions of the conductive material 128a are recessed to expose the sacrificial layer 116b between the bit line structures 102. In this case, as shown in fig. 2L and 3L, a conductor structure 120b (which may be regarded as a first conductor structure) is formed. Specifically, the conductor structure 120b includes a conductor material 124a and a conductor material 128b thereon, wherein the sacrificial layer 116b surrounds sidewalls of the conductor material 128 b. In one embodiment, recessing the conductive material 128a includes performing a wet etch process. The wet etch process uses an etchant with a high etch selectivity that removes most of the conductive material 128a without removing or only slightly removing the dielectric layer 212, the dielectric posts 132, and the sacrificial layer 116 b. In this case, the sacrificial layer 116b between the bit line structures 102 is exposed to the conductor structure 120 b.

Referring to fig. 2L-2M and fig. 3L-3M, the sacrificial layer 116b is completely removed to form an air gap AG surrounding the upper portion of the conductor structure 120b (i.e., the conductor material 128 b). In one embodiment, the method of completely removing the sacrificial layer 116b includes performing a wet etching process, for example, using an etching solution containing hydrofluoric acid (HF), diluted hydrofluoric acid (DHF), buffered oxide etching solution (BOE), etc. The etchant removes the sacrificial layer 116b of silicon oxide without removing or only slightly removing the dielectric layer 212 and the dielectric pillars 132.

Referring to fig. 2M-2N and fig. 3M-3N, another conductor structure 220 is formed on the conductor structure 120b to encapsulate the air gap AG. Specifically, the conductor structure 220 includes a barrier layer 222 and a metal layer 224, wherein the barrier layer 222 covers the metal layer 224. In one embodiment, the material of the barrier layer 222 includes a barrier metal, which may be, for example, Ti, TiN, Ta, TaN, or a combination thereof. The material of the metal layer 224 includes a metal, which may be, for example, W. In this case, as shown in fig. 2N, the conductor structure 120b and the conductor structure 220 thereon may constitute a capacitor contact CC. In one embodiment, the material of the conductor structure 120b is different from the material of the conductor structure 220.

It is noted that, as shown in fig. 2N, the conductor structure 120b includes a lower portion 124a and an upper portion 128 b. In one embodiment, the bottom width of the lower portion 124a is greater than the bottom width of the upper portion 128b, as shown in FIG. 3N. In this case, the air gap AG surrounds the upper portion 128b of the conductor structure 120b so that the cross-sectional profile of the conductor structure 120b is inverted T-shaped. In the present embodiment, the air gap AG not only can reduce the capacitance between the bit line structure 102 and the capacitor contact CC, but also can not sacrifice the contact area between the capacitor contact CC and the active area AA, thereby increasing the operation speed of the memory device 1 and improving the device reliability. Furthermore, in some embodiments, the bottom area of the dielectric pillar 132 is smaller than or equal to the top area of the isolation structure 101, so as to ensure the largest contact area between the capacitor contact CC and the active area AA, as shown in fig. 2N.

Fig. 4 is a schematic top view of a memory element according to a second embodiment of the present invention.

Referring to fig. 4, basically, the memory device 2 of the second embodiment is similar to the memory device 1 of the first embodiment. The difference between the two is as follows: from another perspective, the long side L1 of the active area AA crosses both word lines 402. The capacitor contacts CC' are disposed at both ends of the long side L1 of the active area AA, respectively. It is noted that the memory element 2 further includes a plurality of air gaps AG completely surrounding the sidewalls of the capacitor contact CC 'to reduce the capacitance between the bit line structure 102 and the capacitor contact CC' and reduce the RC delay, thereby increasing the operation speed of the memory element 2.

Referring to fig. 4, fig. 5A and fig. 6A, the present embodiment provides a method for manufacturing a memory device 2, which includes the following steps. First, an initial structure is provided, which includes the substrate 100, the isolation structure 101, and the plurality of word lines 402. The isolation structure 101 is disposed in the substrate 100 to separate the substrate 100 into a plurality of active regions AA. As shown in fig. 5A, a plurality of word lines 402 are disposed in the substrate 100 in the first region R1. In detail, each word line 402 includes a gate 404 and a gate dielectric layer 406 surrounding the gate 404. In addition, the word lines 402 outside the active area AA are disposed in the isolation structure 101. In addition, the initial structure further includes dielectric layers 408 respectively disposed on the word lines 402.

As shown in fig. 5A, a dielectric layer 412 is formed on the substrate 100, and an opening 20 (which may be referred to as a contact opening) is formed in the dielectric layer 412. The openings 20 are respectively disposed on both ends of the active region AA. As shown in fig. 6A, the opening 20 is also disposed between the bit line structures 102. That is, the opening 20 is defined by the substrate 100, the dielectric layer 412 and the bit line structure 102.

Referring to fig. 5B and fig. 6B, a conductive material 314 is formed on the initial structure (or the substrate 100). The conductive material 314 fills the opening 10 and extends to cover the top surface of the bit line structure 102 and the top surface of the dielectric layer 412.

Referring to fig. 5B-5C and fig. 6B-6C, an etch-back process is performed to remove a portion of the conductive material 314, so as to form a conductive material 324 (which may be referred to as a first conductive material) with a smaller thickness in the opening 20.

Referring to fig. 5D and fig. 6D, a sacrificial material 316 is formed on the substrate 100. Sacrificial material 316 conformally covers dielectric layer 412, bitline structures 102, and conductor material 324.

Referring to fig. 5D-5E and 6D-6E, an etch back process is performed to remove a portion of sacrificial material 316 to expose a top surface of conductive material 324 and a top surface of dielectric layer 412. In this case, as shown in fig. 5E and 6E, the remaining sacrificial material 316a (hereinafter referred to as sacrificial layer 316a) is disposed on the conductive material 324 and extends along the sidewalls of the opening 20.

Referring to fig. 5F and fig. 6F, a conductive material 318 is formed on the conductive material 324. Specifically, the conductive material 318 fills the opening 20 and extends to cover the top surface of the bit line structure 102 and the top surface of the dielectric layer 412.

Referring to fig. 5F-5G, a planarization process is performed to remove a portion of the conductive material 318, a portion of the dielectric layer 412, and a portion of the sacrificial layer 316 a. In this case, conductor material 328 is formed over conductor material 324 to form conductor layer 320. Sacrificial layer 316a is disposed on conductor material 324 and surrounds sidewalls of conductor material 328. In addition, as shown in fig. 6F-6G, the planarization process also removes a portion of the cap layer 108, a portion of the first spacer 110, and a portion of the second spacer 112. After the planarization process, as shown in fig. 5G and 6G, the sacrificial layer 316b is exposed out of the conductive layer 320 and the bit line structure 102.

Referring to fig. 5G-5H and fig. 6G-6H, a portion of the conductive material 328 is recessed to expose the sidewalls of the sacrificial layer 316 b. In this case, as shown in fig. 5H and 6H, a conductor structure 320a (which may be regarded as a first conductor structure) is formed. Specifically, conductor structure 320a includes conductor material 324 and conductor material 328a thereover, with sacrificial layer 316b surrounding sidewalls of conductor material 328 a.

Referring to fig. 5H-5I and fig. 6H-6I, the sacrificial layer 316b is completely removed to form an air gap AG' completely surrounding the upper portion of the conductor structure 320a (i.e., the conductor material 328 a).

Referring to fig. 5I-5J and fig. 6I-6J, another conductor structure 420 is formed on the conductor structure 320a to encapsulate the air gap AG'. Specifically, the conductor structure 420 includes a barrier layer 422 and a metal layer 424, wherein the barrier layer 422 covers the metal layer 424. In this case, as shown in fig. 6J, the conductor structure 320a and the conductor structure 420 thereon may constitute a capacitor contact CC'. The conductor structure 320a includes a lower portion 324 and an upper portion 328 a. The air gap AG' surrounds the upper portion 328a of the conductor structure 320a such that the cross-sectional profile of the conductor structure 320a is inverted T-shaped. In the present embodiment, the air gap AG ' not only can reduce the capacitance between the bit line structure 102 and the capacitor contact CC ', but also can not sacrifice the contact area between the capacitor contact CC ' and the active area AA, thereby increasing the operation speed of the memory device 2 and improving the device reliability.

In summary, the memory device of the present invention includes an air gap surrounding the sidewall of the contact, which can reduce the capacitance between the bit line and the contact and reduce the rc delay, thereby increasing the operating speed of the memory device. In addition, the memory element of the invention can still maintain the contact area between the contact window and the active region when reducing the resistance-capacitance delay, thereby improving the element reliability.

Although the present invention has been described with reference to the above embodiments, it should be understood that various changes and modifications can be made therein by those skilled in the art without departing from the spirit and scope of the invention.

Claims

1. A memory element, comprising:

a substrate having a plurality of active regions;

a plurality of contact windows respectively configured on the end points of the active region; and

and a plurality of air gaps respectively surrounding the side walls of the contact windows.

2. The memory element of claim 1, wherein each of the contact windows comprises:

a first conductor structure;

a second conductor structure disposed on the first conductor structure, wherein a material of the second conductor structure is different from a material of the first conductor structure,

wherein the first conductor structure comprises a lower portion and an upper portion, and the air gap surrounds the upper portion of the first conductor structure so that the cross-sectional profile of the first conductor structure is in an inverted T shape.

3. The storage element of claim 2, wherein a bottom width of the lower portion is greater than a bottom width of the upper portion.

4. The storage element of claim 2, wherein the air gap completely surrounds the upper portion of the first conductor structure.

5. The memory element of claim 1, further comprising:

a plurality of bit line structures respectively disposed between the contact windows at the end points of the active region and extending along a first direction; and

and a plurality of word lines respectively arranged between two adjacent contact windows in the first direction and extending along a second direction, wherein the second direction is different from the first direction.

6. The storage element of claim 5, wherein the air gap extends between sidewalls of two bit line structures that are adjacent in the second direction.

7. The memory element of claim 1, further comprising:

the isolation structures are respectively arranged between two active regions adjacent to each other in a first direction so as to electrically isolate the contact windows on the two active regions adjacent to each other in the first direction.

8. A method of manufacturing a memory element, comprising:

providing a substrate, wherein the substrate is provided with a plurality of first areas and a plurality of second areas;

forming a plurality of word line groups in the first region;

forming a first dielectric layer on the substrate of the first region;

forming a conductor layer on the substrate in the second region, wherein a top surface of the conductor layer is lower than a top surface of the first dielectric layer;

forming a sacrificial layer surrounding the conductor layer;

conformally forming a second dielectric layer on the substrate;

performing an etching process to form an opening in the conductor layer and the second dielectric layer of the second region, wherein the opening exposes the first isolation structure in the substrate of the second region;

forming a second isolation structure in the opening;

carrying out a planarization process to expose the sacrificial layer;

recessing a portion of the conductor layer to form a first conductor structure and expose the sacrificial layer;

removing the sacrificial layer to form an air gap around an upper portion of the first conductor structure; and

forming a second conductor structure on the first conductor structure to encapsulate the air gap.

9. The manufacturing method of a memory element according to claim 8, wherein the step of forming the sacrifice layer so as to surround the conductor layer comprises:

forming a first conductor material on the substrate of the second region;

forming a sacrificial material to conformally cover the first conductor material and the first dielectric layer;

removing a portion of the sacrificial material to form the sacrificial layer and expose a top surface of the first conductor material and a top surface of the first dielectric layer; and

a second conductor material is formed on the first conductor material such that the sacrificial layer surrounds sidewalls of the second conductor material.

10. The method for manufacturing a memory element according to claim 8, wherein after the second dielectric layer is formed, the second dielectric layer has a rugged top surface in which a top surface of the second dielectric layer of the second region is lower than a top surface of the second dielectric layer of the first region.

11. The method of claim 8, wherein the etching process includes removing a portion of the second dielectric layer in the first region to expose a top surface of the first dielectric layer.

12. The method for manufacturing a memory element according to claim 8, wherein the second isolation structure contacts the first isolation structure and separates the conductor layer and the sacrificial layer on the second region.

13. A method of manufacturing a memory element, comprising:

providing a substrate, wherein the substrate is provided with a plurality of active regions;

forming a first dielectric layer on the substrate;

forming a plurality of contact window openings in the first dielectric layer, wherein the contact window openings are respectively configured on the end points of the active region;

forming a plurality of conductor layers in the contact window openings respectively;

forming a sacrificial layer to surround the conductor layer;

recessing a portion of the conductor layer to form a first conductor structure;

14. The manufacturing method of a memory element according to claim 13, wherein the step of forming the sacrifice layer so as to surround the conductor layer comprises:

forming a first conductor material in the contact window opening;

15. The method of manufacturing a memory element according to claim 14, wherein the air gap completely surrounds the upper portion of the first conductor structure after the sacrificial layer is completely removed.