CN111710298A

CN111710298A - Pixel circuit, driving method thereof and display panel

Info

Publication number: CN111710298A
Application number: CN202010600387.XA
Authority: CN
Inventors: 王玲; 盖翠丽; 米磊; 卓然然; 张兵; 丁立薇
Original assignee: Yungu Guan Technology Co Ltd
Current assignee: Yungu Guan Technology Co Ltd
Priority date: 2020-06-28
Filing date: 2020-06-28
Publication date: 2020-09-25
Anticipated expiration: 2040-06-28
Also published as: CN111710298B

Abstract

The embodiment of the invention discloses a pixel circuit, a driving method thereof and a display panel.A grid electrode of a driving transistor is coupled to a preset voltage through a coupling module in a characteristic writing stage, and a data voltage is written into a first pole of the driving transistor through a data writing module, wherein the difference value between the preset voltage and the data voltage is opposite to the voltage difference value between the grid electrode of the driving transistor and the first pole when the driving transistor is conducted; in the characteristic recovery stage, the threshold voltage drift degree of the driving transistor is recovered to a certain extent, the threshold voltage drift amount is pulled back, and the threshold voltage drift of the driving transistor can be reduced. And the characteristic recovery stage is before the data writing stage, so that the drift degree of the threshold voltage of the driving transistor is minimum after the characteristic recovery stage in each frame, and further, the compensation module can fully compensate the threshold voltage of the driving transistor within the limited time of the data writing stage, and the display uniformity is improved.

Description

Pixel circuit, driving method thereof and display panel

Technical Field

The embodiment of the invention relates to the technical field of display, in particular to a pixel circuit, a driving method thereof and a display panel.

Background

With the development of display technology, people have higher and higher requirements on display effects.

In the conventional display panel, a plurality of pixel circuits are usually included, and the pixel circuits usually include a driving transistor and a light emitting device, and the driving transistor generates a driving current to control the light emitting luminance of the light emitting device.

However, the conventional display panel has the problems of uneven display and poor display effect.

Disclosure of Invention

The invention provides a pixel circuit, a driving method thereof and a display panel, which aim to reduce threshold voltage drift of a driving transistor, slow down aging speed of a device of the driving transistor, improve display uniformity and further improve display effect.

In a first aspect, an embodiment of the present invention provides a pixel circuit, including: the device comprises a data writing module, a compensation module, a light emitting control module, a driving transistor, a coupling module, a light emitting module and a first initialization module;

the data writing module is used for writing data voltage into the first pole of the driving transistor in a characteristic recovery phase and a data writing phase;

the coupling module is used for coupling the electric potential of the grid electrode of the driving transistor to a preset voltage in a characteristic recovery stage, wherein the difference value between the preset voltage and the data voltage is opposite to the positive and negative of the voltage difference value between the grid electrode of the driving transistor and the first pole when the driving transistor is conducted;

the first initialization module is used for writing initialization voltage into the grid electrode of the driving transistor in an initialization stage; in one frame, the characteristic recovery stage is before the initialization stage;

the compensation module is used for writing a compensation signal containing the threshold voltage information of the driving transistor into the grid electrode of the driving transistor in a data writing stage;

the driving transistor is used for generating a driving signal according to the voltage of the grid electrode of the driving transistor and the voltage of the first electrode of the driving transistor in a light-emitting stage, and the light-emitting control module is used for controlling the driving signal to be output to the light-emitting module in the light-emitting stage.

Optionally, the first end of the coupling module is electrically connected to the gate of the driving transistor, the second end of the coupling module is electrically connected to the coupling control signal end, and the coupling control signal end is configured to input a preset timing signal to the second end of the coupling module in the characteristic recovery stage, where the preset timing signal jumps from the first voltage signal to the second voltage signal in the characteristic recovery stage so that the gate of the driving transistor is coupled to the preset voltage.

Optionally, a control end of the data writing module is electrically connected to a first scanning signal input end, the first scanning signal input end is used for accessing a first scanning signal, a first end of the data writing module is electrically connected to a data voltage input end, and a second end of the data writing module is electrically connected to a first electrode of the driving transistor;

the first scanning signal is an m pulse signal, and m is an integer greater than or equal to 2.

Optionally, the control end of the first initialization module is electrically connected to the second scan signal input end, the second scan signal input end is used for inputting a second scan signal, the first end of the first initialization module is electrically connected to the initialization voltage input end, and the second end of the first initialization module is electrically connected to the first pole of the driving transistor;

the second scanning signal and the first scanning signal are output by the same scanning circuit, the scanning circuit comprises a plurality of cascaded shifting registers, wherein the j-th-stage shifting register is used for outputting the j-th-stage scanning signal, j is more than or equal to 1 and less than or equal to n, and j represents the total stage number of the shifting registers;

the second scan signal is a first 1-level scan signal of the first scan signal.

Optionally, the pixel circuit further includes a third scan signal, where the third scan signal input end is used as a coupling control signal end, the third scan signal input end is used for accessing a third scan signal, and the third scan signal is a single pulse signal;

the single pulse signal of the third scan signal overlaps with any one of the first (m-1) pulse signals of the second scan signal.

Optionally, the pixel circuit further includes a third scan signal input terminal, where the third scan signal input terminal is used as the coupling control signal, and the third scan signal input terminal is used for inputting a third scan signal; the third scanning signal, the first scanning signal and the second scanning signal are output by the same scanning circuit; the third scanning signal is a front (2a-1) level scanning signal of the first scanning signal, wherein a is more than or equal to 2 and less than or equal to m, and a is an integer; in one frame, the interval time between the falling edges of two adjacent pulse signals of the first scanning signal is equal to the scanning time of two rows of pixel circuits.

Optionally, the coupling module includes a capacitor;

optionally, a control end of the data writing module is electrically connected to the first scanning signal input end, a first end of the data writing module is electrically connected to the data voltage input end, and a second end of the data writing module is electrically connected to the first electrode of the driving transistor;

the first end of the coupling module is electrically connected with the grid electrode of the driving transistor, the second end of the coupling module is electrically connected with the coupling control signal end, and two electrode plates of the coupling capacitor are respectively used as the first end and the second end of the coupling module;

the control end of the compensation module is electrically connected with the first scanning signal input end, the first end of the compensation module is electrically connected with the second pole of the driving transistor, and the second end of the compensation module is electrically connected with the grid electrode of the driving transistor;

the light-emitting control module comprises a first light-emitting control unit and a second light-emitting control unit, the control ends of the first light-emitting control unit and the second light-emitting control unit are electrically connected with the light-emitting control signal input end, the first end of the first light-emitting control unit is electrically connected with the first power supply voltage input end, and the second end of the first light-emitting control unit is electrically connected with the first pole of the driving transistor;

the first end of the second light-emitting control unit is electrically connected with the second pole of the driving transistor, the second end of the second light-emitting control unit is electrically connected with the first end of the light-emitting module, and the second end of the light-emitting module is electrically connected with the second power supply voltage input end;

optionally, the pixel circuit further includes a second initialization module;

the second initialization module is used for writing initialization voltage into the first end of the light emitting module in any stage of the characteristic recovery stage, the initialization stage and the data writing stage.

In a second aspect, an embodiment of the present invention further provides a driving method of a pixel circuit, including:

in the characteristic recovery stage, the data writing module writes a data voltage into a first pole of the driving transistor; the coupling module couples the electric potential of the grid electrode of the driving transistor to a preset voltage, wherein the difference value of the preset voltage and the data voltage is opposite to the positive and negative of the voltage difference value of the grid electrode of the driving transistor and the first pole when the driving transistor is conducted;

in an initialization stage, a first initialization module writes an initialization voltage into a grid electrode of a driving transistor;

in a data writing phase, the data writing module writes a data voltage into a first pole of the driving transistor; the compensation module writes a compensation signal containing the threshold voltage information of the driving transistor into the grid electrode of the driving transistor;

in the light-emitting stage, the driving transistor generates a driving signal according to the voltage of the grid electrode of the driving transistor and the voltage of the first electrode of the driving transistor, and the light-emitting control module controls the driving signal to be output to the light-emitting module;

within one frame, the property recovery phase precedes the initialization phase.

In a third aspect, an embodiment of the present invention further provides a display panel, including the pixel circuit provided in the first aspect, further including a plurality of scan lines and a scan circuit, where the scan circuit includes a plurality of cascaded shift registers, an output terminal of an i-th stage shift register is connected to an i-th scan line and connected to an i-th row of pixel circuits, where i is greater than or equal to 1 and less than or equal to n, and n represents a total number of stages of the shift registers; the shift register is used for outputting a pulse signal in one frame.

Optionally, the pulse signal is an m pulse signal, and m is an integer greater than or equal to 2; the second ends of the coupling modules of the kth row of pixel circuits are electrically connected with a (k-2 a + 1) th scanning line, a is more than or equal to 2 and less than or equal to m, wherein a is an integer, the control ends of the data writing modules of the kth row of pixel circuits are electrically connected with the kth scanning line, the control ends of the initialization modules of the kth row of pixel circuits are electrically connected with the k-1 th scanning line, and k is more than or equal to 4 and less than or equal to n.

In the pixel circuit, the driving method thereof, and the display panel provided in this embodiment, in the characteristic writing stage, the gate of the driving transistor is coupled to the preset voltage through the coupling module, and the data voltage is written into the first pole of the driving transistor through the data writing module, where a difference between the preset voltage and the data voltage is opposite to a difference between the gate of the driving transistor and the first pole of the driving transistor when the driving transistor is turned on; in the characteristic recovery stage, the threshold voltage drift degree of the driving transistor is recovered to a certain extent, and the threshold voltage drift amount is pulled back, so that the threshold voltage drift of the driving transistor can be reduced, and the display uniformity is improved. And after the characteristic recovery stage in each frame, the drift degree of the threshold voltage of the driving transistor is minimum, so that the compensation module can fully compensate the threshold voltage of the driving transistor within the limited time of the data writing stage, and the display effect is improved. The characteristics of the driving transistor are recovered, the aging speed of the device of the driving transistor can be reduced, and the display effect is further ensured. In addition, the pixel circuit of the embodiment realizes the compensation of the threshold voltage of the driving transistor in a pixel circuit internal compensation mode, and compared with an external compensation mode, the pixel circuit can save cost.

Drawings

Fig. 1 is a schematic structural diagram of a pixel circuit according to an embodiment of the present invention;

FIG. 2 is a graph of threshold voltage versus time for a driving transistor according to an embodiment of the present invention;

fig. 3 is a schematic structural diagram of another pixel circuit according to an embodiment of the present invention;

fig. 4 is a driving timing diagram of a pixel circuit according to an embodiment of the invention;

fig. 5 is a schematic structural diagram of another pixel circuit according to an embodiment of the present invention;

fig. 6 is a driving timing diagram of another pixel circuit provided in the embodiment of the present invention;

fig. 7 is a driving timing diagram of another pixel circuit according to an embodiment of the invention;

fig. 8 is a flowchart of a driving method of a pixel circuit according to an embodiment of the present invention;

fig. 9 is a schematic structural diagram of a display panel according to an embodiment of the present invention;

fig. 10 is a partially enlarged view of fig. 9.

Detailed Description

The present invention will be described in further detail with reference to the accompanying drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting of the invention. It should be further noted that, for the convenience of description, only some of the structures related to the present invention are shown in the drawings, not all of the structures.

As described in the background art, the conventional pixel panel has the problems of uneven display and poor display effect. The inventor has found that the above problems occur because the conventional display panel generally includes an array substrate including a pixel circuit, and a transistor in the pixel circuit is generally manufactured based on an LTPS process, and the transistor manufactured based on the LTPS process has poor stability. For example, when the driving transistor in the pixel circuit is a P-type transistor, when the driving transistor is turned on to drive the light emitting device to emit light, a negative voltage stress is applied between the gate and the source of the driving transistor, and as the service life of the display panel is prolonged, the threshold voltage of the driving transistor is negatively floated due to the long-time negative voltage stress applied between the gate and the source of the driving transistor. Particularly, when the display panel performs high-brightness display, a large negative pressure stress is applied between the gate and the source of the driving transistor, which is more likely to cause the threshold voltage of the driving transistor to be negatively floated, so that the threshold voltage of the driving transistor is greatly shifted. Although the conventional internal compensation pixel circuit includes a structure for compensating the threshold voltage of the driving transistor, because the compensation time is limited, if the threshold voltage of the driving transistor drifts too much, the conventional internal compensation pixel circuit cannot complete sufficient compensation of the threshold voltage, and the driving current of the driving transistor is affected, thereby causing display non-uniformity. The external compensation technology requires the matching of an external compensation IC, and the cost is high. In addition, in the prior art, neither the internal compensation mode nor the external compensation mode for the threshold voltage recovers the characteristics of the driving transistor, for example, the P-type driving transistor always bears negative pressure stress in each frame of display time, so that the driving transistor still has the problem of high aging speed, and the display effect is influenced.

In view of the above problem, an embodiment of the present invention provides a pixel circuit, and fig. 1 is a schematic structural diagram of the pixel circuit provided in the embodiment of the present invention, and referring to fig. 1, the pixel circuit includes: a data writing module 110, a compensation module 120, a light emitting control module 130, a driving transistor DT, a coupling module 140, a light emitting module 150, and a first initialization module 160;

the data writing module 110 is configured to write a data voltage to the first pole s of the driving transistor DT in the characteristic recovery phase and the data writing phase; in one frame, the characteristic recovery stage is before the data stage;

the coupling module 140 is configured to couple, in a characteristic recovery phase, a potential of the gate g of the driving transistor DT to a preset voltage, where a difference between the preset voltage and the data voltage is opposite to a positive-negative difference between the gate g of the driving transistor DT and the first pole s when the driving transistor DT is turned on;

the first initialization module 160 is configured to write an initialization voltage to the gate g of the driving transistor DT during an initialization phase;

the compensation module 120 is used for writing a compensation signal containing threshold voltage information of the driving transistor DT into the gate g of the driving transistor DT in a data writing phase;

the driving transistor DT is configured to generate a driving signal according to a voltage of the gate g of the driving transistor DT and a voltage of the first pole s of the driving transistor DT during a light emitting period, and the light emitting control module 130 is configured to control the driving signal to be output to the light emitting module 150 during the light emitting period.

Optionally, the first pole s of the driving transistor DT is a source of the driving transistor DT.

Specifically, the operation process of the pixel circuit may include a characteristic recovery phase, an initialization phase, a data writing phase, and a light emitting phase. Wherein, in the characteristic recovery phase, the data writing module 110 writes the data voltage into the first pole s of the driving transistor DT, and the coupling module 140 couples the gate g of the driving transistor DT to the preset voltage, so that the difference between the gate voltage of the driving transistor DT and the first pole s of the driving transistor DT is V1-Vdata, where V1 represents the preset voltage and Vdata represents the data voltage. In the initialization phase, the first initialization module 160 writes an initialization voltage to the gate of the driving transistor DT. In the data writing phase, the data writing module 110 writes a data voltage into the first pole s of the driving transistor DT, and the compensation module 120 writes a compensation signal containing threshold voltage information of the driving transistor DT into the gate g of the driving transistor DT to compensate for the threshold voltage of the driving transistor DT. In the light emitting stage, the driving transistor DT is turned on, and a driving signal is generated according to the voltage of the gate g of the driving transistor DT and the voltage of the first pole s of the driving transistor DT to drive the light emitting module 150 to emit light; wherein, in the light emitting period, the voltage difference between the gate voltage of the driving transistor DT and the first voltage of the driving transistor DT is V2-Vdata, where V2 represents that the driving transistor DT is turned on as the voltage of the first pole s of the driving transistor DT, and Vdata represents the data voltage. Recording a voltage difference value V1-Vdata between the gate voltage of the driving transistor DT and the first pole s of the driving transistor DT in the characteristic recovery stage as a first difference value, recording a voltage difference value V2-Vdata between the gate voltage of the driving transistor DT and the first pole s of the driving transistor DT in the light emitting stage as a second difference value, and recording the difference value between the preset voltage and the data voltage as a positive and negative difference value between the gate g of the driving transistor DT and the first pole s when the driving transistor DT is turned on, namely the positive and negative difference values of the first difference value and the second difference value are opposite, for example, the first difference value is greater than 0, and the second difference value is less than 0; the first difference is less than 0, and the second difference is greater than 0.

Illustratively, when the driving transistor DT is a P-type transistor, the threshold voltage Vth of the driving transistor DT is less than 0, and the on condition of the driving transistor DT is Vgs < Vth, where Vgs is Vg-Vs, Vgs represents the voltage difference between the gate voltage of the driving transistor DT and the first pole s, Vg represents the gate voltage of the driving transistor DT, and Vs represents the first pole voltage of the driving transistor DT. When the driving transistor DT is a P-type transistor and Vgs of the driving transistor DT is required to be smaller than 0 when the driving transistor DT is turned on, the second voltage difference V2-Vdata is smaller than 0, so that a negative voltage stress is applied between the gate g and the first pole s of the driving transistor DT during the light emitting period, and a negative drift is easily generated in the threshold voltage of the driving transistor DT. And in the characteristic recovery stage, the difference value V1-Vdata between the grid voltage of the driving transistor DT and the first pole s of the driving transistor DT is opposite to the positive or negative of the second voltage difference value, and V1-Vdata is greater than 0, so that positive pressure stress is borne between the grid g of the driving transistor DT and the first pole s in the characteristic recovery stage, and the negative drift range of the threshold voltage of the driving transistor DT can be recovered to a certain extent. Fig. 2 is a graph of threshold voltage versus time of the driving transistor according to an embodiment of the present invention, and referring to fig. 2, wherein the abscissa represents time and the ordinate represents threshold voltage. The first curve 10 may represent a threshold voltage of the driving transistor DT with respect to time in the conventional pixel circuit, and the second curve 20 may represent a threshold voltage of the driving transistor DT with respect to time in the pixel circuit of this embodiment, wherein the first phase t10 may represent a data writing phase and a light emitting phase within one frame, and the second phase t20 may represent a characteristic recovery phase. As can be seen from fig. 2, since the conventional pixel circuit does not include a step of recovering the characteristics of the driving transistor DT during operation, the threshold voltage of the driving transistor DT is uniformly shifted toward one direction (for example, fig. 2 may show a process of negatively shifting the threshold voltage of the P-type driving transistor DT. the pixel circuit of this embodiment includes a characteristic recovery step in which the difference between the gate voltage of the driving transistor DT and the first electrode s is opposite to the difference between the gate voltage of the driving transistor DT and the first electrode voltage when the driving transistor DT is turned on, so that the threshold voltage shift of the driving transistor DT is recovered to some extent during the characteristic recovery step, and the threshold voltage shift is pulled back, thereby reducing the threshold voltage shift of the driving transistor DT and facilitating improvement of display uniformity, the initialization stage is performed before the data writing stage, so that the characteristic recovery stage is performed before the data writing stage, and after the characteristic recovery stage is completed, the shift degree of the threshold voltage of the driving transistor DT after the characteristic recovery stage in each frame can be minimized, thereby ensuring that the compensation module 120 can fully compensate the threshold voltage of the driving transistor DT within a limited time of the data writing stage, improving the display uniformity and improving the display effect. In addition, the characteristics of the driving transistor DT are recovered, the aging speed of the device of the driving transistor DT can be slowed down, and the display effect is further ensured.

It should be noted that, in this embodiment and the following embodiments, the preset voltage may not only refer to a fixed voltage value, and the preset voltage may only satisfy that the difference between the preset voltage and the data voltage is opposite to the difference between the voltage of the gate g of the driving transistor DT and the voltage of the first pole s when the driving transistor DT is turned on, that is, the preset voltage may be a range (for example, when the driving transistor DT is turned on, the gate voltage of the driving transistor DT and the voltage of the first pole s of the driving transistor DT are less than 0, it is only required to ensure that the preset voltage is greater than the data voltage), and in the characteristic recovery stage, the coupling module 140 couples the gate voltage of the driving transistor DT into the range.

It should be noted that, the above description is only given by taking the driving transistor DT as a P-type transistor as an example, when the driving transistor DT is an N-type transistor, a difference between the preset voltage and the data voltage is opposite to a difference between a voltage of the gate g of the driving transistor DT and the first pole s when the driving transistor DT is turned on, so that the threshold voltage of the driving transistor DT can be reduced.

In the pixel circuit provided by this embodiment, in the characteristic writing stage, the gate of the driving transistor is coupled to the preset voltage through the coupling module, and the data voltage is written into the first pole of the driving transistor through the data writing module, where a difference between the preset voltage and the data voltage is opposite to a positive or negative of a voltage difference between the gate of the driving transistor and the first pole when the driving transistor is turned on; in the characteristic recovery stage, the threshold voltage drift degree of the driving transistor is recovered to a certain extent, and the threshold voltage drift amount is pulled back, so that the threshold voltage drift of the driving transistor can be reduced, and the display uniformity is improved. And the characteristic recovery stage is before the data writing stage, so that the drift degree of the threshold voltage of the driving transistor is minimum after the characteristic recovery stage in each frame, and further, the compensation module can fully compensate the threshold voltage of the driving transistor within the limited time of the data writing stage, and the display effect is favorably improved. The characteristics of the driving transistor are recovered, the aging speed of the device of the driving transistor can be reduced, and the display effect is further ensured. In addition, the pixel circuit of the embodiment realizes the compensation of the threshold voltage of the driving transistor in a pixel circuit internal compensation mode, and compared with an external compensation mode, the pixel circuit can save cost.

The above is the core idea of the present invention, and the following will clearly and completely describe the technical solution in the embodiment of the present invention with reference to the drawings in the embodiment of the present invention. All other embodiments obtained by a person of ordinary skill in the art based on the embodiments of the present invention without any creative work belong to the protection scope of the present invention.

Fig. 3 is a schematic structural diagram of another pixel circuit according to an embodiment of the present invention, referring to fig. 1 and fig. 3, optionally, the first terminal of the coupling module 140 is electrically connected to the gate g of the driving transistor DT, the second terminal of the coupling module 140 is electrically connected to a coupling control signal terminal Ctrl, and the coupling control signal terminal Ctrl is used for inputting a preset timing signal to the second terminal of the coupling module 140 in the characteristic recovery phase t1, where the preset timing signal jumps from a first voltage signal to a second voltage signal in the characteristic recovery phase t1 so that the gate g of the driving transistor DT is coupled to a preset voltage.

Specifically, the coupling module 140 may have a voltage coupling function, specifically, when the coupling module 140 changes the voltage at one end, the other end generates the same voltage change process. The first end of the coupling module 140 is electrically connected to the gate g of the driving transistor DT, so that the voltage at the first end of the coupling module 140 is equal to the gate voltage of the driving transistor DT, and therefore, in the characteristic recovery phase t1, the preset timing signal is input to the second end of the coupling module 140 through the coupling control signal terminal Ctrl, and in the characteristic recovery phase t1, the preset timing signal jumps from the first voltage signal to the second voltage signal, that is, the voltage signal at the second end of the coupling module 140 jumps, so that the potential at the first end of the coupling module 140 can change accordingly, and by reasonably setting the voltage values of the first voltage signal and the second voltage signal, the gate voltage of the driving transistor DT can be coupled to the preset voltage. For example, for a P-type transistor, the first voltage signal may be a low level signal and the second voltage signal may be a high level signal; wherein the low level signal may be equal to a voltage value of a low level signal of the scan signal supplied to the pixel circuit, and the high level signal may be equal to a voltage value of a high potential signal of the scan signal supplied to the pixel circuit.

With continued reference to fig. 1 and fig. 3, optionally, the control terminal of the Data writing module 110 is electrically connected to the first scan signal input terminal S1, the first terminal of the Data writing module 110 is electrically connected to the Data voltage input terminal Data, and the second terminal of the Data writing module 110 is electrically connected to the first pole S of the driving transistor DT; the first scanning signal is an m pulse signal, and m is an integer greater than or equal to 2.

Specifically, since the data writing module 110 needs to be turned on in both the characteristic recovery phase and the data writing phase to write the data voltage into the first pole s of the driving transistor DT, the first scanning signal is set to be at least two pulse signals, and the two pulse signals of the at least two pulse signals are respectively used for controlling the data writing module 110 to be turned on in the characteristic recovery phase and controlling the data writing module 110 to be turned on in the data writing phase, so that it can be ensured that the data writing module 110 can be turned on in both the characteristic recovery phase and the data writing phase, and further, the data voltage can be written into the first pole s of the driving transistor DT in both the characteristic recovery phase and the data writing phase.

With continued reference to fig. 3, a first terminal of the coupling module 140 is electrically connected to the gate g of the driving transistor DT, and a second terminal of the coupling module 140 is electrically connected to the coupling control signal terminal Ctrl; the control terminal of the compensation module 120 is electrically connected to the first scan signal input terminal S1, the first terminal of the compensation module 120 is electrically connected to the second pole of the driving transistor DT, and the second terminal of the compensation module 120 is electrically connected to the gate g of the driving transistor DT; the light emission control module 130 includes a first light emission control unit 131 and a second light emission control unit 132, control terminals of the first light emission control unit 131 and the second light emission control unit 132 are electrically connected to the light emission control signal input terminal EM, a first terminal of the first light emission control unit 131 is electrically connected to the first power voltage input terminal Vdd, and a second terminal of the first light emission control unit 131 is electrically connected to the first pole s of the driving transistor DT; a first terminal of the second light emission control unit 132 is electrically connected to the second terminal of the driving transistor DT, a second terminal of the second light emission control unit 132 is electrically connected to a first terminal of the light emitting module 150, and a second terminal of the light emitting module 150 is electrically connected to the second power voltage input terminal Vss.

With continued reference to fig. 3, optionally, the data writing module 110 includes a first transistor T1, the compensation module 120 includes a second transistor T2, the first light emission control unit 131 includes a third transistor T3, the second light emission control unit 132 includes a fourth transistor T4, the coupling module 140 includes a coupling capacitor Cst, two plates of the coupling capacitor Cst serve as a first terminal and a second terminal of the coupling module 140, respectively, and the light emitting module 150 includes an organic light emitting device D1.

With continued reference to fig. 3, optionally, the control terminal of the first initialization module 160 is electrically connected to the second scan signal input terminal S2, the second scan signal input terminal S2 is used for inputting the second scan signal, the first terminal of the first initialization module 160 is electrically connected to the initialization voltage input terminal Vref, and the second terminal of the first initialization module 160 is electrically connected to the gate of the driving transistor DT;

the second scanning signal and the first scanning signal are output by the same scanning circuit, the scanning circuit comprises a plurality of cascaded shifting registers, wherein the j-th-stage shifting register is used for outputting the j-th-stage scanning signal, j is more than or equal to 1 and less than or equal to n, and j represents the total stage number of the shifting registers; the second scan signal is a first 1-level scan signal of the first scan signal. With continued reference to fig. 3, the first initialization module 160 may include a fifth transistor T5.

Specifically, the second scan signal and the first scan signal are output by the same scan circuit, and the number of pulse signals of the second scan signal is equal to the number of pulses of the first scan signal in one frame.

Fig. 4 is a driving timing diagram of a pixel circuit according to an embodiment of the present invention, which can be used to drive the pixel circuits shown in fig. 1 and 3. Optionally, the transistor included in the pixel circuit is a P-type transistor, or the transistor included in the pixel circuit is an N-type transistor, which is not specifically limited herein. The operation process of the pixel circuit shown in fig. 3 will be described by taking a P-type transistor as an example.

Referring to fig. 3 and 4, the operation process of the pixel circuit includes a characteristic recovery phase t1, an initialization phase t4, a data writing phase t2, and a light emission phase t 3.

With reference to fig. 3 and 4, the characteristic recovery phase t1 may comprise a first sub-phase t11 and a second sub-phase t12, the first sub-phase t11 being performed before the second sub-phase t 12; in the first sub-phase T11, the second scan signal input terminal S2 inputs a low level signal, the fifth transistor T5 is turned on, and the initialization voltage is transmitted to the gate of the driving transistor; at the time when the second scan signal input terminal S2 changes from low level to high level, the preset voltage signal input by the coupling control signal terminal Ctrl realizes the change from low level to high level, and the gate voltage of the driving transistor DT is coupled to the preset voltage; in the second sub-phase t12, the first scan signal input terminal S1 inputs a low level signal to complete the writing of the data voltage into the first pole S of the driving transistor DT. Since the difference between the preset voltage and the data voltage is opposite to the positive or negative of the voltage difference between the gate g and the first pole s of the driving transistor DT when the driving transistor DT is turned on, the set characteristic recovery phase t1 includes a first sub-phase t11 and a second sub-phase t12 performed after the first sub-phase t11, such that the gate voltage of the driving transistor DT has reached the preset voltage at the second sub-phase t12, such that the driving transistor DT is not turned on when the data voltage is written to the first pole s of the driving transistor DT, such that the data voltage written by the data voltage to the first pole s of the driving transistor DT does not affect the potential of the gate g of the driving transistor DT, and the gate g of the driving transistor DT is coupled to the accurate preset voltage after the characteristic recovery phase t 1. For the P-type transistor, when the driving transistor DT is turned on, the difference between the gate g and the first voltage is smaller than 0, so that the difference between the preset voltage and the data voltage is larger than 0, that is, in the characteristic recovery period t1, the voltage drop stress borne between the gate g and the first pole s of the driving transistor DT is opposite to the voltage drop stress borne when the driving transistor DT is turned on, so that in the characteristic recovery period t1, the threshold voltage drift amount of the driving transistor DT is pulled back, and the threshold voltage drift of the driving transistor DT can be reduced.

In the initialization period T4, the second scan signal input terminal S2 inputs a low level signal, the fifth transistor T5 is turned on, and the initialization voltage input from the initialization voltage terminal Vref is written to the gate g of the driving transistor DT through the turned-on fifth transistor T5. Specifically, as described above, after the characteristic recovery phase t1 is completed, the gate voltage of the driving transistor DT is the predetermined voltage, the potential of the first pole s of the driving transistor DT is the data voltage, and the difference between the predetermined voltage and the data voltage is opposite to the difference between the gate voltage of the driving transistor DT and the first pole voltage when the driving transistor DT is turned on, so that if the characteristic recovery phase t1 is directly transited to the data writing phase t2 within one frame, the driving transistor DT may not be turned on in the data writing phase t2, so that the data voltage cannot be written into the gate g of the driving transistor DT, and the compensation of the threshold voltage of the driving transistor DT cannot be completed. In the pixel circuit of the embodiment, the pixel circuit is configured to include the first initialization module 160, so that the gate voltage of the driving transistor DT is initialized after the characteristic recovery phase t1 and before the data writing phase t2, where the initialization voltage may be lower than the data voltage, so that the driving transistor DT may be turned on after entering the data writing phase t2, thereby ensuring that the data voltage can be successfully written and the threshold voltage of the driving transistor DT can be well compensated.

In the Data writing phase T2, the first scan signal input terminal S1 inputs a low level signal, the first transistor T1 and the second transistor T2 are turned on, and the Data voltage at the Data voltage input terminal Data is written to the gate g of the driving transistor DT through the first transistor T1, the driving transistor DT and the second transistor T2, and at this stage, the compensation of the threshold voltage of the driving transistor DT is completed.

In the light emitting period T3, the light emitting control signal input terminal EM inputs a low level signal, the third transistor T3 and the fourth transistor T4 are turned on, and the driving transistor DT generates a driving signal, which may be a driving current, according to its gate voltage and the voltage of the first electrode s, thereby driving the organic light emitting device to emit light.

Fig. 5 is a schematic structural diagram of another pixel circuit provided in the embodiment of the present invention, and referring to fig. 5, the pixel circuit further includes a second initialization module 170; the second initialization module 170 is configured to write an initialization voltage to the first terminal of the light emitting module 150 at any stage of the characteristic recovery stage, the initialization stage, and the data writing stage. Alternatively, the second initialization module 170 may include a sixth transistor T6, the control terminal of the second initialization module 170 is electrically connected to the first scan signal input terminal S1 or the second scan signal input terminal S2, the first terminal of the first initialization module 160 is electrically connected to the initialization voltage terminal Vref, and the second terminal of the first initialization module 160 is electrically connected to the first terminal of the light emitting module 150. Optionally, the first end of the light emitting module 150 is an anode of the light emitting module 150, and the second end of the light emitting module 150 is a cathode of the light emitting module 150.

When the control terminal (the gate of the sixth transistor T6) of the second initialization module 170 is electrically connected to the first scan signal input terminal S1, the sixth transistor T6 may be turned on during the characteristic recovery phase and the initialization phase; when the control terminal (the gate of the sixth transistor T6) of the second initialization module 170 is electrically connected to the second scan signal input terminal S2, the sixth transistor may be turned on during the characteristic recovery phase and the data writing phase. When the sixth transistor is turned on, the initialization voltage is written into the first end of the light emitting module 150 through the turned-on sixth transistor T6, so that the residual charge of a frame at the first end of the light emitting module 150 can be eliminated, which is beneficial to further improving the display effect.

With continued reference to fig. 5, optionally, the pixel circuit further includes a third scan signal input terminal S3, the third scan signal input terminal S3 is used as the coupling control signal terminal Ctrl, and the third scan signal input terminal S3 is used for receiving a third scan signal;

the third scanning signal is a single pulse signal, and the single pulse signal of the third scanning signal is overlapped with any one of the first (m-1) pulse signals of the second scanning signal.

Specifically, since the third scan signal input terminal S3 serves as the coupling control signal terminal Ctrl, the third scan signal can be used to control the voltage magnitude of the gate g of the driving transistor DT. The driving sequence shown in fig. 4 is also applicable to the pixel circuit shown in fig. 5, and the driving sequence shown in fig. 4 corresponds to the case where the third scan signal is a single pulse signal, and the first scan signal is a double pulse signal, for example, the single pulse signal of the third scan signal overlaps with the first (2-1) pulse signal of the second scan signal (i.e. overlaps with the first pulse signal of the double pulse signal), so that the rising edge of the single pulse signal of the third scan signal coincides with the rising edge of the first pulse signal of the double pulse signal of the second scan signal, and the gate voltage of the driving transistor DT is coupled to the preset voltage at the rising edge, so that when the data voltage is written into the first pole s of the driving transistor DT, the driving transistor DT is not turned on, and the data voltage written into the first pole s of the driving transistor DT by the data voltage does not affect the potential of the gate g of the driving transistor DT, further, after the characteristic recovery period t1, the gate g of the driving transistor DT is coupled to an accurate preset voltage.

The principle is similar to that when m is 2 for the case where m >2, and the description is omitted here.

With continued reference to fig. 5, optionally, the pixel circuit further includes a third scan signal input terminal S3, the third scan signal input terminal S3 is used as a coupling control signal Ctrl, and the third scan signal input terminal Ctrl is used for inputting a third scan signal;

the third scanning signal, the first scanning signal and the second scanning signal are output by the same scanning circuit;

the third scanning signal is a front (2a-1) level scanning signal of the first scanning signal, wherein a is more than or equal to 2 and less than or equal to m, and a is an integer; in one frame, the interval time between the falling edges of two adjacent pulse signals of the first scanning signal is equal to the scanning time of two rows of pixel circuits.

Specifically, the third scan signal, the first scan signal and the second scan signal are output by the same scan circuit, so that the number of pulses of the third scan signal in one frame is equal to the number of pulses of the first scan signal and the number of pulses of the second scan signal. In one frame, the interval time between the falling edges of two adjacent pulse signals of the first scanning signal is equal to the scanning time of two rows of pixel circuits, so the time interval between the falling edges of two adjacent pulse signals of the second scanning signal in one frame and the distance between the falling edges of two adjacent pulse signals of the second scanning signal are both equal to the scanning time of two rows of pixel circuits. For any scanning signal in the first scanning signal, the second scanning signal and the third scanning signal, the falling edges of two adjacent pulse signals or the time interval between the rising edges of two adjacent pulse signals can be the scanning time of two rows of pixel circuits, so that when the pulse signals of the second scanning signal and the third scanning signal are overlapped in one frame, the overlapped pulse signals can be completely overlapped, and further the pulse signals in the second scanning signal and the third scanning signal can simultaneously reach the rising edges in the characteristic recovery stage, and further the potential of the grid electrode of the driving transistor can be coupled to the preset voltage.

Exemplarily, when m is 2 (that is, the first scan signal, the second scan signal, and the third scan signal are all double pulse signals), a is 2, and the third scan signal is the first 3-stage scan signal of the first scan signal; when m is 3 (i.e., the first scan signal, the second scan signal and the third scan signal are all three-pulse signals), a is 2 or 3, then the third scan signal is the first 3 or 5 stage scan signal of the first scan signal; when m is 4, a is 2, 3 or 4, the third scan signal is the first 3, 5 or 7 stage scan signal of the first scan signal, and so on for the case that m >4, which is not described herein again.

Fig. 6 is a timing diagram of another driving sequence of the pixel circuit according to the embodiment of the present invention, where the timing sequence is used to drive the pixel circuit shown in fig. 5, and the timing sequence shown in fig. 6 is illustrated by taking a first scan signal, a second scan signal, and a third scan signal as an example of a double pulse signal. Taking the first Scan signal as ScanN for example, the second Scan signal is Scan (N-1) and the third Scan signal is Scan (N-3). Wherein ScanN represents the scanning signal output by the N-th stage shift register, Scan (N-3) represents the scanning signal output by the (N-3) -th stage shift register, and Scan (N-1) represents the scanning signal output by the (N-1) -th stage shift register, wherein N ≧ 4. When the first scanning signal, the second scanning signal and the third scanning signal are double-pulse signals, the second pulse of the third scanning signal is overlapped with the first pulse of the second scanning signal.

The operation process exemplarily illustrated by taking the example that the transistors included in the pixel circuit illustrated in fig. 5 are all P-type transistors is described as an example.

Referring to fig. 5 and 6, the operation process of the pixel circuit includes a preparation phase t0, a characteristic recovery phase t1, an initialization phase t4, a data writing phase t2, and a light emitting phase t 3.

In preparation for the period t0, the third scan signal input terminal S3 first inputs a signal including a falling edge and a rising edge of a pulse signal, so that the gate voltage of the driving transistor DT is first coupled to be lowered and then coupled to be raised, and thus the gate voltage of the driving transistor DT is changed negligibly in this period.

The characteristic recovery phase t1 may include a first sub-phase t11 and a second sub-phase t 12. Wherein at the initial time of the first sub-phase T11, the third scan signal input terminal S3 and the second scan signal input terminal S2 input low level signals, the fifth transistor T5 and the sixth transistor T6 are turned on in response to the low level input from the second scan signal input terminal S2, the initialization voltage is transmitted to the gate g of the driving transistor DT through the turned-on fifth transistor T5, and the initialization voltage is transmitted to the first terminal of the light emitting module 150 through the turned-on sixth transistor T6. Since the second pulse signal of the third scan signal coincides with the first pulse signal of the second scan signal within a frame, the gate g of the driving transistor DT floats at the moment when the second pulse signal of the third scan signal and the first pulse signal of the second scan signal end, i.e., the low level of the signals input from the third scan signal input terminal S3 and the second scan signal input terminal S2 changes to the high level, and the potential of the gate g of the driving transistor DT is coupled to the preset voltage from the initialization voltage. In the second sub-phase T12, a low level signal is input from the first scan signal input terminal S1, the first transistor T1 is turned on, the data voltage is written into the first pole S of the driving transistor DT, and the difference between the preset voltage and the data voltage is opposite to the positive or negative of the voltage difference between the gate g of the driving transistor DT and the first pole S when the driving transistor DT is turned on, so as to recover the characteristic of the driving transistor DT.

In the initialization period T4, the second scan signal input terminal S2 inputs a low level signal, the fifth transistor T5 is turned on, and the initialization voltage input from the initialization voltage terminal Vref is written to the gate g of the driving transistor DT through the turned-on fifth transistor T5. Taking the gate of the sixth transistor T6 connected to the second scan signal input terminal S2 as an example, in the initialization period T4, the sixth transistor T6 is turned on, and the initialization voltage is written to the first terminal of the light emitting module 150 through the turned-on sixth transistor T6, so that the residual charge of the first terminal of the light emitting module 150 for one frame can be eliminated.

Fig. 7 is a timing diagram of driving another pixel circuit according to an embodiment of the present invention, where the timing diagram is used to drive the pixel circuit shown in fig. 5, and the timing diagram shown in fig. 7 is taken to illustrate that the first scan signal, the second scan signal, and the third scan signal are all three pulse signals. Taking the first Scan signal as ScanN for example, the second Scan signal is Scan (N-1), the third Scan signal is Scan (N-3) or Scan (N-5), where ScanN represents the Scan signal output by the Nth stage shift register, Scan (N-3) represents the Scan signal output by the (N-3) th stage shift register, Scan (N-5) represents the Scan signal output by the (N-5) th stage shift register, and Scan (N-1) represents the Scan signal output by the (N-1) th stage shift register.

Referring to fig. 7, in the driving timing sequence shown in fig. 7, the working process of the corresponding pixel circuit still includes a characteristic recovery phase, an initialization phase t4, a data writing phase t2, and a light emitting phase t3, where the working processes of the initialization phase t4, the data writing phase t2, and the light emitting phase t3 are respectively the same as the working processes of the initialization phase, the data writing phase, and the light emitting phase in any of the above embodiments, and the description of this embodiment is omitted here. When the first scanning signal and the second scanning signal are multi-pulse signals, the last pulse signal in the second scanning signal is used as a control signal for controlling the pixel circuit to perform the working process in the initialization stage, and the last pulse signal in the first scanning signal is used as a control signal for controlling the pixel circuit to perform the working process in the data writing stage.

Referring to fig. 7, when m is equal to 3, Scan (N-3) or Scan (N-5) may be used as the third Scan signal, when Scan (N-3) is used as the third Scan signal and is connected to the third Scan signal input terminal S3, the third pulse signal in the third Scan signal coincides with the second pulse signal in the second Scan signal, at this time, the characteristic recovery stage may correspond to stage t10 in the figure, and the characteristic recovery stage may still include the first sub-stage t101 and the second sub-stage t102, and the working processes of the first sub-stage t101 and the second sub-stage t102 are respectively the same as the working processes of the first sub-stage and the second sub-stage in any of the embodiments of the present invention, and this implementation is not repeated herein. When Scan (N-3) is connected to the third Scan signal input terminal S3 as a third Scan signal, a second pulse signal in the third Scan signal coincides with a first pulse signal of a second Scan signal, and at this time, the characteristic recovery stage may also correspond to stage t11 in the figure, and the characteristic recovery stage may still include a first sub-stage t111 and a second sub-stage t112, where the working process of the first sub-stage t111 is the same as that of the first sub-stage in any of the embodiments of the present invention, and this implementation is not repeated herein; the working process of the second sub-phase t112 may include two phases, namely a first phase t1121 and a second phase t1122, where the working process of the first phase t1121 is a working process of writing a data voltage to the first electrode of the driving transistor, and may be the same as the second sub-phase in any of the embodiments of the present invention described above, and the second phase t1122 may be the same as the second sub-phase in the phase t10, and will not be described herein again.

Referring to fig. 7, when m is 3, when Scan (N-5) is accessed as a third Scan signal to the third Scan signal input terminal S3, a third pulse signal in the third Scan signal coincides with a first pulse signal of the second Scan signal, at this time, the characteristic recovery stage may correspond to stage t11 in the figure, and the characteristic recovery stage may still include a first sub-stage t111 and a second sub-stage t112, a working process of the first sub-stage t111 is the same as that of the first sub-stage in any of the embodiments of the present invention, and details of the implementation are not repeated herein; the operation process of the second sub-phase t112 may include two phases, i.e., a first phase t1121 and a second phase t1122, where the operation process of the first phase t1121 is the operation process of writing the data voltage into the first pole of the driving transistor, and may be the same as the operation process of the second sub-phase in any of the embodiments of the present invention described above;

unlike Scan (N-3) as the third Scan signal, the third Scan signal is all high level signal in the second stage t1122, and no pulse signal coincident with the second Scan signal is included, so that the process of recovering the characteristics of the driving transistor is not included in the second stage t1122, but only the process of initializing the gate of the driving transistor (the second pulse signal of the second Scan signal) and writing data to the first pole of the driving transistor (the second pulse signal of the first Scan signal) are included in the second stage t 1122.

In the pixel circuit provided in this embodiment, the signals coupled to the control signal terminal Ctrl, the control terminal of the first initialization module 160, and the control terminal of the data write-in module 110 are provided by the same scanning circuit, and the scanning circuit is usually disposed in the frame region of the display panel, so that the signals coupled to the control signal terminal Ctrl, the control terminal of the first initialization module 160, and the control terminal of the data write-in module 110 are provided by the same scanning circuit, so that the frame region occupied by the scanning circuit is small, and the narrow frame of the display panel including the pixel circuit is advantageously implemented.

In any of the above embodiments of the present invention, the coupling module 140 may be a coupling capacitor.

An embodiment of the present invention further provides a driving method for a pixel circuit, where the driving method can be used to drive the pixel circuit provided in any of the above embodiments of the present invention, and fig. 8 is a flowchart of the driving method for a pixel circuit provided in the embodiment of the present invention, and with reference to fig. 8, the driving method includes:

step 210, in the characteristic recovery stage, the data writing module writes the data voltage into the first pole of the driving transistor; the coupling module couples the electric potential of the grid electrode of the driving transistor to a preset voltage, wherein the difference value of the preset voltage and the data voltage is opposite to the positive and negative of the voltage difference value of the grid electrode of the driving transistor and the first pole when the driving transistor is conducted;

step 220, in the initialization stage, the first initialization module writes an initialization voltage into the gate of the driving transistor;

step 230, in the data writing stage, the data writing module writes the data voltage into the first pole of the driving transistor; the compensation module writes a compensation signal containing the threshold voltage information of the driving transistor into the grid electrode of the driving transistor;

step 240, in the light emitting stage, the driving transistor generates a driving signal according to the voltage of the gate of the driving transistor and the voltage of the first pole of the driving transistor, and the light emitting control module controls the driving signal to be output to the light emitting module;

within one frame, the property recovery phase precedes the data phase.

According to the driving method of the pixel circuit provided by the embodiment of the invention, in the characteristic recovery stage, the data writing module writes the data voltage into the first pole of the driving transistor; the coupling module couples the grid electrode of the driving transistor to a preset voltage, wherein the difference value between the preset voltage and the data voltage is opposite to the positive and negative of the voltage difference value between the grid electrode of the driving transistor and the first pole when the driving transistor is conducted; in the characteristic recovery stage, the threshold voltage drift degree of the driving transistor is recovered to a certain extent, and the threshold voltage drift amount is pulled back, so that the threshold voltage drift of the driving transistor can be reduced, and the display uniformity is improved. And the characteristic recovery stage is before the data writing stage, so that the drift degree of the threshold voltage of the driving transistor is minimum after the characteristic recovery stage in each frame, and further, the compensation module can fully compensate the threshold voltage of the driving transistor within the limited time of the data writing stage, the display uniformity is improved, and the display effect is improved. The characteristics of the driving transistor are recovered, the aging speed of the device of the driving transistor can be reduced, and the display effect is further ensured. In addition, in the driving method of the pixel circuit of the embodiment, the compensation of the threshold voltage of the driving transistor is realized in an internal compensation mode of the pixel circuit, and compared with an external compensation mode, the cost can be saved.

Fig. 9 is a schematic structural diagram of a display panel according to an embodiment of the present invention, and referring to fig. 9, the display panel 300 includes a pixel circuit 310 according to any embodiment of the present invention.

With continued reference to fig. 9, optionally, the display panel 300 further includes a plurality of scan lines 320 and a scan circuit 330, the scan circuit 330 includes a plurality of cascaded shift registers 331, wherein an output terminal of the ith-stage shift register 331 is connected to the ith scan line and connected to the ith row of pixel circuits, where 1 ≦ i ≦ n, and n represents the total number of stages of the shift register 331; the shift register 331 is used to output a pulse signal within one frame.

Optionally, the pulse signal is an m pulse signal, and m is an integer greater than or equal to 2; the second end of the coupling module of the kth row of pixel circuits 310 is electrically connected to the (k-2 a + 1) th scanning line, a is greater than or equal to 2 and is less than or equal to m, wherein a is an integer, the control end of the data writing module of the kth row of pixel circuits 310 is electrically connected to the kth scanning line, the control end of the initialization module of the kth row of pixel circuits 310 is electrically connected to the (k-1) th scanning line, and k is greater than or equal to 4 and is less than or equal to n.

Referring to fig. 9, the display panel 300 may further include data lines 340, wherein the first to nth stages of shift registers are arranged along a first direction y in which the data lines 340 extend; each scan line extends along a direction in which 320 intersects with the data line 340, and the 1 st scan line to the nth scan line are arranged along a first direction in which the data line 340 extends. The display panel 300 includes a display area AA and a non-display area NAA, and optionally, the pixel circuit 310 is disposed in the display area AA, and the scan circuit 330 is disposed in the non-display area NAA.

Fig. 10 is a partial enlarged view of fig. 9, where fig. 10 may correspond to an enlarged view corresponding to a dashed line enclosed area 350 in fig. 9, and fig. 10 exemplarily shows the first 4 rows of pixel circuits 310 of the first column of pixel circuits 310, taking the scanning signal output by the shift register as a double pulse signal, that is, m is 2, where a is 2, and k-2a +1 is k-3; referring to fig. 10, the second terminal of the coupling module (connected to the second scan signal input terminal S2) of the pixel circuit 310 in the fourth row is electrically connected to the 1(4-3) th scan line 320, the control terminal of the data write module (connected to the first scan signal input terminal S1) of the pixel circuit 310 in the 4 th row is electrically connected to the 4 th scan line, and the control terminal of the initialization module (connected to the third scan signal input terminal S3) of the pixel circuit in the 4 th row is electrically connected to the 3(4-1) th scan line.

It should be noted that fig. 10 only uses the connection manner of the pixel circuits 310 in the row 4 and the scan line 320 as an example for schematic output, and the pixel circuits 310 in the rows 4 to n can all adopt the connection manner, so that signals coupling the control signal terminal, the control terminal of the first initialization module, and the control terminal of the data writing module can be provided by the same scan circuit 330, and a group of scan circuits 330 is provided in the display panel 300, and the scan circuit 330 is usually disposed in a frame area (non-display area NAA) of the display panel 300, so that the frame area occupied by the scan circuit 330 is smaller, and further, it is beneficial to implement a narrow frame of the display panel 300 including the pixel circuit 310.

It is to be noted that the foregoing is only illustrative of the preferred embodiments of the present invention and the technical principles employed. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, although the present invention has been described in greater detail by the above embodiments, the present invention is not limited to the above embodiments, and may include other equivalent embodiments without departing from the spirit of the present invention, and the scope of the present invention is determined by the scope of the appended claims.

Claims

1. A pixel circuit, comprising: the device comprises a data writing module, a compensation module, a light emitting control module, a driving transistor, a coupling module, a light emitting module and a first initialization module;

the data writing module is used for writing a data voltage into a first pole of the driving transistor in a characteristic recovery phase and a data writing phase;

the first initialization module is used for writing initialization voltage into the grid electrode of the driving transistor in an initialization stage; within one frame, the characteristic recovery phase precedes the initialization phase;

2. The pixel circuit according to claim 1, wherein a first terminal of the coupling module is electrically connected to the gate of the driving transistor, and a second terminal of the coupling module is electrically connected to a coupling control signal terminal, the coupling control signal terminal being configured to input a predetermined timing signal to the second terminal of the coupling module during the characteristic recovery phase, wherein the predetermined timing signal jumps from a first voltage signal to a second voltage signal during the characteristic recovery phase to couple the gate of the driving transistor to a predetermined voltage.

3. The pixel circuit according to claim 2, wherein the control terminal of the data writing module is electrically connected to a first scan signal input terminal, the first scan signal input terminal is configured to receive a first scan signal, the first terminal of the data writing module is electrically connected to a data voltage input terminal, and the second terminal of the data writing module is electrically connected to the first pole of the driving transistor;

4. The pixel circuit according to claim 3, wherein the control terminal of the first initialization module is electrically connected to a second scan signal input terminal, the second scan signal input terminal is used for inputting a second scan signal, the first terminal of the first initialization module is electrically connected to an initialization voltage input terminal, and the second terminal of the first initialization module is electrically connected to the gate of the driving transistor;

the second scanning signal and the first scanning signal are output by the same scanning circuit, the scanning circuit comprises a plurality of cascaded shift registers, wherein the j-th-stage shift register is used for outputting the j-th-stage scanning signal, j is more than or equal to 1 and less than or equal to n, and j represents the total stage number of the shift registers;

the second scan signal is a first 1-level scan signal of the first scan signal.

5. The pixel circuit according to claim 4, further comprising a third scan signal input terminal, the third scan signal input terminal being the coupling control signal terminal, the third scan signal input terminal being configured to receive a third scan signal;

the third scanning signal is a single pulse signal, and the single pulse signal of the third scanning signal overlaps with any one of the first (m-1) pulse signals of the second scanning signal.

6. The pixel circuit according to claim 4, further comprising a third scan signal input terminal as the coupling control signal, the third scan signal input terminal being for inputting a third scan signal;

the third scanning signal is a front (2a-1) level scanning signal of the first scanning signal, wherein a is more than or equal to 2 and less than or equal to m, and a is an integer; in one frame, the interval time between the falling edges of two adjacent pulse signals of the first scanning signal is equal to the scanning time of two rows of the pixel circuits.

7. The pixel circuit according to claim 1 or 2, wherein the coupling module comprises a capacitor;

the control end of the data writing module is electrically connected with the first scanning signal input end, the first end of the data writing module is electrically connected with the data voltage input end, and the second end of the data writing module is electrically connected with the first pole of the driving transistor;

the first end of the coupling module is electrically connected with the grid electrode of the driving transistor, the second end of the coupling module is electrically connected with the coupling control signal end, and two polar plates of the coupling capacitor are respectively used as the first end and the second end of the coupling module;

the light-emitting control module comprises a first light-emitting control unit and a second light-emitting control unit, control ends of the first light-emitting control unit and the second light-emitting control unit are electrically connected with a light-emitting control signal input end, a first end of the first light-emitting control unit is electrically connected with a first power supply voltage input end, and a second end of the first light-emitting control unit is electrically connected with a first pole of the driving transistor;

a first end of the second light-emitting control unit is electrically connected with a second electrode of the driving transistor, a second end of the second light-emitting control unit is electrically connected with a first end of the light-emitting module, and a second end of the light-emitting module is electrically connected with a second power supply voltage input end;

preferably, the pixel circuit further comprises a second initialization module;

the second initialization module is configured to write an initialization voltage to the first terminal of the light emitting module at any one of the characteristic recovery phase, the initialization phase, and the data writing phase.

8. A method of driving a pixel circuit, comprising:

in the characteristic recovery stage, the data writing module writes a data voltage into a first pole of the driving transistor; the coupling module couples the electric potential of the grid electrode of the driving transistor to a preset voltage, wherein the difference value between the preset voltage and the data voltage is opposite to the positive and negative of the voltage difference value between the grid electrode of the driving transistor and the first pole when the driving transistor is conducted;

in an initialization stage, a first initialization module writes an initialization voltage into a grid electrode of the driving transistor;

in a light emitting stage, the driving transistor generates a driving signal according to the voltage of the grid electrode of the driving transistor and the voltage of the first electrode of the driving transistor, and the light emitting control module controls the driving signal to be output to the light emitting module;

within one frame, the characteristic recovery phase precedes the initialization phase.

9. A display panel comprising the pixel circuit according to any one of claims 1 to 7, further comprising a plurality of scan lines and a scan circuit, wherein the scan circuit comprises a plurality of cascaded shift registers, wherein an output terminal of an i-th stage shift register is connected to an i-th scan line connected to an i-th row of the pixel circuits, wherein 1 ≦ i ≦ n, and n represents a total number of stages of the shift register; the shift register is used for outputting a pulse signal in one frame.

10. The display panel according to claim 9, wherein the pulse signal is an m-pulse signal, m being an integer greater than or equal to 2; the second ends of the coupling modules of the kth row of pixel circuits are electrically connected with a (k-2 a + 1) th scanning line, a is more than or equal to 2 and less than or equal to m, wherein a is an integer, the control ends of the data writing modules of the kth row of pixel circuits are electrically connected with the kth scanning line, the control ends of the initialization modules of the kth row of pixel circuits are electrically connected with the k-1 th scanning line, and k is more than or equal to 4 and less than or equal to n.