CN111709203A - FPGA (field programmable Gate array) optimization method and system for star topology structure of maintenance system - Google Patents
FPGA (field programmable Gate array) optimization method and system for star topology structure of maintenance system Download PDFInfo
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- CN111709203A CN111709203A CN202010386603.5A CN202010386603A CN111709203A CN 111709203 A CN111709203 A CN 111709203A CN 202010386603 A CN202010386603 A CN 202010386603A CN 111709203 A CN111709203 A CN 111709203A
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Abstract
The invention discloses a FPGA (field programmable gate array) optimization method and system for a star topology structure of a maintenance system, wherein the method comprises the following steps: s100, adding a maintenance relay module in each FPGA fragment in the plurality of FPGA fragments to be interconnected with a core function module so as to change the original single-beat logic into multi-beat logic; s200, based on the maintenance relay modules in the FPGA fragments, converting the connection structures between the FPGA fragments and the maintenance system function module from a star topology structure to a serial structure. The star topology structure is converted into a serial structure, so that the problem of interconnection of multiple FPGA maintaining systems under the multi-core scale is solved; and a maintenance relay module is added, the original single-beat logic is changed into multi-beat logic, and the threading logic is beaten for two beats by using a trigger, so that the problem of time sequence convergence of the threading logic is solved.
Description
Technical Field
The invention relates to the field of FPGA optimization, in particular to an FPGA optimization method and system for maintaining a star topology structure of a system.
Background
In chip design, in order to facilitate maintenance and debugging, system function modules are designed and maintained.
With SoC multi-core technology
The development is rapid, the number of cores integrated on one chip is more and more, the scale is larger and more, a maintenance system in a multi-core chip usually adopts a star topology structure, and a maintenance system function module and all core modules in the chip are connected with each other and are used for scanning, error reporting and other maintenance, diagnosis and test logics.
During FPGA simulation verification, after FPGA is sliced, due to the limitation of the number of pins between the slices, the number of connecting lines between the FPGA slices is increased sharply along with the increase of the number of cores, and the one-to-many maintenance star topology structure cannot be realized under the multi-core scale. Therefore, there is a need for an FPGA optimization technique for one-to-many star topologies without affecting logic correctness.
Disclosure of Invention
Aiming at the defects in the prior art, the invention aims to provide an FPGA (field programmable gate array) optimization method and system for a star topology structure of a maintenance system, wherein the star topology structure is converted into a serial structure, the original one-to-many maintenance interconnection structure is optimized into a head-to-tail serial structure, and the problem of interconnection of multiple FPGAs of the maintenance system under the multi-core scale is solved.
In order to achieve the purpose, the technical scheme adopted by the invention is as follows:
an FPGA optimization method for a star topology structure of a maintenance system comprises the following steps:
(1) a maintenance relay module is added in each FPGA fragment of the plurality of FPGA fragments and is interconnected with the core function module to change the original single-beat logic into multi-beat logic;
(2) and based on the maintenance relay modules in the FPGA fragments, converting the connection structures between the FPGA fragments and the maintenance system function module from a star topology structure to a serial structure.
Further, according to the above FPGA optimization method for the maintenance system star topology, the star topology is: and the core function module in each FPGA sub-chip is connected with the maintenance system function module.
Further, according to the above FPGA optimization method for maintaining the star topology of the system, the serial structure is: and the maintenance relay modules in the FPGA sub-slices are sequentially connected in series end to end, and the maintenance relay module in the first FPGA sub-slice is connected with the maintenance system function module.
Further, as described above, the method for optimizing an FPGA facing a star topology of a maintenance system includes: a plurality of register sets.
Further, the method for optimizing the FPGA facing the maintenance system star topology structure is characterized in that the maintenance relay module includes: the first register group is used for receiving an output signal of the core function module of the current stage through the maintenance interface; the second register group is used for receiving the output signal of the next-stage maintenance relay module; the third register group is used for receiving the output signals of the first register group and the second register group and sending the received signals to the upper-level maintenance relay module; the fourth register group is used for receiving the output signal of the upper-level core function module; the fifth register group is used for receiving the output signal of the fourth register group and sending the received signal to the next-stage maintenance relay module; and the sixth register group is used for receiving the output signal of the fourth register group and sending the received signal to the core function module of the current stage through the maintenance interface.
An FPGA optimization system for a star topology of a maintenance system comprises:
the system comprises an optimization module, a core function module and a plurality of FPGA fragments, wherein the optimization module is used for adding a maintenance relay module in each FPGA fragment in the plurality of FPGA fragments to be interconnected with the core function module so as to change the original single-beat logic into multi-beat logic;
and the conversion optimization module is used for converting the connection structure between the FPGA fragments and the maintenance system function module from a star topology structure into a serial structure based on the maintenance relay modules in the FPGA fragments.
Further, as described above, the FPGA optimization system for maintaining the star topology structure of the system, the star topology structure is: and the core function module in each FPGA sub-chip is connected with the maintenance system function module.
Further, as described above, the serial structure of the FPGA optimization system for the maintenance system star topology is: and the maintenance relay modules in the FPGA sub-slices are sequentially connected in series end to end, and the maintenance relay module in the first FPGA sub-slice is connected with the maintenance system function module.
Further, as described above, the maintenance relay module includes: a plurality of register sets.
Further, as described above, the maintenance relay module includes: the first register group is used for receiving an output signal of the core function module of the current stage through the maintenance interface; the second register group is used for receiving the output signal of the next-stage maintenance relay module; the third register group is used for receiving the output signals of the first register group and the second register group and sending the received signals to the upper-level maintenance relay module; the fourth register group is used for receiving the output signal of the upper-level core function module; the fifth register group is used for receiving the output signal of the fourth register group and sending the received signal to the next-stage maintenance relay module; and the sixth register group is used for receiving the output signal of the fourth register group and sending the received signal to the core function module of the current stage through the maintenance interface.
The invention has the beneficial effects that: the star topology structure is converted into a serial structure, so that the problem of interconnection of multiple FPGA maintaining systems under the multi-core scale is solved; and a maintenance relay module is added, the original single-beat logic is changed into multi-beat logic, and the threading logic is beaten for two beats by using a trigger, so that the problem of time sequence convergence of the threading logic is solved.
Drawings
Fig. 1 is a schematic flowchart of an FPGA optimization method for maintaining a star topology of a system according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of topology conversion provided in an embodiment of the present invention;
fig. 3 is a schematic structural diagram of a maintenance relay module provided in the embodiment of the present invention.
Detailed Description
The invention is described in further detail below with reference to the drawings and the detailed description.
As shown in fig. 1, a method for optimizing an FPGA facing a star topology of a maintenance system includes:
s100, adding a maintenance relay module in each FPGA fragment in the plurality of FPGA fragments to be interconnected with a core function module so as to change the original single-beat logic into multi-beat logic;
s200, based on the maintenance relay modules in the FPGA fragments, converting the connection structures between the FPGA fragments and the maintenance system function module from a star topology structure to a serial structure.
The star topology is: and the core function module in each FPGA sub-chip is connected with the maintenance system function module.
The serial structure is as follows: the maintenance relay modules in the FPGA sub-slices are sequentially connected in series end to end, and the maintenance relay module in the first FPGA sub-slice is connected with the maintenance system function module.
Preferably, the maintenance relay module includes: the first register group is used for receiving an output signal of the core function module of the current stage through the maintenance interface; the second register group is used for receiving the output signal of the next-stage maintenance relay module; the third register group is used for receiving output signals of the first register group and the second register group and sending the received signals to the upper-level maintenance relay module; the fourth register group is used for receiving the output signal of the upper-level core function module; the fifth register group is used for receiving the output signal of the fourth register group and sending the received signal to the next-stage maintenance relay module; and the sixth register group is used for receiving the output signal of the fourth register group and sending the received signal to the core function module of the current stage through the maintenance interface.
As shown in fig. 2, the star topology is converted into a serial structure, and the original one-to-many maintenance interconnection structure is optimized into a first serial structure. Before conversion, each core function module is generally realized by using one FPGA fragment due to large scale, and since n core function modules and a maintenance system function module all have interfaces, after FPGA fragmentation (a dashed box in fig. 2 represents FPGA fragmentation), the FPGA where the maintenance logic is located needs n sets of maintenance interfaces. After the serial structure is converted, only one set of maintenance interface is needed for maintaining the FPGA where the logic is located, so that the problem of interconnection of multiple FPGAs of the maintenance system under the multi-core scale is solved.
As shown in fig. 3, the original single-beat logic is changed into multi-beat logic, and as the relay signal needs to be transmitted through the chip, the sockets used for the chip input and the chip output are not in the same super logic area, and no trigger is arranged in the middle, the time line crossing the super logic area is prolonged, and the timing constraint is difficult to meet. And the trigger is used for beating the maintenance relay signal needing threading transmission for two beats, so that IO register resources can be used for both the in-chip and the out-chip, and the problem of threading logic time sequence convergence is solved.
The invention converts the star topology structure into the serial structure, optimizes the original one-to-many maintenance interconnection structure into a head-to-tail serial structure, and solves the interconnection problem of multiple FPGAs of the maintenance system under the multi-core scale. The maintenance relay module is added to realize maintenance serial relay, the original single-beat logic is changed into multi-beat logic, and because the sockets used by the chip-through signal chip-in and chip-out are not in the same super logic area and no trigger is arranged in the middle, the time line crossing the super logic area is prolonged, and the time sequence constraint is difficult to meet. And the flip-flop is used for beating the threading logic for two beats, so that IO register resources can be used for both the in-chip and the out-chip, and the problem of threading logic time sequence convergence is solved.
The invention also provides an FPGA optimization system for the maintenance system star topology structure, which comprises:
the system comprises an optimization module, a core function module and a plurality of FPGA fragments, wherein the optimization module is used for adding a maintenance relay module in each FPGA fragment in the plurality of FPGA fragments to be interconnected with the core function module so as to change the original single-beat logic into multi-beat logic;
and the conversion optimization module is used for converting the connection structure between the FPGA slices and the maintenance system function module from a star topology structure into a serial structure based on the maintenance relay modules in the FPGA slices.
The star topology is: and the core function module in each FPGA sub-chip is connected with the maintenance system function module.
The serial structure is as follows: the maintenance relay modules in the FPGA sub-slices are sequentially connected in series end to end, and the maintenance relay module in the first FPGA sub-slice is connected with the maintenance system function module.
Preferably, the maintenance relay module includes: the first register group is used for receiving an output signal of the core function module of the current stage through the maintenance interface; the second register group is used for receiving the output signal of the next-stage maintenance relay module; the third register group is used for receiving output signals of the first register group and the second register group and sending the received signals to the upper-level maintenance relay module; the fourth register group is used for receiving the output signal of the upper-level core function module; the fifth register group is used for receiving the output signal of the fourth register group and sending the received signal to the next-stage maintenance relay module; and the sixth register group is used for receiving the output signal of the fourth register group and sending the received signal to the core function module of the current stage through the maintenance interface.
It will be apparent to those skilled in the art that various changes and modifications may be made in the present invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is intended to include such modifications and variations.
Claims (10)
1. An FPGA optimization method for a star topology structure of a maintenance system is characterized by comprising the following steps:
(1) a maintenance relay module is added in each FPGA fragment of the plurality of FPGA fragments and is interconnected with the core function module to change the original single-beat logic into multi-beat logic;
(2) and based on the maintenance relay modules in the FPGA fragments, converting the connection structures between the FPGA fragments and the maintenance system function module from a star topology structure to a serial structure.
2. The FPGA optimization method for the maintenance system star topology according to claim 1, wherein the star topology is: and the core function module in each FPGA sub-chip is connected with the maintenance system function module.
3. The FPGA optimization method for the maintenance system star topology according to claim 1, wherein the serial structure is: and the maintenance relay modules in the FPGA sub-slices are sequentially connected in series end to end, and the maintenance relay module in the first FPGA sub-slice is connected with the maintenance system function module.
4. The FPGA optimization method for the maintenance system star topology according to claim 1, wherein the maintenance relay module comprises: a plurality of register sets.
5. The FPGA optimization method for the maintenance system star topology according to claim 4, wherein the maintenance relay module comprises: the first register group is used for receiving an output signal of the core function module of the current stage through the maintenance interface; the second register group is used for receiving the output signal of the next-stage maintenance relay module; the third register group is used for receiving the output signals of the first register group and the second register group and sending the received signals to the upper-level maintenance relay module; the fourth register group is used for receiving the output signal of the upper-level core function module; the fifth register group is used for receiving the output signal of the fourth register group and sending the received signal to the next-stage maintenance relay module; and the sixth register group is used for receiving the output signal of the fourth register group and sending the received signal to the core function module of the current stage through the maintenance interface.
6. The utility model provides a maintain FPGA optimal system of system star topology structure which is characterized in that, includes:
the system comprises an optimization module, a core function module and a plurality of FPGA fragments, wherein the optimization module is used for adding a maintenance relay module in each FPGA fragment in the plurality of FPGA fragments to be interconnected with the core function module so as to change the original single-beat logic into multi-beat logic;
and the conversion optimization module is used for converting the connection structure between the FPGA fragments and the maintenance system function module from a star topology structure into a serial structure based on the maintenance relay modules in the FPGA fragments.
7. The FPGA optimization system for the maintenance system star topology according to claim 6, wherein the star topology is: and the core function module in each FPGA sub-chip is connected with the maintenance system function module.
8. The FPGA optimization system for the maintenance system star topology according to claim 6, wherein the serial structure is: and the maintenance relay modules in the FPGA sub-slices are sequentially connected in series end to end, and the maintenance relay module in the first FPGA sub-slice is connected with the maintenance system function module.
9. The FPGA optimization system for the maintenance system star topology according to claim 6, wherein the maintenance relay module comprises: a plurality of register sets.
10. The FPGA optimization system for the maintenance system star topology according to claim 9, wherein the maintenance relay module comprises: the first register group is used for receiving an output signal of the core function module of the current stage through the maintenance interface; the second register group is used for receiving the output signal of the next-stage maintenance relay module; the third register group is used for receiving the output signals of the first register group and the second register group and sending the received signals to the upper-level maintenance relay module; the fourth register group is used for receiving the output signal of the upper-level core function module; the fifth register group is used for receiving the output signal of the fourth register group and sending the received signal to the next-stage maintenance relay module; and the sixth register group is used for receiving the output signal of the fourth register group and sending the received signal to the core function module of the current stage through the maintenance interface.
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