CN111709032A

CN111709032A - Method, system, equipment and medium for realizing PFR function on multiple partitions

Info

Publication number: CN111709032A
Application number: CN202010470162.7A
Authority: CN
Inventors: 张莉
Original assignee: Suzhou Inspur Intelligent Technology Co Ltd
Current assignee: Suzhou Inspur Intelligent Technology Co Ltd
Priority date: 2020-05-28
Filing date: 2020-05-28
Publication date: 2020-09-25

Abstract

The invention discloses a method, a system, equipment and a storage medium for realizing PFR function on various partitions, wherein the method comprises the following steps: responding to a pre-starting mode for starting the PFR, and judging the current partition type of the system; responding to the current partition type of the system being a single partition or a double partition, the slave node sends a PFR preparation completion signal to the master node, and responding to the master node completing a pre-starting mode of the PFR, the master node sends a starting signal to the PCH card; in response to the fact that the current partition type of the system is a four-partition, any node sends a starting signal to the PCH buckle card; and responding to the PCH fastening card to receive a starting signal, and starting a PFR normal working mode. The scheme provided by the invention saves the requirement of judging the chip through the interaction of the slave node and the master node, and can freely realize the PFR function for different partition conditions.

Description

Method, system, equipment and medium for realizing PFR function on multiple partitions

Technical Field

The present invention relates to the field of servers, and more particularly, to a method, system, computer device, and readable medium for implementing PFR functions on multiple partitions.

Background

With the development of information technology, the application of the server is more and more extensive. In government, finance, energy and other industries, the demands for large core databases, virtualization integration, memory computing and high-performance computing are higher and higher, and the advantages of 8-way servers are widely applied.

In the multi-way server, each main board is provided with two CPUs, a BMC chip and an optional plug-in PCH (south bridge integrated) card. Four main boards can be inserted into the whole case to form a set of eight-path system, and the whole set of eight-path system, two four-path system or four two-path system can be flexibly configured through hardware setting. For different partition conditions, a PFR (Platform Firmware protection and recovery) function needs to be implemented, at this time, a CPLD (Complex Programmable Logic Device) control chip may be added on a backplane connecting four motherboards, and is used to interact with an FPGA (Field Programmable GATE Array) chip on each motherboard, where the CPLD may obtain configuration information of the whole machine, such as a specific partition mode, and may also obtain a working state of each motherboard, such as a stage where the PFR function is currently located. In this way, the FPGA resource on each motherboard is occupied for interaction with the CPLD, and the interaction of the whole system must be realized only by one control chip-CPLD.

Disclosure of Invention

In view of this, embodiments of the present invention provide a method, a system, a computer device, and a computer-readable storage medium for implementing a PFR function on multiple partitions, so that the requirement of a judgment chip is saved by interaction between a slave node and a master node, and the PFR function can be freely implemented for different partition conditions. The use of devices is saved from the aspect of design, the cost is reduced, and the PFR function of each partition of each node is flexibly realized.

Based on the above object, an aspect of the embodiments of the present invention provides a method for implementing PFR functions on multiple partitions, including the following steps: responding to a pre-starting mode for starting the PFR, and judging the current partition type of the system; responding to the current partition type of the system being a single partition or a double partition, the slave node sends a PFR preparation completion signal to the master node, and responding to the master node completing a pre-starting mode of the PFR, the master node sends a starting signal to the PCH card; in response to the fact that the current partition type of the system is a four-partition, any node sends a starting signal to the PCH buckle card; and responding to the PCH fastening card to receive a starting signal, and starting a PFR normal working mode.

In some embodiments, the determining the current partition type of the system includes: and judging the partition mode according to the mode identifier, and judging a master node and a slave node according to the node identifier.

In some embodiments, the master node sending a power-on signal to the PCH cardholder includes: and the master node sends a synchronous starting signal to each slave node.

In some embodiments, sending a power-on signal from any node to the PCH cardholder includes: and any node sends a synchronous starting signal to other nodes.

In another aspect of the embodiments of the present invention, a system for implementing PFR functions on multiple partitions is further provided, including: the judging module is configured to respond to a pre-starting mode for starting the PFR and judge the current partition type of the system; the system comprises a first partition module, a second partition module and a master node, wherein the first partition module is configured to respond to the fact that the current partition type of the system is a single partition or a double partition, the slave node sends a PFR preparation completion signal to the master node, and respond to the fact that the master node completes a pre-starting mode of the PFR, and the master node sends a starting signal to a PCH card; the second partition module is configured to respond that the current partition type of the system is a four-partition, and any node sends a starting signal to the PCH buckle card; and the execution module is configured to respond to the PCH buckle card and receive a starting signal and start a PFR normal working mode.

In some embodiments, the determining module is further configured to: and judging the partition mode according to the mode identifier, and judging a master node and a slave node according to the node identifier.

In some embodiments, the first partitioning module is further configured to: and the master node sends a synchronous starting signal to each slave node.

In some embodiments, the second partitioning module is further configured to: and any node sends a synchronous starting signal to other nodes.

In another aspect of the embodiments of the present invention, there is also provided a computer device, including: at least one processor; and a memory storing computer instructions executable on the processor, the instructions when executed by the processor implementing the steps of the method as above.

In a further aspect of the embodiments of the present invention, a computer-readable storage medium is also provided, in which a computer program for implementing the above method steps is stored when the computer program is executed by a processor.

The invention has the following beneficial technical effects: the requirement for judging the chip is saved through the interaction of the slave node and the master node, and the PFR function can be freely realized under different partition conditions. The use of devices is saved from the aspect of design, the cost is reduced, and the PFR function of each partition of each node is flexibly realized.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other embodiments can be obtained by using the drawings without creative efforts.

FIG. 1 is a schematic diagram of an embodiment of a method for implementing PFR functions on multiple partitions according to the present invention;

FIG. 2 is a schematic diagram of partition mode setting and node setting provided by the present invention;

FIG. 3 is a schematic diagram of a computing node signal transmission according to the present invention;

fig. 4 is a schematic hardware structure diagram of an embodiment of a computer device that implements PFR functions on multiple partitions according to the present invention.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention more apparent, the following embodiments of the present invention are described in further detail with reference to the accompanying drawings.

It should be noted that all expressions using "first" and "second" in the embodiments of the present invention are used for distinguishing two entities with the same name but different names or different parameters, and it should be noted that "first" and "second" are merely for convenience of description and should not be construed as limitations of the embodiments of the present invention, and they are not described in any more detail in the following embodiments.

In view of the above objects, a first aspect of embodiments of the present invention proposes an embodiment of a method for implementing PFR functions on multiple partitions. Fig. 1 is a schematic diagram illustrating an embodiment of a method for implementing PFR functions on various partitions according to the present invention. As shown in fig. 1, the embodiment of the present invention includes the following steps:

s1, responding to the pre-starting mode of starting the PFR, and judging the current partition type of the system;

s2, in response to the fact that the current partition type of the system is single partition or double partition, the slave node sends a PFR preparation completion signal to the master node, and in response to the fact that the master node completes the pre-starting mode of the PFR, the master node sends a starting signal to the PCH card;

s3, responding to the fact that the current partition type of the system is a four-partition, and sending a starting signal to the PCH buckle card by any node; and

s4, responding to the PCH card receiving the starting signal, starting the PFR normal working mode.

Each computing node has a BMC (Baseboard Management Controller) and an FPGA chip, and when the computing node is a master node, a PCH card is inserted, and when the computing node is a slave node, the PCH card is not inserted into the computing node. The PCH card has a PCH chip and a flash memory (BIOS).

PFR (platform firmware protection recovery) functionality is a completely new standard, providing full protection for servers and providing security against known and unknown vulnerabilities. The goal of PFR technology is to provide resiliency by protecting platform assets, detecting corrupted firmware and malicious or erroneous behavior, and restoring the platform to a known good state. PFR functions fulfill protection, detection and recovery functions as required by NIST. The PFR function has mainly two modes of operation: a pre-start mode and a normal operating mode. In the pre-starting mode, the FPGA checks the BMC and the BIOS FLASH, and the like; in the normal starting mode, a PCH/BMC master control false chip reads the chip content, and realizes the configuration and program loading of the BMC or the PCH. Under two working modes, the SPI signal to Flash realizes the switching through SPI mux.

And responding to the starting of the pre-starting mode of the PFR, and judging the current partition type of the system. In some embodiments, the determining the current partition type of the system includes: and judging the partition mode according to the mode identifier, and judging a master node and a slave node according to the node identifier. Fig. 2 is a schematic diagram illustrating partition mode setting and node setting provided by the present invention. For the partition setting of the system, different partitions are set through hardware jump caps, and when the MODE [1:0] is 00, the system is a single partition, namely, a set of eight-path system is formed by four computing nodes; when the MODE [1:0] is 01, the system is a double-partition system, namely two sets of four-way systems, the computing node 0 and the computing node 1 form a set of system, the computing node 2 and the computing node 3 form a set of system, and the two sets of systems do not influence each other; when the MODE [1:0] is 10, the system is 4 partitions, namely four sets of two-path systems, and the four computing nodes are respectively one set of independent systems and do not influence each other. Different states of MODE signals are set through the position of the jump cap and are given to the FPGA chip of each mainboard, so that the electrification and other functions of each computing node are controlled. The master-slave relationship of each computing node not only depends on the setting of a system mode, but also is related to the specific position of the computing node inserted in the system, and the FPGA of the computing node judges the specific position of the node through MS1 and MS 0. When MS [1:0] ═ 11, the computational node is node 0; when MS [1:0] is 10, the calculation node is node 1; when MS [1:0] is 01, the computing node is node 2; when MS [1:0] ═ 00, the compute node is node 3. When the system is a single partition, the computing node 0 is a master node, and the

computing nodes

1, 2 and 3 are slave nodes; when the system is in a double-partition area, the

computing nodes

0 and 2 are main nodes, and the computing nodes 1 and 3 are slave nodes; when the system is 4 partitions, the four computing nodes are respectively the main nodes.

For the double-partition and single-partition modes, no PCH (physical channel) is buckled on the slave node, at the moment, a program can be set in the FPGA, and the check of a BIOS (basic input output System) FLASH is skipped; however, the master node has no way to know the PFR operating status of the slave node, i.e., whether to complete the pre-boot mode of the PFR and whether to start the normal boot mode. The embodiment of the invention simplifies and uses a plurality of judgment signals to serve as the interactive signals of the FPGA state between the nodes, and does not need an external CPLD to acquire the PFR working state of the node FPGA. After the pre-boot mode is completed, the system is normally booted, when the BMC or the BIOS false is read, the system works in the normal boot mode, and each computing node completes the respective normal boot mode.

And in response to the fact that the current partition type of the system is a single partition or a double partition, the slave node sends a PFR preparation completion signal to the master node, and in response to the fact that the master node completes a pre-starting mode of the PFR, the master node sends a starting signal to the PCH card. Fig. 3 is a schematic diagram illustrating the signal transmission of the computing node provided by the present invention. An embodiment of the present invention will be specifically described with reference to fig. 3. When the system AC (alternating current) is electrified, the FPGA starts to work after the P3V3_ STBY electricity of the FPGA is electrified, at the moment, a pre-starting mode of the PFR can be started, the channel from the FPGA to the FLASH is gated, and the FPGA reads and checks the contents of the backup BMC and the BIOS FLASH. After the partial content is completed, the FPGA of the slave node sends a PRF _ OK _4S or PRF _ OK _8S signal to the master node. Each computing node judges whether the PRF _ OK _4S or PRF _ OK _8S signal is an input signal or an output signal according to the position of the system where the computing node is located and the partition setting of the system. For example, when the system is single-partition, the

computing nodes

1, 2 and 3 are slave nodes, and send a PRF _ OK _8S signal to the master computing node 0; when the system is in a double-partition area, the computing nodes 1 and 3 are slave nodes and send PRF _ OK _4S signals to the

main computing nodes

0 and 1; when the system is 4 partitions, all the computing nodes are the main computing node, and the step is not needed.

After receiving the PRF _ OK signal sent by the slave node, the master node informs the slave node to prepare to send an RSMRST signal to the PCH board, the master node sends PRE _ RSMRST _4S or PRE _ RSMRST _8S to the slave node, and after receiving the signal, the slave node prepares to start a subsequent normal power-on step: when the system is a single partition, the computing node 0 is a master node and sends a PRE _ RSMRST _8S signal to the

slave computing nodes

1, 2 and 3; when the system is in a double-partition area, the

computing nodes

0 and 2 are main nodes and send PRE _ RSMRST _4S signals to the slave computing nodes 1 and 3; when the system is 4 partitions, all the computing nodes are master computing nodes, and the step is not carried out.

And responding to the condition that the current partition type of the system is the four-partition, and sending a starting signal to the PCH buckle card by any node. The master node sends RSMRST _ N to PCH: when the system is a single partition, the computing node 0 is a main node and sends RSMRST _ N to the PCH card; when the system is in a double-partition area, the

computing nodes

0 and 2 are main nodes and send RSMRST _ N to PCH buckles inserted into the nodes; when the system is 4 partitions, all the computing nodes are the main computing nodes and send RSMRST _ N to PCH buckles inserted on the nodes.

And the PFR pre-starting mode is completed, then each node starts to carry out respective normal power-on time sequence and the steps of reading FLASH, and the PFR normal working mode is carried out. If the whole system starts the PFR function, all nodes need to be kept consistent, and when a single partition, a double partition and a four partition are used, one computing node is SET to start the PFR function and needs to be synchronized to other nodes, namely, the master node sends a PFR _ SET signal to other nodes for synchronization. In some embodiments, the master node sending a power-on signal to the PCH cardholder includes: and the master node sends a synchronous starting signal to each slave node. In some embodiments, sending a power-on signal from any node to the PCH cardholder includes: and any node sends a synchronous starting signal to other nodes.

It should be particularly noted that, the steps in the embodiments of the method for implementing PFR functions on multiple partitions described above may be mutually intersected, replaced, added, or deleted, and therefore, these reasonable permutations and combinations should also belong to the scope of the present invention, and should not limit the scope of the present invention to the embodiments.

In view of the above object, a second aspect of the embodiments of the present invention provides a system for implementing PFR functions on multiple partitions, including: the judging module is configured to respond to a pre-starting mode for starting the PFR and judge the current partition type of the system; the system comprises a first partition module, a second partition module and a master node, wherein the first partition module is configured to respond to the fact that the current partition type of the system is a single partition or a double partition, the slave node sends a PFR preparation completion signal to the master node, and respond to the fact that the master node completes a pre-starting mode of the PFR, and the master node sends a starting signal to a PCH card; the second partition module is configured to respond that the current partition type of the system is a four-partition, and any node sends a starting signal to the PCH buckle card; and the execution module is configured to respond to the PCH buckle card and receive a starting signal and start a PFR normal working mode.

In view of the above object, a third aspect of the embodiments of the present invention provides a computer device, including: at least one processor; and a memory storing computer instructions executable on the processor, the instructions being executable by the processor to perform the steps of: s1, responding to the pre-starting mode of starting the PFR, and judging the current partition type of the system; s2, in response to the fact that the current partition type of the system is single partition or double partition, the slave node sends a PFR preparation completion signal to the master node, and in response to the fact that the master node completes the pre-starting mode of the PFR, the master node sends a starting signal to the PCH card; s3, responding to the fact that the current partition type of the system is a four-partition, and sending a starting signal to the PCH buckle card by any node; and S4, responding to the PCH card receiving the starting signal, starting the PFR normal working mode.

Fig. 4 is a schematic hardware structure diagram of an embodiment of the computer device for implementing PFR functions on various partitions according to the present invention.

Taking the apparatus shown in fig. 4 as an example, the apparatus includes a processor 301 and a memory 302, and may further include: an input device 303 and an output device 304.

The processor 301, the memory 302, the input device 303 and the output device 304 may be connected by a bus or other means, and fig. 4 illustrates the connection by a bus as an example.

Memory 302, which is a non-volatile computer-readable storage medium, may be used to store non-volatile software programs, non-volatile computer-executable programs, and modules, such as program instructions/modules corresponding to the methods of implementing PFR functionality on various partitions in embodiments of the present application. The processor 301 executes various functional applications of the server and data processing, i.e., the method of implementing PFR functions on various partitions of the above-described method embodiments, by running non-volatile software programs, instructions, and modules stored in the memory 302.

The memory 302 may include a storage program area and a storage data area, wherein the storage program area may store an operating system, an application program required for at least one function; the storage data area may store data created according to the use of a method of implementing the PFR function on various partitions, and the like. Further, the memory 302 may include high speed random access memory, and may also include non-volatile memory, such as at least one magnetic disk storage device, flash memory device, or other non-volatile solid state storage device. In some embodiments, memory 302 optionally includes memory located remotely from processor 301, which may be connected to a local module via a network. Examples of such networks include, but are not limited to, the internet, intranets, local area networks, mobile communication networks, and combinations thereof.

The input device 303 may receive information such as a user name and a password that are input. The output means 304 may comprise a display device such as a display screen.

Program instructions/modules corresponding to one or more methods for implementing PFR functions on various partitions are stored in memory 302 and, when executed by processor 301, perform the methods for implementing PFR functions on various partitions in any of the method embodiments described above.

Any embodiment of a computer apparatus for performing the above method for implementing PFR functions on multiple partitions may achieve the same or similar effects as any of the above method embodiments corresponding thereto.

The invention also provides a computer readable storage medium storing a computer program which, when executed by a processor, performs the method as above.

Finally, it should be noted that, as one of ordinary skill in the art can appreciate that all or part of the processes of the methods of the above embodiments can be implemented by a computer program to instruct related hardware, and the program of the method for implementing PFR functions on various partitions can be stored in a computer readable storage medium, and when executed, the program can include the processes of the embodiments of the methods described above. The storage medium of the program may be a magnetic disk, an optical disk, a Read Only Memory (ROM), a Random Access Memory (RAM), or the like. The embodiments of the computer program may achieve the same or similar effects as any of the above-described method embodiments.

Furthermore, the methods disclosed according to embodiments of the present invention may also be implemented as a computer program executed by a processor, which may be stored in a computer-readable storage medium. Which when executed by a processor performs the above-described functions defined in the methods disclosed in embodiments of the invention.

Further, the above method steps and system elements may also be implemented using a controller and a computer readable storage medium for storing a computer program for causing the controller to implement the functions of the above steps or elements.

Further, it should be appreciated that the computer-readable storage media (e.g., memory) herein can be either volatile memory or nonvolatile memory, or can include both volatile and nonvolatile memory. By way of example, and not limitation, nonvolatile memory can include Read Only Memory (ROM), Programmable ROM (PROM), Electrically Programmable ROM (EPROM), Electrically Erasable Programmable ROM (EEPROM), or flash memory. Volatile memory can include Random Access Memory (RAM), which can act as external cache memory. By way of example and not limitation, RAM is available in a variety of forms such as synchronous RAM (DRAM), Dynamic RAM (DRAM), Synchronous DRAM (SDRAM), Double Data Rate SDRAM (DDRSDRAM), Enhanced SDRAM (ESDRAM), Synchronous Link DRAM (SLDRAM), and Direct Rambus RAM (DRRAM). The storage devices of the disclosed aspects are intended to comprise, without being limited to, these and other suitable types of memory.

Those of skill would further appreciate that the various illustrative logical blocks, modules, circuits, and algorithm steps described in connection with the disclosure herein may be implemented as electronic hardware, computer software, or combinations of both. To clearly illustrate this interchangeability of hardware and software, various illustrative components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. Whether such functionality is implemented as software or hardware depends upon the particular application and design constraints imposed on the overall system. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the disclosed embodiments of the present invention.

The various illustrative logical blocks, modules, and circuits described in connection with the disclosure herein may be implemented or performed with the following components designed to perform the functions herein: a general purpose processor, a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination of these components. A general purpose processor may be a microprocessor, but in the alternative, the processor may be any conventional processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices, e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP, and/or any other such configuration.

The steps of a method or algorithm described in connection with the disclosure herein may be embodied directly in hardware, in a software module executed by a processor, or in a combination of the two. A software module may reside in RAM memory, flash memory, ROM memory, EPROM memory, EEPROM memory, registers, hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art. An exemplary storage medium is coupled to the processor such the processor can read information from, and write information to, the storage medium. In the alternative, the storage medium may be integral to the processor. The processor and the storage medium may reside in an ASIC. The ASIC may reside in a user terminal. In the alternative, the processor and the storage medium may reside as discrete components in a user terminal.

In one or more exemplary designs, the functions may be implemented in hardware, software, firmware, or any combination thereof. If implemented in software, the functions may be stored on or transmitted over as one or more instructions or code on a computer-readable medium. Computer-readable media includes both computer storage media and communication media including any medium that facilitates transfer of a computer program from one place to another. A storage media may be any available media that can be accessed by a general purpose or special purpose computer. By way of example, and not limitation, such computer-readable media can comprise RAM, ROM, EEPROM, CD-ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to carry or store desired program code in the form of instructions or data structures and that can be accessed by a general-purpose or special-purpose computer, or a general-purpose or special-purpose processor. Also, any connection is properly termed a computer-readable medium. For example, if the software is transmitted from a website, server, or other remote source using a coaxial cable, fiber optic cable, twisted pair, Digital Subscriber Line (DSL), or wireless technologies such as infrared, radio, and microwave, then the coaxial cable, fiber optic cable, twisted pair, DSL, or wireless technologies such as infrared, radio, and microwave are included in the definition of medium. Disk and disc, as used herein, includes Compact Disc (CD), laser disc, optical disc, Digital Versatile Disc (DVD), floppy disk, blu-ray disc where disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of the above should also be included within the scope of computer-readable media.

The foregoing is an exemplary embodiment of the present disclosure, but it should be noted that various changes and modifications could be made herein without departing from the scope of the present disclosure as defined by the appended claims. The functions, steps and/or actions of the method claims in accordance with the disclosed embodiments described herein need not be performed in any particular order. Furthermore, although elements of the disclosed embodiments of the invention may be described or claimed in the singular, the plural is contemplated unless limitation to the singular is explicitly stated.

It should be understood that, as used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly supports the exception. It should also be understood that "and/or" as used herein is meant to include any and all possible combinations of one or more of the associated listed items.

The numbers of the embodiments disclosed in the embodiments of the present invention are merely for description, and do not represent the merits of the embodiments.

It will be understood by those skilled in the art that all or part of the steps for implementing the above embodiments may be implemented by hardware, or may be implemented by a program instructing relevant hardware, and the program may be stored in a computer-readable storage medium, and the above-mentioned storage medium may be a read-only memory, a magnetic disk or an optical disk, etc.

Those of ordinary skill in the art will understand that: the discussion of any embodiment above is meant to be exemplary only, and is not intended to intimate that the scope of the disclosure, including the claims, of embodiments of the invention is limited to these examples; within the idea of an embodiment of the invention, also technical features in the above embodiment or in different embodiments may be combined and there are many other variations of the different aspects of the embodiments of the invention as described above, which are not provided in detail for the sake of brevity. Therefore, any omissions, modifications, substitutions, improvements, and the like that may be made without departing from the spirit and principles of the embodiments of the present invention are intended to be included within the scope of the embodiments of the present invention.

Claims

1. A method for performing PFR functions on a plurality of partitions, comprising the steps of:

responding to a pre-starting mode for starting the PFR, and judging the current partition type of the system;

responding to the current partition type of the system being a single partition or a double partition, the slave node sends a PFR preparation completion signal to the master node, and responding to the master node completing a pre-starting mode of the PFR, the master node sends a starting signal to the PCH card;

in response to the fact that the current partition type of the system is a four-partition, any node sends a starting signal to the PCH buckle card; and

and starting a PFR normal working mode in response to the PCH buckle receiving a starting signal.

2. The method of claim 1, wherein determining the current partition type of the system comprises:

and judging the partition mode according to the mode identifier, and judging a master node and a slave node according to the node identifier.

3. The method of claim 1, wherein sending a power-on signal by the master node to the PCH fob comprises:

and the master node sends a synchronous starting signal to each slave node.

4. The method of claim 1, wherein sending a power-on signal from any node to the PCH cardholder comprises:

and any node sends a synchronous starting signal to other nodes.

5. A system for implementing PFR functions on multiple partitions, comprising:

the judging module is configured to respond to a pre-starting mode for starting the PFR and judge the current partition type of the system;

the system comprises a first partition module, a second partition module and a master node, wherein the first partition module is configured to respond to the fact that the current partition type of the system is a single partition or a double partition, the slave node sends a PFR preparation completion signal to the master node, and respond to the fact that the master node completes a pre-starting mode of the PFR, and the master node sends a starting signal to a PCH card;

the second partition module is configured to respond that the current partition type of the system is a four-partition, and any node sends a starting signal to the PCH buckle card; and

and the execution module is configured to respond to the PCH buckle card to receive a starting signal and start a PFR normal working mode.

6. The system of claim 5, wherein the determination module is further configured to:

7. The system of claim 5, wherein the first partition module is further configured to:

and the master node sends a synchronous starting signal to each slave node.

8. The system of claim 5, wherein the second partition module is further configured to:

and any node sends a synchronous starting signal to other nodes.

9. A computer device, comprising:

at least one processor; and

a memory storing computer instructions executable on the processor, the instructions when executed by the processor implementing the steps of the method of any one of claims 1 to 4.

10. A computer-readable storage medium, in which a computer program is stored which, when being executed by a processor, carries out the steps of the method according to any one of claims 1 to 4.