CN111697128B - Method for manufacturing MRAM device - Google Patents

Method for manufacturing MRAM device Download PDF

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CN111697128B
CN111697128B CN201910184568.6A CN201910184568A CN111697128B CN 111697128 B CN111697128 B CN 111697128B CN 201910184568 A CN201910184568 A CN 201910184568A CN 111697128 B CN111697128 B CN 111697128B
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layer
thin film
dielectric layer
metal thin
depositing
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CN111697128A (en
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刘鲁萍
王雷
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CETHIK Group Ltd
Hikstor Technology Co Ltd
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CETHIK Group Ltd
Hikstor Technology Co Ltd
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N50/00—Galvanomagnetic devices
    • H10N50/10—Magnetoresistive devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B61/00—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
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  • Mram Or Spin Memory Techniques (AREA)
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Abstract

The invention provides a preparation method of an MRAM device, which comprises the following steps: providing a substrate, and sequentially depositing a bottom electrode metal layer, a multilayer film of a magnetic tunnel junction and a metal thin film protective layer on the substrate; depositing a dielectric layer on the metal thin film protective layer for the first time; carrying out first photoetching and etching to form a plurality of pre-stored structures with intervals on the substrate; depositing a dielectric layer for the second time; performing second photoetching and etching to form a plurality of storage unit structures on the substrate, and reserving a dielectric layer with the same height as the storage unit structures between two adjacent storage unit structures; depositing a polishing barrier layer; depositing a dielectric layer for the third time; and carrying out chemical mechanical polishing until all polishing barrier layers above the metal film protective layer and the dielectric layer between two adjacent storage unit structures are exposed. The invention can improve the control precision of the polishing end point in the CMP manufacture procedure.

Description

Method for manufacturing MRAM device
Technical Field
The invention relates to the technical field of magnetic memories, in particular to a method for manufacturing an MRAM device.
Background
In recent years, MRAM (Magnetic Random Access Memory) using the magnetoresistive effect of MTJ (Magnetic Tunnel Junction) is considered as a future solid-state nonvolatile Memory, which has the characteristics of high speed read and write, large capacity, and low power consumption.
In the fabrication of an MRAM device, a substrate is provided, a bottom electrode and a Magnetic Tunnel Junction (MTJ) are disposed on the substrate, a metal Ta (tantalum) is formed on the surface of the MTJ, a Polishing stop layer (SiN, for example) and a dielectric layer (TEOS, for example) are sequentially disposed on the metal thin film protection layer, and during a CMP (Chemical Mechanical Polishing) process, the dielectric layer and the Polishing stop layer on the Magnetic Tunnel Junction are removed and a Polishing end point is stopped on the metal thin film protection layer. When the density of the pattern of the MTJ unit is relatively low, in the subsequent process of removing the dielectric layer and stopping the polishing endpoint on the polishing stop layer in the CMP process, the patterning density of the polishing stop layer on the MTJ unit is low, which may not function well in controlling the polishing endpoint, resulting in incomplete or over-polishing in the case of uniform surface flatness across the wafer, or resulting in non-uniform surface flatness across the wafer, which may seriously affect the function of the MRAM device. Because the selection ratios of different thin film materials are different, and no mature grinding fluid product with high selection ratio aiming at TEOS/SiN/Ta exists in the market at present, it is very challenging to accurately stop the polishing end point above the metal thin film protection layer of the magnetic tunnel junction multilayer film structure in the actual CMP process. In order to solve the problem, a method of CMP process and wet etching is adopted in one scheme, which is beneficial to controlling a polishing end point, and CMP polishing generally takes obtained polishing barrier layer information as a control end point, so that the control precision is greatly improved under the existing process. Therefore, how to improve the control accuracy in the CMP process is a problem to be solved.
Disclosure of Invention
In view of the above, the present invention provides a method for manufacturing an MRAM device, which can improve the control accuracy of a polishing endpoint in a CMP process.
The invention provides a preparation method of an MRAM device, which comprises the following steps:
providing a substrate, and sequentially depositing a bottom electrode metal layer, a multilayer film of a magnetic tunnel junction and a metal thin film protective layer on the substrate;
depositing a dielectric layer on the metal thin film protective layer for the first time;
carrying out first photoetching and etching to form a plurality of pre-stored structures with intervals on the substrate;
depositing a dielectric layer for the second time;
performing second photoetching and etching to form a plurality of storage unit structures on the substrate, and reserving a dielectric layer with the same height as the storage unit structures between two adjacent storage unit structures;
depositing a polishing barrier layer;
depositing a dielectric layer for the third time;
and carrying out chemical mechanical polishing until all polishing barrier layers above the metal film protective layer and above the dielectric layer between the two adjacent memory cell structures are exposed.
Optionally, after exposing all polishing barrier layers above the metal thin film protection layer and above the dielectric layer between two adjacent memory cell structures, the method further comprises:
etching the polishing barrier layer, and removing all the polishing barrier layers on the upper surface of the metal thin film protective layer and partial polishing barrier layers on two sides of the metal thin film protective layer at the same time, wherein the thickness of the removed partial polishing barrier layers on the two sides of the metal thin film protective layer is less than or equal to the thickness of a tunneling barrier layer in the magnetic tunnel junction;
depositing a dielectric layer for the fourth time;
carrying out third photoetching and etching, forming an opening above each memory cell structure, exposing the upper surface of the metal film protective layer and the part of the two sides of the metal film protective layer, which is removed with the polishing barrier layer;
and depositing top electrode metal to form a top electrode.
Optionally, a wet etching method is used for etching the polishing barrier layer.
Optionally, the material of the polishing barrier layer is a compound containing nitrogen and silicon.
Optionally, the material of the dielectric layer is SiO 2 FSG, low-K or ultra-K materials.
According to the preparation method of the MRAM device, the dielectric layers with the same height as the memory cell structures are reserved between the two adjacent memory cell structures, then the polishing barrier layer and the dielectric layers are deposited, and chemical mechanical polishing is carried out.
Drawings
FIG. 1 is a flow chart illustrating one embodiment of a method for fabricating an MRAM device of the present invention;
fig. 2 is a schematic structural diagram of a bottom electrode metal layer, a multilayer film of a magnetic tunnel junction, and a metal thin film protection layer deposited on a substrate in sequence according to an embodiment of the present invention;
FIG. 3 is a schematic structural diagram illustrating a first deposition of a dielectric layer on a metal thin film passivation layer according to an embodiment of the present invention;
FIG. 4 is a schematic structural diagram of the first photolithography and etching process according to an embodiment of the present invention;
FIG. 5 is a schematic structural diagram illustrating a second deposition of a dielectric layer according to an embodiment of the present invention;
fig. 6 is a schematic structural diagram after performing second photolithography and etching according to an embodiment of the present invention;
FIG. 7 is a schematic structural view of a polishing stop layer deposited according to an embodiment of the present invention;
FIG. 8 is a schematic diagram showing a third deposition of a dielectric layer;
FIG. 9 is a schematic diagram of a post-CMP structure provided in accordance with an embodiment of the present invention;
FIG. 10 is a flow chart illustrating a method of fabricating an MRAM device according to another embodiment of the invention;
fig. 11 is a schematic structural diagram of a polishing stop layer after etching according to an embodiment of the present invention;
FIG. 12 is a schematic view of a fourth deposition of a dielectric layer according to an embodiment of the present invention;
FIG. 13 is a schematic structural diagram of the third photolithography and etching process according to an embodiment of the present invention;
fig. 14 is a schematic structural diagram after forming a top electrode according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
An embodiment of the present invention provides a method for manufacturing an MRAM device, as shown in fig. 1, the method includes:
s101, providing a substrate, and sequentially depositing a bottom electrode metal layer, a multilayer film of a magnetic tunnel junction and a metal thin film protective layer on the substrate;
referring to fig. 2, in step S101, fig. 2 is a schematic structural diagram of a bottom electrode metal layer, a multilayer film of a magnetic tunnel junction, and a metal thin film protection layer sequentially deposited on a substrate according to an embodiment of the present invention, and as shown in fig. 2, a bottom electrode metal layer 202, a multilayer film 203 of a magnetic tunnel junction, and a metal thin film protection layer 204 are sequentially deposited on a substrate 201. The multilayer film 203 of the magnetic tunnel junction includes a reference layer, a tunneling barrier layer, and a free layer, which are collectively referred to herein as a metal thin film protection layer 204, which may be a layer of metal tantalum Ta, tantalum nitride, or other metals.
S102, depositing a dielectric layer on the metal thin film protective layer for the first time;
referring to fig. 3, in step S102, fig. 3 is a schematic structural diagram of the metal thin film passivation layer after a dielectric layer is deposited for the first time according to the embodiment of the present invention, and as shown in fig. 3, a dielectric layer 205 is deposited on the metal thin film passivation layer 204. The material of the dielectric layer 205 is SiO 2 FSG, low-K or ultra-K materials, e.g. Carbon/Fluorine doped SiO 2 One or more of them.
S103, carrying out first photoetching and etching, and forming a plurality of pre-stored structures with intervals on the substrate;
referring to fig. 4, in step S103, referring to fig. 4, fig. 4 is a schematic structural diagram after performing the first photolithography and etching according to an embodiment of the present invention, as shown in fig. 4, taking two pre-stored structures as an example for explanation, forming two pre-stored structures with an interval on a substrate through photolithography and etching processes, where each pre-stored structure includes a bottom electrode 202, a multilayer film 203 of a magnetic tunnel junction, a metal thin film protection layer 204, and a dielectric layer 205, which are stacked in sequence from bottom to top and have the same size.
S104, depositing a dielectric layer for the second time;
with reference to fig. 5, in step S104, fig. 5 is a schematic structural diagram after depositing a dielectric layer for the second time according to the embodiment of the present invention, and as shown in fig. 5, gaps between a plurality of pre-stored structures are filled by depositing a dielectric layer; since the material of the dielectric layer deposited for the second time is the same as that of the dielectric layer 205 left after etching, the two can be integrated into a whole, and the two can be collectively referred to as a dielectric layer 206.
S105, carrying out second photoetching and etching to form a plurality of storage unit structures on the substrate, wherein a dielectric layer with the same height as the storage unit structures is reserved between every two adjacent storage unit structures;
referring to fig. 6, in step S105, referring to fig. 6, fig. 6 is a schematic structural diagram after performing the second photolithography and etching according to an embodiment of the present invention, as shown in fig. 6, two memory cell structures are formed on the substrate through photolithography and etching processes, each memory cell structure includes a bottom electrode 202 and a multilayer film 203 of a magnetic tunnel junction located on the bottom electrode 202, an upper surface of the multilayer film 203 of the magnetic tunnel junction has a metal thin film protection layer 204, and a size of the multilayer film 203 of the magnetic tunnel junction is equal to a size of the metal thin film protection layer 204 and is smaller than a size of the bottom electrode 202. In particular, a dielectric layer 206 having the same height as the memory cell structure is left between two adjacent memory cell structures.
S106, depositing a polishing barrier layer;
with reference to fig. 7, in step S106, fig. 7 is a schematic structural diagram of the polishing stop layer deposited according to the embodiment of the present invention, as shown in fig. 7, the polishing stop layer is denoted as 207, and the material of the polishing stop layer 207 is a compound containing nitrogen and silicon, such as SiN x ,SiN x H,SiN x CH,Si a C b N c H d Including a combination of one or more of silicon nitride, nitrogen-doped silicon oxide, and nitrogen-doped silicon carbide.
S107, depositing a dielectric layer for the third time;
with reference to fig. 8, in step S107, fig. 8 is a schematic structural diagram after a third deposition of a dielectric layer, and as shown in fig. 8, a dielectric layer 208 is deposited over the polish stop layer 207.
And S108, carrying out chemical mechanical polishing until all polishing barrier layers above the metal film protective layer and above the dielectric layer between the two adjacent memory cell structures are exposed.
Referring to fig. 9, fig. 9 is a schematic diagram of a structure after chemical mechanical polishing according to an embodiment of the present invention in step S108, as shown in fig. 9, in which the polishing stop layer 207 is not removed, and a polishing end point stops at the polishing stop layer 207 above the metal thin film protection layer and above the dielectric layer between two adjacent memory cell structures.
In the method for manufacturing the MRAM device according to the above embodiment, the dielectric layer having the same height as the memory cell structure is left between the two adjacent memory cell structures, and then the polishing stop layer and the dielectric layer are deposited and chemical mechanical polishing is performed.
Further, as shown in fig. 10, after exposing all polishing stop layers above the metal thin film protection layer and above the dielectric layer between two adjacent memory cell structures based on the method flow shown in fig. 1, the method further comprises the following steps:
s109, etching the polishing barrier layer, and removing all polishing barrier layers on the upper surface of the metal film protective layer and partial polishing barrier layers on two sides of the metal film protective layer;
with reference to fig. 11, fig. 11 is a schematic structural diagram of the polishing stop layer after etching according to the embodiment of the present invention, as shown in fig. 11, when etching the polishing stop layer 207 on the basis of the structure shown in fig. 9, the polishing stop layer 207 may be over-etched, and all the polishing stop layers on the upper surface of the metal thin film protection layer 204 and portions of the polishing stop layers on both sides of the metal thin film protection layer 204 are removed at the same time, where the thickness of the removed portions of the polishing stop layers on both sides of the metal thin film protection layer 204 is less than or equal to the thickness of the tunneling barrier layer in the magnetic tunnel junction, that is, the polishing stop layers on both sides of the tunneling barrier layer in the magnetic tunnel junction should not be damaged.
It should be noted that etching is the selective removal of portions of the thin film layer not masked by the resist, either chemically, physically or both, to obtain a pattern on the thin film that is substantially identical to the pattern on the resist film. The etching techniques are mainly classified into dry etching and wet etching. The dry etching mainly utilizes reaction gas and plasma for etching; wet etching mainly utilizes chemical reagents to perform chemical reaction with the material to be etched.
The embodiment of the invention can use dry etching and wet etching, preferably wet etching, and has ideal etching effect. The wet etching process can be completed in a wet cleaning machine or a CMP machine.
Taking polishing barrier layer 207 material as Si 3 N 4 To illustrate, the chemical equation based on wet etching is:
3Si 3 N 4 +27H 2 O+4H 3 PO 4 ＝4(NH 4 ) 3 PO 4 +9H 2 SiO 4 。
s110, depositing a dielectric layer for the fourth time;
with reference to fig. 12, in step S110, fig. 12 is a schematic structural diagram after a fourth deposition of a dielectric layer according to the embodiment of the present invention, as shown in fig. 12, a gap generated after etching is filled by depositing the dielectric layer; the previously left-over dielectric layers 206 and 208 are merged with the newly deposited dielectric layer, collectively referred to as dielectric layer 209;
s111, carrying out third photoetching and etching, forming an opening above each storage unit structure, and exposing the upper surface of the metal film protective layer and the parts of the two sides of the metal film protective layer, which are removed with the polishing barrier layers;
referring to fig. 13, in step S111, fig. 13 is a schematic structural diagram after performing the third photolithography and etching according to the embodiment of the present invention, and as shown in fig. 13, a size of the formed opening 210 is greater than a sum of a size of the metal thin film protection layer 204 and a thickness of the polishing stop layer on both sides of the metal thin film protection layer.
And S112, depositing top electrode metal to form a top electrode.
Referring to fig. 14, in step S112, fig. 14 is a schematic structural diagram after forming the top electrode according to the embodiment of the present invention, and as shown in fig. 14, a top electrode metal is deposited in the opening 210 to form a top electrode 211.
The above process is only one implementation form of the method for manufacturing the MRAM device of the present invention, and the MRAM device manufactured by the present invention improves the electrical interconnection characteristics between the top electrode and the metal thin film protection layer in the MRAM device.
The above description is only for the specific embodiments of the present invention, but the scope of the present invention is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present invention are also within the scope of the present invention. Therefore, the protection scope of the present invention should be subject to the protection scope of the claims.

Claims (5)

1. A method of fabricating an MRAM device, the method comprising:
providing a substrate, and sequentially depositing a bottom electrode metal layer, a multilayer film of a magnetic tunnel junction and a metal thin film protective layer on the substrate;
depositing a dielectric layer on the metal thin film protective layer for the first time;
carrying out first photoetching and etching, etching the bottom electrode metal layer, the multilayer film of the magnetic tunnel junction, the metal thin film protective layer and the dielectric layer above the metal thin film protective layer, and forming a plurality of pre-stored structures with intervals on the substrate;
depositing a dielectric layer for the second time so as to fill the intervals among the plurality of pre-stored structures;
performing second photoetching and etching to etch the plurality of pre-stored structures, forming a plurality of storage unit structures on the substrate, and reserving dielectric layers with the same height as the storage unit structures at intervals between two adjacent storage unit structures;
depositing a polishing barrier layer, and covering the surface of the storage unit structure and the surface of a dielectric layer with the same height as the storage unit structure;
depositing a dielectric layer for the third time;
and carrying out chemical mechanical polishing until all polishing barrier layers above the metal film protective layer and above the dielectric layer between the two adjacent memory cell structures are exposed.
2. The method of claim 1, wherein after exposing all polish stop layers above the metal thin film protective layer and above a dielectric layer between two adjacent memory cell structures, the method further comprises:
etching the polishing barrier layer, and removing all the polishing barrier layers on the upper surface of the metal thin film protective layer and partial polishing barrier layers on two sides of the metal thin film protective layer at the same time, wherein the thickness of the removed partial polishing barrier layers on two sides of the metal thin film protective layer is less than or equal to the thickness of the tunneling barrier layer in the magnetic tunnel junction;
depositing a dielectric layer for the fourth time;
carrying out third photoetching and etching to form an opening above each storage unit structure, and exposing the upper surface of the metal thin film protective layer and the parts of the two sides of the metal thin film protective layer, from which the polishing barrier layers are removed;
and depositing top electrode metal to form a top electrode.
3. The method of claim 2, wherein the polish stop layer is etched by wet etching.
4. The method of claim 1, wherein the material of the polish stop layer is a nitrogen and silicon containing compound.
5. The method of claim 1, wherein the dielectric layerIs made of SiO 2 FSG, low-K or ultra-K materials.
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KR20100079960A (en) * 2008-12-31 2010-07-08 삼성전자주식회사 Method for formation of flash memory
US9082695B2 (en) * 2011-06-06 2015-07-14 Avalanche Technology, Inc. Vialess memory structure and method of manufacturing same
GB2526456B (en) * 2013-03-15 2020-07-15 Intel Corp Logic chip including embedded magnetic tunnel junctions
US20190013353A1 (en) * 2016-03-07 2019-01-10 Intel Corporation Approaches for integrating stt-mram memory arrays into a logic processor and the resulting structures

Patent Citations (2)

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Publication number Priority date Publication date Assignee Title
WO2017052586A1 (en) * 2015-09-25 2017-03-30 Intel Corporation High density memory array with self-aligned via
CN109087993A (en) * 2017-06-13 2018-12-25 上海磁宇信息科技有限公司 A method of making magnetic RAM top electrode hole

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