CN111694759B - Flash memory management method and flash memory - Google Patents

Flash memory management method and flash memory Download PDF

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Publication number
CN111694759B
CN111694759B CN201910377863.3A CN201910377863A CN111694759B CN 111694759 B CN111694759 B CN 111694759B CN 201910377863 A CN201910377863 A CN 201910377863A CN 111694759 B CN111694759 B CN 111694759B
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page address
address mapping
partial page
mapping table
flash memory
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CN111694759A (en
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邱日圣
许智宏
萧智伟
陈昱维
叶庭玮
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Asolid Technology Co Ltd
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Asolid Technology Co Ltd
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
    • G06F12/023—Free address space management
    • G06F12/0238—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
    • G06F12/0246—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory in block erasable memory, e.g. flash memory
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
    • G06F12/0292—User address space allocation, e.g. contiguous or non contiguous base addressing using tables or multilevel address translation means
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Read Only Memory (AREA)

Abstract

The present disclosure provides a flash memory management method and a flash memory. The flash memory management method comprises the following steps: generating a plurality of partial page address mapping tables in the random access memory; and when the first partial page address mapping table of the partial page address mapping tables is released, moving the data stored in the second partial page address mapping table which is newly generated in the partial page address mapping tables to the first partial page address mapping table.

Description

Flash memory management method and flash memory
Technical Field
The present disclosure relates to a flash memory management method and a flash memory, and more particularly, to a flash memory management method and a flash memory for improving random writing performance.
Background
In performance evaluation of flash memory, random writing speed (or 4K random writing speed) is an important evaluation index. In randomly writing data, the flash memory controller must continuously generate a page mapping table and perform operations to write the page mapping table to the flash memory or read the page mapping table from the flash memory to the random access memory. Frequent updates of the page mapping table may cause a decrease in random write speed.
Disclosure of Invention
The disclosure provides a flash memory management method and a flash memory, which effectively prevent the speed of random writing from being reduced.
The present disclosure proposes a flash memory management method, comprising: generating a plurality of partial page address mapping tables in the random access memory; and when the first partial page address mapping table of the partial page address mapping tables is released, moving the data stored in the second partial page address mapping table which is newly generated in the partial page address mapping tables to the first partial page address mapping table.
The present disclosure proposes a flash memory comprising: the memory unit module comprises a plurality of entity memory groups, wherein each entity memory group comprises a plurality of entity memory pages; and a controller coupled to the memory cell module. The controller generates a plurality of partial page address mapping tables in the random access memory; and when the first partial page address mapping table of the partial page address mapping tables is released, moving the data stored in the second partial page address mapping table which is newly generated in the partial page address mapping tables to the first partial page address mapping table.
Based on the above, the flash memory management method and the flash memory of the present disclosure will move the data stored in the second partial page address mapping table generated newly to the first partial page address mapping table when the first partial page address mapping table of the random access memory is released. Therefore, the random writing speed of the flash memory can be effectively prevented from being reduced.
In order to make the above features and advantages of the present disclosure more comprehensible, embodiments accompanied with figures are described in detail below.
Drawings
Fig. 1 is a block diagram of a flash memory according to an embodiment of the present disclosure.
Fig. 2A to 2D are schematic diagrams of a flash memory management method according to an embodiment of the disclosure.
FIG. 3 is a diagram of a partial page address mapping table according to one embodiment of the present disclosure.
Fig. 4 is a flowchart of a flash memory management method according to an embodiment of the present disclosure.
[ symbolic description ]
100: flash memory
110: controller for controlling a power supply
120: memory cell module
200: partial page address mapping table queue
201: indicator(s)
211. 212, 300: partial page address mapping table
SE1 to SE4: section column
301: mapping entity memory groups
302: mapping physical page addresses
303: mapping segments
S401, S402: flash memory management method
Detailed Description
Fig. 1 is a block diagram of a flash memory according to an embodiment of the present disclosure.
Referring to fig. 1, a flash memory 100 according to an embodiment of the disclosure includes a controller 110 and a memory cell module 120 coupled to the controller 110. The controller 110 may perform management operations with respect to the memory cell module 120. The memory cell module 120 includes a plurality of physical memory banks (or physical blocks). Each physical memory group includes a plurality of physical memory pages (or referred to as physical pages, physical pages). Each physical memory page includes a plurality of segments (or called fragments), each segment being, for example, 4 kbytes in size.
Fig. 2A to 2D are schematic diagrams of a flash memory management method according to an embodiment of the disclosure.
Referring to fig. 2A and 1, fig. 2A shows an example of a partial page address mapping table (Partial Page address Mapping Table, PPMT) queue 200 stored in the ram of the flash memory 100. PPMT queue 200 may include PPMT group 0 through PPMT group M. Each PPMT group may include page 0 through page N, and each page may store one PPMT data. In an initial state where no page of each PPMT group has stored PPMT data, the indicator 201 refers to the address of page 0 of PPMT group 0. It is noted that in full page address mapping, a logical page will map to a physical page; in partial page address mapping, a logical page may be mapped to segments of multiple different physical pages.
Referring to fig. 2B and 1, after performing a plurality of random write operations (e.g., 4K random write operations), PPMTs are sequentially built in the PPMT queue 200. For example, the PPMT of the PPMT group 0, the PPMT of the PPMT group 1, and the PPMT of the PPMT group 1 are stored, that is, the controller 110 can obtain the logical entity mapping relationship of the partial page address mapping according to the PPMT (that is, the PPMT of the PPMT group 0, the PPMT of the PPMT group 1, and the PPMT is in the first state). After the PPMT is established, the indicator 201 refers to the address of the page 2 of the PPMT group 1 to indicate the address of the next PPMT to be established.
Referring to fig. 2C and fig. 1, when a partial page address mapping table (PPMT) 211 (also referred to as a first partial page address mapping table) is released by the controller 110 (i.e., the contents of the PPMT211 are cleared), the controller 110 does not move the data of the PPMT211 to the release queue, but moves the mapping data stored in a most recently generated partial page address mapping table (PPMT) 212 (also referred to as a second partial page address mapping table) to the PPMT211.
Referring to fig. 2D and fig. 1, after the data stored in the PPMT 212 is moved to the PPMT211, the controller 110 points the indicator 201 to the address of the page 1 of the PPMT group 1, and sets the PPMT of the page 1 of the PPMT group 1 to a second state, in which the controller 110 cannot obtain the logical entity mapping relationship according to the PPMT of the page 1 of the PPMT group 1.
Through the above PPMT reforming method, the update times of the PPMT can be effectively reduced, and the access operation of the PPMT between the random access memory and the memory cell module 120 can be reduced.
FIG. 3 is a diagram of a partial page address mapping table according to one embodiment of the present disclosure.
Referring to FIG. 3, a partial page address mapping table 300 according to an embodiment of the present disclosure includes section fields SE1 through SE4. Each section field comprises a record mapping entity page address, a mapping section and a mapping entity memory group. Taking section field SE1 as an example, mapped entity memory group 301 recorded in section field SE1 is entity memory group B 1 The mapped physical page address 302 recorded in section column SE1 is P 1 (i.e., entity memory group B) 1 P (th) 1 Page), and the mapped segment 303 recorded in section field SE1 is S 1 (i.e., entity memory group B) 1 P (th) 1 S of page 1 Segment data). The contents recorded by the section columns SE1 to SE4 can be known to correspond to the contentsThe data in the logical page addresses of the partial page address mapping table 300 are stored in: physical memory group B 1 P of (b) 1 S of page 1 Segment, physical memory group B 2 P of (b) 2 S of page 2 Segment, physical memory group B 3 P of (b) 3 S of page 3 Segmentation and physical memory group B 4 P of (b) 4 S of page 4 Segmentation. Although the above embodiment illustrates that the partial page address mapping table 300 includes four section fields, the present disclosure is not limited thereto. In other embodiments, the partial page address mapping table 300 may also include eight or other numbers of section fields.
Fig. 4 is a flowchart of a flash memory management method according to an embodiment of the present disclosure.
Referring to fig. 4, in step S401, a plurality of partial page address mapping tables are generated in the random access memory.
In step S402, when the first partial page address mapping table of the partial page address mapping tables is released, the data stored in the second partial page address mapping table newly generated in the partial page address mapping tables is moved to the first partial page address mapping table.
In summary, in the flash memory management method and the flash memory of the present disclosure, when the first partial page address mapping table of the random access memory is released, the data stored in the second partial page address mapping table that is newly generated is moved to the first partial page address mapping table. The method for managing the flash memory can be used for reforming the partial page address mapping table, so that the updating times of the partial page address mapping table, namely the times of reading the partial page address mapping table from the flash memory to the random access memory and writing the partial page address mapping table into the flash memory from the random access memory, can be greatly reduced. In addition, the flash memory management method of the present disclosure does not require the use of a release queue. Therefore, the random writing speed of the flash memory can be effectively prevented from being reduced.
Although the present disclosure has been described with reference to the above embodiments, it should be understood that the invention is not limited thereto, but rather by one skilled in the art, as long as modifications and variations can be made thereto without departing from the spirit and scope of the present disclosure as defined by the appended claims.

Claims (10)

1. A method for managing flash memory, comprising:
generating a plurality of continuous partial page address mapping tables in the random access memory according to the random write operation of the flash memory for a plurality of times;
in the generation process of the partial page address mapping tables, sequentially increasing pages corresponding to an indicator;
when a first partial page address mapping table of the partial page address mapping tables is released, moving data stored in a second partial page address mapping table which is newly generated in the partial page address mapping tables to the first partial page address mapping table, and changing the indicator to correspond to the second partial page address mapping table; and
the second partial page address mapping table is set to an unreadable state,
wherein the indicator corresponds to a storage page of data of the newly added partial page address mapping table at the next write operation.
2. The flash memory management method of claim 1, further comprising: the data of the first partial page address mapping table is not moved to a release queue.
3. The method of claim 1, wherein each of the partial page address mapping tables comprises a plurality of section fields, each of the section fields comprising a mapping entity page address, a mapping segment, and a mapping entity memory group.
4. The flash memory management method of claim 1, wherein the first partial page address mapping table is in a first state in which a controller can obtain a logical entity mapping relationship from the first partial page address mapping table.
5. The flash memory management method of claim 4, further comprising: and setting the second partial page address mapping table to a second state, wherein the controller cannot obtain the logical entity mapping relation according to the second partial page address mapping table in the second state.
6. A flash memory, comprising:
the memory unit module comprises a plurality of entity memory groups, wherein each entity memory group comprises a plurality of entity memory pages; and
a controller coupled to the memory cell module, wherein the controller generates a plurality of consecutive partial page address mapping tables in the random access memory according to a plurality of random write operations of the flash memory;
in the generation process of the partial page address mapping tables, sequentially increasing pages corresponding to an indicator;
when a first partial page address mapping table of the partial page address mapping tables is released, moving data stored in a second partial page address mapping table which is newly generated in the partial page address mapping tables to the first partial page address mapping table, and changing the indicator to correspond to the second partial page address mapping table; and
the second partial page address mapping table is set to an unreadable state,
wherein the indicator corresponds to a storage page of data of the newly added partial page address mapping table at the next write operation.
7. The flash memory of claim 6 wherein the controller does not move data of the first partial page address mapping table to a release queue.
8. The flash memory of claim 6 wherein each of the partial page address maps includes a plurality of section fields, each of the section fields including a map physical page address, a map segment, and a map physical memory group.
9. The flash memory of claim 6, wherein the first partial page address mapping table is in a first state in which a controller can obtain a logical entity mapping relationship from the first partial page address mapping table.
10. The flash memory of claim 9, wherein the controller sets the second partial page address mapping table to a second state in which the controller is unable to obtain the logical entity mapping relationship from the second partial page address mapping table.
CN201910377863.3A 2019-03-14 2019-05-06 Flash memory management method and flash memory Active CN111694759B (en)

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Citations (5)

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Publication number Priority date Publication date Assignee Title
WO2016082227A1 (en) * 2014-11-29 2016-06-02 华为技术有限公司 Data storage method and apparatus
CN105868122A (en) * 2016-03-28 2016-08-17 深圳市硅格半导体股份有限公司 Data processing method and device for quick flashing storage equipment
CN108446238A (en) * 2017-02-14 2018-08-24 点序科技股份有限公司 Flash memory and management method thereof
CN109299021A (en) * 2017-07-24 2019-02-01 阿里巴巴集团控股有限公司 Page migration method, apparatus and central processing unit
TWI652679B (en) * 2017-12-08 2019-03-01 旺宏電子股份有限公司 Memory controller, memory system and control method

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101510120B1 (en) * 2008-11-21 2015-04-10 삼성전자주식회사 Memory device and management method of memory device
TWI604307B (en) * 2014-10-31 2017-11-01 慧榮科技股份有限公司 Data storage device and flash memory control method

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2016082227A1 (en) * 2014-11-29 2016-06-02 华为技术有限公司 Data storage method and apparatus
CN105868122A (en) * 2016-03-28 2016-08-17 深圳市硅格半导体股份有限公司 Data processing method and device for quick flashing storage equipment
CN108446238A (en) * 2017-02-14 2018-08-24 点序科技股份有限公司 Flash memory and management method thereof
CN109299021A (en) * 2017-07-24 2019-02-01 阿里巴巴集团控股有限公司 Page migration method, apparatus and central processing unit
TWI652679B (en) * 2017-12-08 2019-03-01 旺宏電子股份有限公司 Memory controller, memory system and control method

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