CN112559384B - Dynamic partitioning method for hybrid solid-state disk based on nonvolatile memory - Google Patents
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Abstract
The invention discloses a dynamic partitioning method of a hybrid solid-state disk based on a nonvolatile memory, which divides a PCM (pulse code modulation) of the nonvolatile memory into two areas, namely a cache area and a data area, wherein the cache area is used as a memory inside the solid-state disk, and the data area and a flash memory are uniformly addressed to store data ejected from the cache area. And dynamically partitioning the cache region and the data region to obtain the optimal proportion between the cache region and the data region, so that the hybrid solid-state disk can obtain the optimal performance under different loads.
Description
Technical Field
The invention relates to the technical field of computer external storage, in particular to a dynamic partitioning method for a hybrid solid-state disk based on a nonvolatile memory.
Background
Solid state disks are increasingly common in everyday life, and typically include multiple flash memory chips, each of which includes one or more dies, each of which includes multiple blocks, each of which contains multiple pages. A block is the smallest unit of erase in flash memory and a page is the smallest unit of write.
The solid state disk operates in a defined unit of erase (i.e., the block size of data erased during an erase operation) and a defined unit of write (i.e., the block size of data written during a write operation). The difference in block size between the unit of erase and the unit of write usually requires the use of a flash translation layer (flashtranssliationlayer). FTL is essentially an address mapping scheme, and address mapping can be implemented using page mapping, block mapping, or hybrid mapping. In the conventional solid-state disk, a DFTL algorithm of page mapping is generally adopted, the algorithm is based on a locality principle, a global mapping directory and a part of commonly used mapping tables are stored in a cache inside the solid-state disk, and the DFTL can obtain better performance in the solid-state disk with a single medium. The phase change memory is a novel low-power consumption solid-state memory device, is considered as a new generation of high-performance memory device capable of replacing a flash memory, and has the characteristics of bit-based modification, in-situ update, long service life and the like. Therefore, it can be added to a solid-state disk to constitute a hybrid solid-state disk with flash memory. In the hybrid solid-state disk, because the difference between the reading performance of the flash memory and the phase change memory is not large (the page reading time of the flash memory is 10-100 ns, but 2 KB-4 KB data can be read each time, the time of the phase change memory reading once is about 10-50 mus, and 1B data is read each time), the difference between the writing performance of the flash memory and the writing performance of the DRAM is not as large as that between the phase change memory and the DRAM, meanwhile, the flash memory has the characteristics of large capacity and the like, so that the phase change memory can be used as the memory part of the solid-state disk to enhance the reading and writing performance of the solid-state disk, and the service life of the flash memory is prolonged.
Disclosure of Invention
The invention aims to solve the problems that: a dynamic partitioning method of a hybrid solid state disk based on a nonvolatile memory is provided, wherein the nonvolatile memory PCM is divided into two areas, namely a cache area and a data area, the cache area is used as a memory inside the solid state disk, the data area and a flash memory are uniformly addressed, and data ejected from the cache area are stored. And dynamically allocating the cache region and the data region to obtain the optimal proportion between the cache region and the data region, so that the hybrid solid-state disk can obtain the optimal performance under different loads.
The technical scheme provided by the invention for solving the problems is as follows: a dynamic partitioning method for a hybrid solid-state disk based on a nonvolatile memory is characterized by comprising the following steps: the method comprises the following steps of,
(1) the initial stage, dividing PCM into a buffer area and a data area, setting a counter for each page of the PCM data area, assigning an initial value to the counter of the page written for the first time, and adding one if the page in the data area is updated, and subtracting one if the page is not updated;
(2) after a certain period, counting the value of a counter of each page in the data area, performing cluster analysis on the data by using a K-means algorithm, dividing the data into three types of data, and calculating the mass center of each type of data; dividing the three groups of data into a hot group, a warm group and a cold group from big to small according to the value of each mass center, and counting the number of the data of each group;
(3) setting two thresholds K1 and K2, which respectively represent the minimum times of page updating in a hot group and the maximum times of page updating in a cold group; if the centroid in the hot group is smaller than K1, the number of the hot group smaller than K1 is calculated, and the number of the pages is divided into cache areas; if the mass center in the cold group is larger than K2, the number of the cold group larger than K2 is calculated, and the pages of the number are divided into data areas; if neither case occurs, entering step (4);
(4) setting the sizes of the hot group and the cold group to be a certain proportion, comparing the counted data numbers of the hot group and the cold group, if the data number of the hot group is more than the proportion, dividing the redundant page number of the hot group into the data area, and if the data number of the cold area is more than the proportion, dividing the redundant page number of the cold group into the cache area.
Preferably, the capacity ratio of the buffer area to the data area in step (1) is one to one.
Preferably, the cache region part in the step (1) stores the mapping table entry which is frequently updated in the part of the global mapping table in the flash memory, and the frequently updated data of the write request from the external file system.
Compared with the prior art, the invention has the advantages that: the invention divides the non-volatile memory PCM into two areas, a cache area and a data area, the cache area is used as the internal memory of the solid state disk, and the data area and the flash memory are addressed uniformly to store the data expelled from the cache area. And dynamically allocating the cache region and the data region to obtain the optimal proportion between the cache region and the data region, so that the hybrid solid-state disk can obtain the optimal performance under different loads.
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The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the invention and not to limit the invention.
FIG. 1 is a hybrid solid state disk weave architecture of the present invention
Fig. 2 is a flow chart of the present invention.
Detailed Description
The embodiments of the present invention will be described in detail with reference to the accompanying drawings and examples, so that how to implement the technical means for solving the technical problems and achieving the technical effects of the present invention can be fully understood and implemented.
A data partitioning method for a hybrid solid-state disk based on a nonvolatile memory comprises the following specific steps:
(1) in the initial stage, the PCM capacity is divided into a buffer area and a data area in a one-to-one ratio, a counter is set for each page of the PCM data area, the counter of the page written for the first time is given an initial value, and the counter is increased as long as the page in the data area is updated and decreased by one if the page is not updated.
(2) After a certain period, counting the value of a counter of each page in the data area, carrying out cluster analysis on the data by using a K-means algorithm, dividing the data into three types of data, and calculating the mass center of each type of data. And dividing the three groups of data into a hot group, a warm group and a cold group from large to small according to the value of each mass center, and counting the number of the data of each group.
(3) Two thresholds K1, K2 are set, indicating the minimum number of page updates in the hot group and the maximum number of page updates in the cold group, respectively. If the centroid in the hot group is smaller than K1, the number of the hot group smaller than K1 is calculated, and the number of the pages is divided into cache areas; if the centroid in the cold group is greater than K2, the number of cold groups greater than K2 is found and the number of pages is divided into data areas. If neither of these conditions occurs, step (4) is entered.
(4) Setting the sizes of the hot group and the cold group to be a certain proportion, comparing the counted data numbers of the hot group and the cold group, if the data number of the hot group is more than the proportion, dividing the redundant page number of the hot group into the data area, and if the data number of the cold area is more than the proportion, dividing the redundant page number of the cold group into the cache area.
In the invention, the cache region part stores the mapping table item which is frequently updated by the part of the global mapping table in the flash memory and the frequently updated data of the writing request from the external file system, so that the cache region is dynamically partitioned by utilizing the memory partitioning technology of predecessors in order to better obtain the reading and writing performance of the hybrid solid-state disk.
The method mainly comprises the steps of setting two key parameters Pb and Pm; updating two key parameters according to the read-write requests under different conditions; after a certain period, according to the change of the parameters Pb and Pm, using a group of calculation formulas to find the optimal size ratio of the data cache part and the part of the mapping relation; and adjusting the composition of the buffer area according to the composition of the current buffer area and the optimal size ratio of the data buffer part and the mapping relation part obtained before.
In the invention, when a read request reaches the solid-state disk, if the target data is in the cache region, the data in the cache can be directly read, otherwise, the data needs to be read in the PCM data region or the flash memory. When the target data is not in the cache region, the mapping address of the target data needs to be inquired first, and when the mapping address is in the PCM cache region, the address of the target data can be obtained immediately. When the mapping address is not in the PCM cache region, and if the mapping table entry portion of the PCM cache region is full, the least common mapping is evicted. If the mapping relationship is dirty, the translation page needs to be searched according to the global mapping directory and updated to make the mapping information consistent. And then further finding out the address of the data to be read according to the global mapping directory, and writing the address into the PCM cache region.
When a write request arrives, if the data of the write request exists in the data part of the cache region, the new data of the write request can be directly written to the data part of the cache region, otherwise, in order to make a position for the new data of the request, the least frequently used data of the data part of the cache region needs to be written back to the PCM data region. Then, firstly, the target address of the write-back data needs to be inquired in the mapping table entry part of the cache region, if the search is successful, whether the target address is in the data region of the PCM is judged, if so, the write-back data can be directly modified in place according to the characteristics of the PCM, the corresponding mapping relation is kept unchanged, and if the target address is in the flash memory, a space needs to be made for the write-back data in the PCM data region. Therefore, it is necessary to migrate the page with the least number of updates in the PCM data area to the flash memory, and modify the mapping relationship between the write-back page and the mapping relationship between the migrated pages. If the target address of the write-back data cannot be found in the cache region and a space needs to be made for the mapping relation of the write-back data, the least frequently used mapping relation is driven out, and if the mapping relation is dirty, the translation page needs to be searched according to the global mapping directory and updated to enable the mapping information of the translation page to be consistent. The translation page updates are all operated on in the flash memory, and the data written to the PCM data area is all evicted from the PCM cache area. Writing the write-back data back to the PCM data area, if the PCM data area is full, migrating the page with least update times in the PCM data area to the flash memory, and modifying the mapping relation of the migrated page.
The foregoing is merely illustrative of the preferred embodiments of the present invention and is not to be construed as limiting the claims. The present invention is not limited to the above embodiments, and the specific structure thereof is allowed to vary. All changes which come within the scope of the invention as defined by the independent claims are intended to be embraced therein.
Claims (2)
1. A dynamic partitioning method for a hybrid solid-state disk based on a nonvolatile memory is characterized by comprising the following steps: the method comprises the following steps of,
(1) the initial stage, dividing PCM into a buffer area and a data area, setting a counter for each page of the PCM data area, assigning an initial value to the counter of the page written for the first time, and adding one if the page in the data area is updated, and subtracting one if the page is not updated;
(2) after a certain period, counting the value of a counter of each page in the data area, performing cluster analysis on the data by using a K-means algorithm, dividing the data into three types of data, and calculating the mass center of each type of data; dividing the three groups of data into a hot group, a warm group and a cold group from big to small according to the value of each mass center, and counting the number of the data of each group;
(3) setting two thresholds K1 and K2, which respectively represent the minimum times of page updating in a hot group and the maximum times of page updating in a cold group; if the centroid in the hot group is smaller than K1, the number of the hot group smaller than K1 is calculated, and the number of the pages is divided into cache areas; if the mass center in the cold group is larger than K2, the number of the cold group larger than K2 is calculated, and the pages of the number are divided into data areas; if neither case occurs, entering step (4);
(4) setting the sizes of the hot group and the cold group to be a certain proportion, comparing the counted data numbers of the hot group and the cold group, if the data number of the hot group is more than the proportion, dividing the redundant page number of the hot group into a data area, and if the data number of the cold area is more than the proportion, dividing the redundant page number of the cold group into a cache area;
wherein, the cache region in the step (1) stores the mapping table entry frequently updated by the global mapping table in the flash memory, and the frequently updated data of the write request from the external file system.
2. A hybrid solid-state disk dynamic partitioning method based on non-volatile memory as claimed in claim 1 wherein: and (2) the capacity ratio of the buffer area to the data area in the step (1) is one to one.
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