CN111682848B - Terahertz frequency tripler based on CMOS (complementary metal oxide semiconductor) process - Google Patents
Terahertz frequency tripler based on CMOS (complementary metal oxide semiconductor) process Download PDFInfo
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- CN111682848B CN111682848B CN202010587732.0A CN202010587732A CN111682848B CN 111682848 B CN111682848 B CN 111682848B CN 202010587732 A CN202010587732 A CN 202010587732A CN 111682848 B CN111682848 B CN 111682848B
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- H03B19/06—Generation of oscillations by non-regenerative frequency multiplication or division of a signal from a separate source by means of discharge device or semiconductor device with more than two electrodes
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Abstract
The invention relates to the technical field of millimeter wave communication, in particular to a terahertz tripler based on a CMOS (complementary metal oxide semiconductor) process, which is used for solving the difficult problems of large processing and assembly errors of the traditional terahertz hybrid integrated tripler. The invention comprises the following steps: the device comprises a transistor NMOS1, a transistor NMOS2, a grid bias circuit, a drain bias circuit, two 3 rd harmonic idle circuits, two fundamental wave idle circuits, an input transmission line transformer and an output transmission line transformer; the whole frequency multiplier circuit adopts a balanced frequency multiplication structure, so that even harmonic output is effectively inhibited, and the purity of a frequency spectrum is improved; meanwhile, the 3 rd harmonic idle circuit at the input end and the fundamental wave idle circuit at the output end can effectively improve the frequency multiplication efficiency of the frequency multiplier; in addition, the invention adopts the semiconductor technology to form once, devices such as a diode, a triode and the like do not need to be assembled for the second time, the processing error of the frequency multiplier circuit is greatly reduced, and the production cost is greatly reduced.
Description
Technical Field
The invention belongs to the technical field of millimeter wave communication, and particularly relates to a terahertz frequency tripler based on a CMOS (complementary metal oxide semiconductor) process.
Background
Since maxwell proposed electromagnetic theory, applications of the electromagnetic spectrum have been expanding. In recent years, low-end frequency spectrum is increasingly crowded, so that people are promoted to continuously develop new frequency spectrum resources, and the terahertz technology is very focused on the national and international scientific circles under the background. Terahertz waves generally refer to electromagnetic waves with frequencies in the range of 100-10000 GHz, the frequency range of which is in the intersection area of photonics and electronics, and the terahertz waves have a plurality of unique properties, which presupposes that the terahertz waves have wide application prospects in various aspects; the method has great scientific and application values in the fields of safety inspection, object imaging, environment detection, satellite communication, radio astronomy, military radar and the like.
The development of terahertz technology must first solve the source problem; the conventional terahertz source generation method expands microwave (millimeter wave) technology to a high-frequency direction and mainly comprises a solid-state circuit technology and an electric vacuum technology. Compared with the electric vacuum technology, the solid-state circuit technology has the main advantages that: high-voltage devices are not needed, the reliability is good, the volume is small, the weight is light, the efficiency is high, the power consumption is low, the service life is long, and the like; thus, solid-state terahertz source technology has been developed in recent years. The terahertz source can be obtained by a solid-state circuit technology in two ways, namely, direct oscillation generation and microwave source frequency multiplication; compared with direct oscillation generation, the frequency multiplication source has good phase noise performance, so the technology is widely studied and adopted.
The existing terahertz frequency tripling technology mostly adopts a diode-based hybrid integration technology, such as a terahertz frequency band tripler disclosed in the patent document with the publication number of CN108111127A, a 2mm multilayer frequency tripler disclosed in the patent document with the publication number of CN103490594A, a frequency tripler method and the like; the main disadvantages are: 1) The mixed integrated circuit adopts a design scheme based on a P CB version, and in a terahertz frequency band, the circuit size is very small, and the poor processing precision of the PCB greatly influences the circuit performance; 2) In circuit assembly, devices such as a diode and the like need to be assembled on a PCB, and in a terahertz frequency band, the assembly error of the diode device can also greatly influence the circuit performance; 3) Because of the large difficulty in circuit processing and assembly and large manual debugging quantity, the cost of the mixed integration terahertz frequency multiplier circuit is very high.
Based on the above, the invention provides a terahertz frequency tripler based on a CMOS process.
Disclosure of Invention
The invention aims to solve the problems or the defects of the prior art and provides a terahertz tripler based on a CMOS process, which is realized on the CMOS process. The technical scheme adopted by the invention is as follows:
a terahertz tripler based on CMOS process, comprising: the device comprises a transistor NMOS1, a transistor NMOS2, a grid bias circuit, a drain bias circuit, two 3 rd harmonic idle circuits, two fundamental wave idle circuits, an input transmission line transformer and an output transmission line transformer; the device is characterized in that the grid electrodes of the transistors NMOS1 and NMOS2 are respectively connected with a 3 rd harmonic idle circuit, and the other ends of the two 3 rd harmonic idle circuits are respectively connected with two output ports of an input transmission line transformer; the sources of the transistors NMOS1 and NMOS2 are respectively connected with an inductor and then grounded; drains of the transistors NMOS1 and NMO S2 are respectively connected with a fundamental idle circuit, and the other ends of the two fundamental idle circuits are respectively connected with two output ports of the output transmission line transformer; the grid bias circuit is connected with the center tap of the input transmission line transformer, and the drain bias circuit is connected with the center tap of the output transmission line transformer; the input end of the input transmission line transformer is used as a fundamental wave signal input end, and the input end of the output transmission line transformer is used as a frequency tripling signal output end.
Further, the gate bias circuit is composed of a series resistor R1 and a parallel capacitor C1.
The drain bias circuit is implemented by a parallel capacitor C2.
The 3 rd harmonic idle circuits are all realized by adopting parallel 1/4 wavelength open circuits.
The fundamental idle circuits are all realized by adopting series resonance circuits consisting of an inductor L3 (L4) and a capacitor C3 (C4).
The input transmission line transformer and the output transmission line transformer are both realized by adopting broadside coupling structures.
The invention has the beneficial effects that: the terahertz frequency tripler based on the CMOS process has the following advantages compared with the prior art:
1) The whole frequency multiplier circuit adopts a balanced frequency multiplication structure, an input transmission line transformer changes an input signal into two paths of constant amplitude reverse signals to be input into two NMOS devices, an output transmission line transformer synthesizes two paths of constant amplitude reverse 3 rd harmonic signals generated by the NMOS devices into one path of output, and the 3 rd harmonic output power is improved by 1 time compared with that of a frequency multiplication circuit with only a single NMOS device; meanwhile, the balanced structure can effectively inhibit even harmonic output and improve the purity of a frequency spectrum;
2) The 3 rd harmonic idle circuit at the input end can inhibit 3 rd harmonic signals generated by the NMOS device from leaking from the input transmission line transformer, and the fundamental wave idle circuit at the output end can inhibit fundamental wave signals of the input frequency multiplier from leaking from the output transmission line transformer, so that the frequency multiplication efficiency of the frequency multiplier is effectively improved;
3) The ratio of the required 3-order harmonic signals in each order harmonic component can be increased by optimizing the inductance value of the inductance connected with the source electrode of the NMOS device, so that the frequency doubling efficiency is further improved;
4) The grid bias voltage and the drain bias voltage are respectively added from the center taps of the input and output transmission line transformers, and the grid bias voltage and the drain bias voltage can be provided for two transistors only by one grid bias circuit, so that the design of the bias circuit is greatly simplified;
5) The device such as a diode, a triode and the like is formed at one time by adopting a semiconductor process technology, secondary assembly is not needed, meanwhile, the processing error of a frequency multiplier circuit only depends on the semiconductor process precision, and the process precision is far better than the processing precision of a PCB (printed circuit board), so that the difficult problem of large processing and assembly errors of the traditional terahertz hybrid integrated tripler is solved, and the production cost is greatly reduced.
Drawings
FIG. 1 is a schematic diagram of a terahertz tripler circuit based on a CMOS process of the present invention;
FIG. 2 is a cross-sectional view of a silicon CMOS process of the present invention;
FIG. 3 is a three-dimensional view of an input transmission line transformer of the present invention;
FIG. 4 is a three-dimensional view of an output transmission line transformer according to the present invention;
FIG. 5 is a schematic diagram of the saturated output power of a terahertz frequency tripler according to an embodiment of the present invention;
fig. 6 shows the input and output port reflection coefficients of a terahertz tripler in accordance with an embodiment of the present invention.
Detailed Description
In order to illustrate the technical scheme of the invention, the detailed description is provided below with reference to the accompanying drawings.
The embodiment provides a terahertz frequency tripler based on a CMOS process, a circuit schematic diagram of which is shown in fig. 1, which specifically comprises: NMOS1, NMOS2, a grid bias circuit, a drain bias circuit, two 3 rd harmonic idle circuits, two fundamental idle circuits, an input transmission line transformer and an output transmission line transformer; wherein, the liquid crystal display device comprises a liquid crystal display device,
the grid electrodes of the NMOS1 and the NMOS2 are respectively connected with one end of a 3 rd harmonic idle circuit, and the other ends of the two 3 rd harmonic idle circuits are respectively connected with two output ports of the input transmission line transformer;
the sources of the NMOS1 and the NMOS2 are respectively connected with one ends of the inductors L1 and L2, and the other ends of the inductors L1 and L2 are grounded;
the drains of the NMOS1 and the NMOS2 are respectively connected with one end of a fundamental idle circuit, and the other ends of the two fundamental idle circuits are respectively connected with two output ports of an output transmission line transformer;
the grid bias circuit of the NMOS device is connected with the center tap of the input transmission line transformer, and the drain bias circuit of the NMOS device is connected with the center tap of the output transmission line transformer;
the grid bias circuit consists of a series resistor R1 and a parallel capacitor C1, and the drain bias circuit is realized by a parallel capacitor C2; the 3 rd harmonic idle circuit is realized by adopting parallel 1/4 wavelength opening lines TL1 and TL 2; the fundamental idle circuit is realized by adopting a series resonant circuit consisting of an inductor L3 (L4) and a capacitor C3 (C4);
the input end of the input transmission line transformer inputs fundamental wave signals, and the input end of the output transmission line transformer outputs 3 times frequency signals.
The present embodiment is designed on a silicon CMOS process with a multi-layer structure, as shown in fig. 2, which is a cross-sectional view of the process; the bottom is a silicon substrate with the thickness of 254um, nine metal layers M1-M9 are arranged on the silicon substrate, and through holes Via1-Via8 are connected with the metal layers; in addition, the CBM layer and the CTM layer are upper and lower electrode layers of the capacitor and are respectively connected to the M8 layer through via hole CBM and via hole CT M; more specifically:
firstly, the size of an NMOS device needs to be selected, and the output power of a frequency multiplier is insufficient due to the too small gate width; the excessive gate width can cause large parasitic parameters of the device and can affect the frequency multiplication efficiency and the output power of the frequency multiplier. In this embodiment, load traction simulation is performed on transistors with multiple sizes, and the size of the final selected transistor is 1×10um; in addition, the grid and drain voltages of the frequency multiplier and the source grounding inductance are also optimally designed to ensure that the optimal frequency tripled output power is obtained, the final selected grid voltage is 0.15V, the drain voltage is 1V, and the source inductance is 25pH;
the grid bias circuit consists of a series resistor R1 and a parallel capacitor C1, wherein the resistance value of the resistor is 1.2k ohms, and the capacitance value of the capacitor is 1PF; the drain bias circuit is realized by a parallel capacitor C2, and the capacitance value is 1PF; the design of the bias circuit mainly ensures the stability of the whole circuit and prevents low-frequency clutter signals from entering the frequency doubling circuit;
the 3 rd harmonic idle circuit is realized by adopting parallel open circuit transmission lines TL1 and TL2, the length of the 3 rd harmonic idle circuit is 1/4 of the wavelength corresponding to the 3 rd harmonic frequency, the 3 rd harmonic can be effectively inhibited from leaking to the output end, and in order to minimize the loss of the transmission line, all the transmission lines are realized by adopting M9 layers of metal, and the thickness of the metal layer is thickest and far away from the silicon substrate; the fundamental wave idle circuit is realized by adopting a series resonant circuit of an inductor L3 (L4) and a capacitor C3 (C4), the resonant frequency is selected at the fundamental wave working frequency, the leakage of fundamental wave signals from an output port can be effectively inhibited, the inductor is realized by adopting a transmission line winding mode, and the capacitor is realized by adopting the coupling between two polar plates of a CBM and a CTM; through the design of the 3 rd harmonic and fundamental wave idle circuit, the frequency multiplication efficiency of the terahertz tripler is further improved;
the input and output transmission line transformers are realized by adopting a broadside coupling structure, and the broadside coupling transmission line transformers are designed by the two uppermost layers of metals in the process for minimizing the insertion loss of the transmission line transformers; the three-dimensional structures of the input and output transmission line transformers are respectively shown in fig. 3 and 4, an octagonal structure is adopted, and a grid electrode and a drain electrode bias circuit are respectively connected from the center taps of the input and output transmission line transformers; electromagnetic field simulation of the transmission line transformer shows that the input transmission line transformer realizes that the amplitude unbalance is less than 0.5dB and the phase unbalance is less than 4 degrees in the frequency range of 87-97 GHz; the output transmission line transformer realizes that the amplitude unbalance is less than 0.8dB and the phase unbalance is less than 6 degrees in the frequency range of 260-290 GHz.
Finally, combining all the part unit circuits designed in the above way to perform overall electromagnetic simulation so as to ensure the precision of circuit design under the terahertz frequency band, wherein the final simulation result is shown in fig. 5 and 6; the saturated output power of the tripler is larger than-0.4 dBm in the working frequency band of 260-290 GHz, the frequency doubling loss is smaller than 20dB, and the fundamental wave suppression degree is larger than 30dB.
While the invention has been described in terms of specific embodiments, any feature disclosed in this specification may be replaced by alternative features serving the equivalent or similar purpose, unless expressly stated otherwise; all of the features disclosed, or all of the steps in a method or process, except for mutually exclusive features and/or steps, may be combined in any manner.
Claims (4)
1. A terahertz tripler based on CMOS process, comprising: the device comprises a transistor NMOS1, a transistor NMOS2, a grid bias circuit, a drain bias circuit, two 3 rd harmonic idle circuits, two fundamental wave idle circuits, an input transmission line transformer and an output transmission line transformer; the device is characterized in that the grid electrodes of the transistors NMOS1 and NMOS2 are respectively connected with a 3 rd harmonic idle circuit, and the other ends of the two 3 rd harmonic idle circuits are respectively connected with two output ports of an input transmission line transformer; the sources of the transistors NMOS1 and NMOS2 are respectively connected with an inductor and then grounded; drains of the transistors NMOS1 and NMOS2 are respectively connected with a fundamental idle circuit, and the other ends of the two fundamental idle circuits are respectively connected with two output ports of the output transmission line transformer; the grid bias circuit is connected with the center tap of the input transmission line transformer, and the drain bias circuit is connected with the center tap of the output transmission line transformer; the input end of the input transmission line transformer is used as a fundamental wave signal input end, and the input end of the output transmission line transformer is used as a frequency tripling signal output end; the 3-order harmonic idle circuits are all realized by adopting parallel 1/4 wavelength open circuits, and the fundamental wave idle circuits are all realized by adopting series resonance circuits consisting of inductors and capacitors.
2. The terahertz tripler based on the CMOS process according to claim 1, wherein the gate bias circuit is composed of a series resistor R1 and a parallel capacitor C1.
3. The CMOS process-based terahertz tripler as recited in claim 1, wherein said drain bias circuit is implemented by a shunt capacitor C2.
4. The CMOS process-based terahertz tripler of claim 1, wherein the input transmission line transformer and the output transmission line transformer are both implemented using broadside coupling structures.
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| CN114157241B (en) * | 2021-12-10 | 2023-03-10 | 杭州电子科技大学 | Millimeter wave reconfigurable frequency multiplier circuit and control method thereof |
| CN115088187A (en) * | 2021-12-20 | 2022-09-20 | 香港中文大学（深圳） | Push-push frequency doubler based on complementary transistor |
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