CN111682070A - Device for restraining negative temperature characteristic of controllable sampling field effect transistor - Google Patents
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- H01L29/772—Field effect transistors
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Abstract
The invention provides a device for restraining negative temperature characteristic of a controllable sampling field effect transistor, which comprises: the device comprises a P-type substrate, an N-type drift region, a P-type heavily doped first region, an N-type semiconductor drain region, a P-type Double reduced surface electric field (Double RESURF) region, a P-type body region, a P-type heavily doped second region, an N-type heavily doped region, a P-type well region, an N-type lightly doped resistance region, first polysilicon, second polysilicon, an oxide layer, drain metal, gate metal, lead metal, a current sensing electrode and substrate metal; on the basis of the traditional high-voltage C-SenseFET, a trap resistor is formed by diffusion between the source end of the power device and the Sense electrode and is connected with the source electrode through a metal wire, so that the design of a new structure of the high-voltage C-SenseFET is realized, the negative temperature characteristic is effectively inhibited, the temperature drift coefficient is reduced, and the temperature characteristic of the C-SenseFET device is improved.
Description
Technical Field
The invention belongs to the technical field of power semiconductor devices, and relates to a novel structure for restraining negative temperature characteristics of a controllable sampling field effect transistor (C-SenseFET).
Background
With the development of Smart Power Integrated Circuits (SPICs), SPICs, which integrate high-voltage devices, CMOS devices, and bipolar devices, are now widely used in various instruments and communication devices. An SPIC generally includes three parts: power control, detection protection, I/O interface, where the power control part is the core of the SPIC design. In order to reduce the power consumption of the high voltage power integrated circuit and ensure the reliability of the whole integrated circuit, accurate signal sampling and control of the high voltage power integrated circuit and the application system thereof need to be realized. At present, sampling aiming at the SPIC can be divided into voltage sampling, current sampling and temperature sampling, because the voltage sampling is difficult to directly carry out, the technology (such as the temperature sampling by utilizing a polysilicon diode) required by directly carrying out the temperature sampling has high requirements on the process, certain limitation is realized in the aspect of sampling, the sampling response of a current mode is fast, the anti-interference capability is strong, the process compatibility is good, and therefore the current sampling is widely applied.
A sampling Field Effect transistor (sense Field Effect transistor) is a current sampling power device that can be applied to a power conversion integrated circuit. The traditional sampling field effect transistor sampling structure comprises a JFET sampling structure, a current mirror sampling structure and the like, is simple in structure and high in sampling precision, and can only realize uncontrollable current detection under lower voltage. With the continuous expansion of power integrated circuits to higher voltage class application fields, the conventional sampling fet devices have failed to meet the requirement of accurate detection of current at high voltage, and therefore, in order to realize controllable current detection at high voltage, a new controllable sampling fet is proposed on the basis of the conventional structure, as shown in fig. 3.
The controllable sampling Field effect transistor C-SenseFET (controlled sampled Field effect transistor) can accurately sample the current of a high-voltage power element in the SPIC when the SPIC works in a linear region, and the sampling current can be adjusted according to different conditions and requirements; when the chip works in a saturation region, the external bypass capacitor can be charged with constant current, so that the self-power supply of the chip is realized. However, since the C-SenseFET has a negative temperature characteristic, when sampling is performed in a linear region, a current decrease due to a temperature increase may cause an unstable sampling signal to be output from the device, and when the device is operated in a saturation region, a charging current may decrease and a current output may be unstable due to an excessively long operation time and a difficulty in heat dissipation. Therefore, when the temperature changes, the phenomenon of mismatching between the sampling current and the current of the power device may occur in the C-sense fet, so that the control circuit is triggered by mistake or not triggered, and the power IC system is disturbed and uncontrollable.
Therefore, in order to improve the operating characteristics of the high-voltage C-SenseFET at different temperatures and realize better current sampling, a new structure of the C-SenseFET capable of suppressing the negative temperature effect is provided as shown in FIG. 1, and the circuit diagram is shown in FIG. 2. The main advantage of the structure is that the negative temperature characteristic of the C-SenseFET can be restrained to a certain extent by utilizing the positive temperature characteristic of the trap resistance current after the high-voltage C-SenseFET is connected in series.
Disclosure of Invention
In order to inhibit the negative temperature characteristic of the high-voltage controllable sampling field effect transistor, the invention realizes a new structure capable of inhibiting the negative temperature effect of the C-SenseFET by connecting a resistor in series behind the traditional high-voltage C-SenseFET.
In order to achieve the purpose, the technical scheme of the invention is as follows:
a device for restraining negative temperature characteristics of a controllable sampling field effect transistor C-SenseFET comprises a P-type substrate 1 positioned at the bottommost part of the device, a P-type heavily doped first region 3 positioned on the upper surface of the right side of the P-type substrate 1 and an N-type drift region 2 positioned on the left side of the P-type doped region 3; an N-type semiconductor drain region 4, a P-type Double reduced surface electric field (Double RESURF) region 5, a P-type body region 6, an N-type heavily doped region 8 and a P-type well region 9 are sequentially arranged on the upper surface in the N-type drift region 2 from left to right; a P-type heavily doped second region 7 is arranged below the inner surface of the P-type body region 6; an N-type lightly doped resistance region 10 is arranged below the inner surface of the P-type well region 9; an oxide layer 13 is arranged on the upper surface of the P-type Double reduced surface field (Double RESURF) region 5; the oxide layer 13 is provided with a field plate structure formed by the first polysilicon 11 and the second polysilicon 12; the upper surface of the N-type semiconductor drain region 4 is connected with the first polysilicon 11 through drain metal 14; the upper surface of the P-type heavily doped second region 7 is connected with the second polysilicon 12 through gate metal 15; the upper surface of the N-type heavily doped region 8 is connected with the upper surface of the N-type lightly doped resistance region 10 through a wire metal 16; the upper surface of the N-type lightly doped resistance region 10 is provided with a current sensing electrode 17 positioned on the right side of the lead metal 16, and the current sensing electrode 17 is connected with the right end of the N-type lightly doped resistance region 10; the upper surface of the P-type heavily doped region 3 has a substrate metal 18 located on the right side of the current sensing electrode 17.
Preferably, the oxide layer 13 located above the P-type Double reduced surface field (Double RESURF) region 5 is a field oxide layer implemented by a local oxidation process, and the oxide layer 13 located above the P-type substrate 1, the N-type drift region 2 and the field oxide layer implemented by the local oxidation process is a barrier oxide layer implemented by a borophosphosilicate glass process.
Preferably, the N-type or P-type semiconductor is single crystal silicon, silicon carbide, or gallium nitride.
In the invention, a field plate structure formed by first polysilicon 11 and second polysilicon 12 and a P-type Double reduced surface electric field (Double RESURF) region 5 on the lower surface of an oxide layer 13 are used for improving the withstand voltage of the C-SenseFET device;
the P-type well region 9 and the well resistor formed by the N-type lightly doped resistor region 10 below the surface of the P-type well region can be used as an isolation ring for isolating devices, so that the cost can be effectively reduced on the basis of improving the sampling performance and stability of the devices, and the effectiveness of the devices is greatly improved.
The high-voltage controllable sampling field effect transistor C-SenseFET has good process compatibility with a power device, can effectively optimize and integrate the layout design steps of the sampling device and the power device and the occupied area of a chip, and improves the design efficiency.
In conclusion, the beneficial effects of the invention are as follows: according to the invention, the trap resistor is connected in series behind the traditional high-voltage C-SenseFET, and when the current is reduced, the voltage difference between two ends of a grid source is reduced through resistor voltage division, so that the current is increased, and the current negative feedback of a certain degree can be provided when the temperature is reduced; meanwhile, when the doping concentration of the well resistor is higher, the temperature rise causes the reduction of the resistor and the increase of the current, so that the negative temperature characteristic of the output current of the C-SenseFET is inhibited to a certain extent.
Drawings
FIG. 1 is a schematic diagram of a lateral cross-sectional structure of a device for suppressing negative temperature characteristics of a controllable sampling FET according to the present invention.
Fig. 2 is a simplified current diagram of a high voltage C-SenseFET device of the present invention that suppresses negative temperature characteristics.
Fig. 3 is a schematic diagram of a lateral cross-sectional structure of a conventional high-voltage controllable sampling fet C-SenseFET.
FIG. 4 is a simulation diagram of saturation region characteristics of a conventional high-voltage controllable sampling FET C-SenseFET structure at different temperatures.
FIG. 5 is a simulation diagram of the saturation region characteristics of two well-doped controllable sampling FET C-SenseFET structures according to the present invention.
The device comprises a substrate 1, a drift region 2, a heavily doped P-type region 3, a heavily doped N-type semiconductor drain region 4, a dual reduced surface field (Double RESURF) P-type region 5, a body P-type region 6, a heavily doped P-type region 7, a heavily doped N-type region 8, a well P-type region 9, a lightly doped N-type resistor region 10, a first polysilicon 11, a second polysilicon 12, an oxide layer 13, a drain metal 14, a gate metal 15, a lead metal 16, a current sensing electrode 17, and a substrate metal 18.
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
A device for restraining negative temperature characteristic of a controllable sampling field effect transistor C-SenseFET comprises a P-type substrate 1 positioned at the bottommost part of the device, a P-type heavily doped first region 3 positioned on the upper surface of the right side of the P-type substrate 1 and an N-type drift region 2 positioned on the left side of the P-type doped region 3; an N-type semiconductor drain region 4, a P-type Double reduced surface electric field (Double RESURF) region 5, a P-type body region 6, an N-type heavily doped region 8 and a P-type well region 9 are sequentially arranged on the upper surface in the N-type drift region 2 from left to right; a P-type heavily doped second region 7 is arranged below the inner surface of the P-type body region 6; an N-type lightly doped resistance region 10 is arranged below the inner surface of the P-type well region 9; the upper surface of the P-type Double RESURF region 5 is provided with an oxide layer 13; the oxide layer 13 is provided with a field plate structure formed by the first polysilicon 11 and the second polysilicon 12; the upper surface of the N-type semiconductor drain region 4 is connected with the first polysilicon 11 through drain metal 14; the upper surface of the P-type heavily doped second region 7 is connected with the second polysilicon 12 through gate metal 15; the upper surface of the N-type heavily doped region 8 is connected with the upper surface of the N-type lightly doped resistance region 10 through a wire metal 16; the upper surface of the N-type lightly doped resistance region 10 is provided with a current sensing electrode 17 positioned on the right side of the lead metal 16, and the current sensing electrode 17 is connected with the right end of the N-type lightly doped resistance region 10; the upper surface of the P-type heavily doped region 3 has a substrate metal 18 located on the right side of the current sensing electrode 17.
The oxide layer 13 located above the P-type Double reduced surface electric field (Double RESURF) region 5 is a field oxide layer implemented by using a local oxidation process, and the oxide layer 13 located above the P-type substrate 1, the N-type drift region 2 and the field oxide layer implemented by using the local oxidation process is a barrier oxide layer implemented by using a borophosphosilicate glass process.
The N-type or P-type semiconductor is monocrystalline silicon, silicon carbide or gallium nitride.
In the invention, a field plate structure formed by first polysilicon and second polysilicon and a P-type Double reduced surface electric field (Double RESURF) region on the lower surface of an oxide layer are used for improving the withstand voltage of a C-SenseFET device; the P-type well region and the well resistor formed by the N-type lightly doped resistor region below the surface of the P-type well region can be used as an isolation ring for isolating devices, so that the cost can be effectively reduced on the basis of improving the sampling performance and stability of the devices, and the effectiveness of the devices is greatly improved; the high-voltage C-SenseFET has good process compatibility with a power device, can effectively optimize and integrate the layout design steps of a sampling device and the power device and the occupied area of a chip, and improves the design efficiency.
The principle of the invention is as follows: based on the traditional high-voltage C-SenseFET structure, a trap resistor is formed by diffusion between the source end of a power device and a Sense electrode of the power device, and the trap resistor is connected with the source end through a metal wire. When the device is in a conducting state, current enters from the drain electrode of the device, passes through the N-type drift region, passes through the JFET region below the P-type body region and finally flows out of the current sensing electrode. The device can realize the sampling of current in a linear region, and the magnitude of the sampling current can be controlled by a grid electrode above a P type body region. The device can perform constant current charging on an external bypass capacitor in a saturation region so as to realize self power supply of the chip. When the device works in a linear region, when the current is reduced, the partial voltage of the well resistor is reduced, and the absolute value of the feedback gate voltage provided by the device is reduced, so that the channel depletion region is narrowed, the channel is widened, the channel resistance is reduced, the current is improved, and the current negative feedback when the temperature is reduced is provided; meanwhile, when the doping concentration of the trap resistor is higher, the carrier mobility is also enabled to be in a positive temperature coefficient, when the temperature rises, the trap resistor is reduced, the current rises, and the negative temperature characteristic of the C-SenseFET is also inhibited to a certain extent.
In order to verify the beneficial effects of the present invention, the conventional C-sense fet structure shown in fig. 3 and the new C-sense fet structure shown in fig. 1 were simulated separately using the piece of medical software. The main parameters for the simulation of the conventional C-SenseFET structure are as follows: the resistivity of the P-type substrate is 80 Ω · cm; the implantation dose range of the N drift region is 3.5e12-4.5e12cm-2The junction depth is 7.9 μm; the implantation dosage range of the P-type Double reduced surface field (Double RESURF) region is 1e12-6.0e13cm-2The junction depth is 0.8 μm; the implantation dosage range of the P-type body region is 1e13-1e14cm-2The junction depth was 5.2 μm. The new structure of the C-SenseFET is only added with a P-type well region and an N-type lightly doped resistance region on the basis of the traditional C-SenseFET structure, wherein the P-type well region is implanted for multiple times, and the implantation dosage range is 5e13-1e14cm-2(ii) a The N-type lightly doped resistor region is subjected to high doping and low doping contrast injectionThe implantation dosage range is 1e13-3e15cm-2。
Defining the drift coefficient M of the current with temperature:
wherein, IHIs C-SenseFET saturation region current at high temperature, ILThe current in the saturation region of the C-SenseFET at low temperature.
As can be seen from the simulation diagram of the saturation region characteristics of the conventional high-voltage C-sense fet structure shown in fig. 4 at different temperatures, when the junction temperature rises due to too long operating time or difficult heat dissipation, the charging current decreases, and the difference between the saturation region currents at high temperature and low temperature is large, that is, the drift coefficient of the current with temperature is large. In the simulation diagram of the characteristics of the saturated region of the new structure of the C-SenseFET under the two kinds of well doping in fig. 5, it can be seen that the electrical parameters are obviously optimized, and the current difference of the saturated region of the new structure of the C-SenseFET under high temperature and low temperature is small.
The saturation region currents of the two devices in fig. 4 and 5 at two different temperatures of 300K and 400K are read to calculate the temperature drift coefficients of the two devices, wherein the temperature drift coefficient of the conventional high-voltage C-Sense FET structure is 27.4%, the temperature drift coefficient of the new C-Sense FET structure with high doped well resistance is 17.3%, and the temperature drift coefficient of the new C-Sense FET structure with low doped well resistance is 9.5%. Simulation data show that the new structure of the C-SenseFET greatly reduces the temperature drift coefficient of the device so as to obtain better temperature characteristics, and meanwhile, when the well resistor is low-doped in the new structure of the C-SenseFET, the suppression effect on temperature drift current is the best.
In summary, on the basis of the traditional high-voltage C-SenseFET structure, a well resistor is formed by diffusion between the source end of the power device and the Sense electrode, so that the formed C-SenseFET new structure can effectively inhibit the negative temperature effect of the device, reduce the temperature drift coefficient of the device and improve the temperature characteristic of the device.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.
Claims (3)
1. A device for suppressing negative temperature characteristics of a controllable sampling field effect transistor is characterized in that: the device comprises a P-type substrate (1) positioned at the bottommost part of the device, a P-type heavily doped first region (3) positioned on the upper surface of the right side of the P-type substrate (1), and an N-type drift region (2) positioned on the left side of the P-type doped region (3); an N-type semiconductor drain region (4), a P-type Double reduced surface electric field (Double RESURF) region (5), a P-type body region (6), an N-type heavily doped region (8) and a P-type well region (9) are sequentially arranged on the upper surface in the N-type drift region (2) from left to right; a P-type heavily doped second region (7) is arranged below the inner surface of the P-type body region (6); an N-type lightly doped resistance region (10) is arranged below the inner surface of the P-type well region (9); the upper surface of the P-type Double RESURF region (5) is provided with an oxidation layer (13); the oxide layer (13) is provided with a field plate structure consisting of first polysilicon (11) and second polysilicon (12); the upper surface of the N-type semiconductor drain region (4) is connected with the first polycrystalline silicon (11) through drain metal (14); the upper surface of the P-type heavily doped second region (7) is connected with the second polysilicon (12) through gate metal (15); the upper surface of the N-type heavily doped region (8) is connected with the upper surface of the N-type lightly doped resistance region (10) through a wire metal (16); the upper surface of the N-type lightly doped resistance region (10) is provided with a current sensing electrode (17) positioned on the right side of the lead metal (16), and the current sensing electrode (17) is connected with the right end of the N-type lightly doped resistance region (10); the upper surface of the P-type heavily doped region (3) is provided with a substrate metal (18) positioned on the right side of the current sensing electrode (17).
2. The device for suppressing negative temperature characteristics of a controllably sampled fet as recited in claim 1, wherein: the oxide layer (13) positioned above the P-type Double reduced surface electric field (Double RESURF) area (5) is a field oxide layer realized by using a local oxidation process, and the oxide layer (13) positioned above the P-type substrate (1), the N-type drift area (2) and the field oxide layer realized by using the local oxidation process is a barrier oxide layer realized by using a borophosphosilicate glass process.
3. The device for suppressing negative temperature characteristics of a controllably sampled fet as recited in claim 1, wherein: the N-type or P-type semiconductor is monocrystalline silicon, silicon carbide or gallium nitride.
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|---|---|---|---|---|
| CN101980362A (en) * | 2010-08-31 | 2011-02-23 | 电子科技大学 | Controllable self-clamping SensorFET composite vertical power device |
| CN102832219A (en) * | 2012-08-31 | 2012-12-19 | 电子科技大学 | Self-feedback linear galvanostat integrating adjustable thermistor |
| US20160211256A1 (en) * | 2015-01-16 | 2016-07-21 | Seiko Instruments Inc. | Semiconductor device |
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- 2020-07-30 CN CN202010748363.9A patent/CN111682070A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101980362A (en) * | 2010-08-31 | 2011-02-23 | 电子科技大学 | Controllable self-clamping SensorFET composite vertical power device |
| CN102832219A (en) * | 2012-08-31 | 2012-12-19 | 电子科技大学 | Self-feedback linear galvanostat integrating adjustable thermistor |
| US20160211256A1 (en) * | 2015-01-16 | 2016-07-21 | Seiko Instruments Inc. | Semiconductor device |
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| Title |
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| 李泽宏等: "智能型高压SENSEFET器件的设计分析和实现", 《半导体学报》 * |
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Application publication date: 20200918 |