CN111681590A

CN111681590A - Display driving circuit

Info

Publication number: CN111681590A
Application number: CN202010591147.8A
Authority: CN
Inventors: 曹海明; 田超
Original assignee: Wuhan China Star Optoelectronics Technology Co Ltd
Current assignee: Wuhan China Star Optoelectronics Technology Co Ltd
Priority date: 2020-06-24
Filing date: 2020-06-24
Publication date: 2020-09-18
Anticipated expiration: 2040-06-24
Also published as: CN111681590B

Abstract

The application provides a show drive circuit, show drive circuit includes multistage drive unit, every level the drive unit includes the pull-up unit, pull-up unit electric connection second high-voltage signal input end makes the high-voltage signal of second high-voltage signal input end input directly transmits to cascaded signal output end through the pull-up unit, and then makes show drive circuit output high voltage's drive signal, make simultaneously show the inside thin film transistor's of drive circuit grid keeps lower voltage, has avoided the increase of thin film transistor internal stress, makes show drive circuit's driving force and drive stability and obtain showing the promotion.

Description

Display driving circuit

Technical Field

The application relates to the technical field of display, in particular to a display driving circuit.

Background

The goa (gate Driver on array) technology, that is, the array substrate line driving technology, directly manufactures the scan driving circuit on the array substrate, thereby saving the space for separately arranging the scan driving circuit through the integrated chip, being beneficial to realizing the narrow frame design of the display, and reducing the welding process of the integrated chip. Therefore, the application of the GOA technology in the display panel field is becoming more and more widespread.

The Low temperature poly-crystalline oxide (LTPO) technology is a novel semiconductor technology combining a Low temperature poly-silicon (LTPS) technology and an Indium Gallium Zinc Oxide (IGZO) technology, and when applied to a GOA circuit, the Low temperature poly-crystalline oxide (LTPO) technology can enable a display panel to have the characteristics of strong driving capability and Low power consumption. However, the LTPO technology also has a problem of low mobility of the IGZO technology, and when the GOA driving circuit using the LTPO technology performs high frequency display, the requirement of supplying a high level voltage to the display region in a short time cannot be met, which results in the display quality of the display panel being reduced. The prior art has two methods for improving the problem of low mobility of LTPO technology: one is to increase the aspect ratio of LTPO, but this method will result in increased space occupation of the tft and reduced display panel aperture ratio; another method is to increase the gate-source voltage difference of the thin film transistors, but this method may cause stress increase of all thin film transistors in the display panel, affect the overall stability of the GOA circuit, and may cause power consumption increase of the display panel.

Disclosure of Invention

Based on the not enough among the above-mentioned prior art, this application provides a display drive circuit set up second high voltage signal input in the every grade drive unit of display drive circuit, the high voltage signal of second high voltage signal input transmits to cascading signal output part through the pull-up unit, thereby makes display drive circuit outputs the drive signal of high voltage.

The application provides a display drive circuit, includes multistage drive unit, every level the drive unit includes:

the pull-up control unit is electrically connected with a first control signal input end, a first cascade signal input end, a first clock signal input end, a first high-voltage signal input end and a first node, and is used for transmitting a signal input by the first clock signal input end to the first node under the control of signals input by the first control signal input end, the first cascade signal input end and the first high-voltage signal input end;

the pull-up unit is electrically connected with a second high-voltage signal input end, the first node and the cascade signal output end and is used for transmitting a signal input by the second high-voltage signal input end to the cascade signal output end under the signal control of the first node;

the feedback unit is electrically connected with the first node and the cascade signal output end and is used for feeding back a signal output by the cascade signal output end to the first node;

the voltage input by the second high-voltage signal input end is greater than the voltage input by the first high-voltage signal input end.

According to an embodiment of the present application, the pull-up control unit includes a first transistor, a second transistor, a third transistor, and a first capacitor, a gate, a source, and a drain of the first transistor are electrically connected to the first cascade signal input terminal, the first control signal input terminal, and the second node, a gate and a source of the second transistor are electrically connected to the second node and the first clock signal input terminal, a gate and a drain of the third transistor are electrically connected to the first high voltage signal input terminal and the first node, a drain of the second transistor is electrically connected to a source of the third transistor, and two ends of the first capacitor are electrically connected to the drain of the second transistor and the second node, respectively.

According to an embodiment of the present application, the pull-up unit includes a fourth transistor, and a gate, a source, and a drain of the fourth transistor are electrically connected to the first node, the second high-voltage signal input terminal, and the cascade signal output terminal, respectively.

According to an embodiment of the present application, the feedback unit includes a second capacitor, and two ends of the second capacitor are electrically connected to the first node and the cascade signal output terminal, respectively.

According to an embodiment of the present application, each stage of the driving unit further includes:

the pull-down control unit is electrically connected with the first control signal input end, the second clock signal input end, the third clock signal input end, the second control signal input end, the first high-voltage signal input end, the low-voltage signal input end, the second cascade signal input end and a third node, and is used for transmitting signals input by the first high-voltage signal input end and/or the low-voltage signal input end to the third node under the common control of signals input by the first control signal input end, the second clock signal input end, the third clock signal input end, the second control signal input end and the second cascade signal input end;

a jump control unit electrically connected to the third node, the low voltage signal input terminal, the first jump signal input terminal, the second jump signal input terminal, and the cascade signal output terminal, and configured to transmit a signal input from the low voltage signal input terminal to the third node and/or the cascade signal output terminal under control of signals input from the first jump signal input terminal and the second jump signal input terminal;

and the pull-down unit is electrically connected with the third node, the low-voltage signal input end and the cascade signal output end and is used for transmitting the signal input by the low-voltage signal input end to the cascade signal output end under the control of the signal of the third node.

According to an embodiment of the present application, the pull-down control unit includes a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, and a third capacitor, wherein a gate and a source of the fifth transistor are electrically connected to the first control signal input terminal and the second clock signal input terminal, respectively, a drain of the fifth transistor is electrically connected to a drain of the sixth transistor and a gate of the seventh transistor, a gate and a source of the sixth transistor are electrically connected to the second control signal input terminal and the third clock signal input terminal, respectively, a source and a drain of the seventh transistor are electrically connected to the first high voltage signal input terminal and the third node, respectively, a gate and a source of the eighth transistor are electrically connected to the second cascade signal input terminal and the second control signal input terminal, respectively, the drain of the eighth transistor is electrically connected to the gate of the ninth transistor, the source and the drain of the ninth transistor are electrically connected to the low-voltage signal input terminal and the third node, respectively, the gate and the source of the tenth transistor are electrically connected to the third node and the low-voltage signal input terminal, respectively, and two ends of the third capacitor are electrically connected to the low-voltage signal input terminal and the third node, respectively.

According to an embodiment of the present application, the transition control unit includes an eleventh transistor, a twelfth transistor, and a thirteenth transistor, a gate and a source of the eleventh transistor and a gate of the twelfth transistor are electrically connected to the first transition signal input terminal, a drain of the eleventh transistor is electrically connected to the cascade signal output terminal, a source and a drain of the twelfth transistor are electrically connected to the low voltage signal input terminal and the third node, respectively, and a gate, a source, and a drain of the thirteenth transistor are electrically connected to the second transition signal input terminal, the low voltage signal input terminal, and the cascade signal output terminal, respectively.

According to an embodiment of the present application, the pull-down unit includes a fourteenth transistor, and a gate, a source, and a drain of the fourteenth transistor are electrically connected to the third node, the low-voltage signal input terminal, and the cascade signal output terminal, respectively.

According to an embodiment of the present application, the first cascade signal input terminal of the nth stage of the driving unit is electrically connected to the cascade signal output terminal of the (n-1) th stage of the driving unit, and the second cascade signal input terminal of the nth stage of the driving unit is electrically connected to the cascade signal output terminal of the (n +1) th stage of the driving unit; wherein n is an integer greater than 1.

According to an embodiment of the present application, the first cascade signal input terminal of the nth stage of the driving unit is electrically connected to the cascade signal output terminal of the (n-2) th stage of the driving unit, and the second cascade signal input terminal of the nth stage of the driving unit is electrically connected to the cascade signal output terminal of the (n +2) th stage of the driving unit; wherein n is an integer greater than 2.

The beneficial effect of this application is: the utility model provides a show drive circuit includes multistage drive unit, through at each level set up second high-voltage signal input end alone in the drive unit, make the high voltage signal of second high-voltage signal input end input directly transmits to cascaded signal output end through pull-up unit, and then makes show drive circuit output high voltage's drive signal, compare in prior art, need not to increase the size or the grid source voltage difference of showing the inside thin film transistor of drive circuit, avoided the reduction of display panel aperture ratio and the increase of thin film transistor internal stress, make show drive circuit's driving capability and drive stability and obtain showing and promote.

Drawings

In order to illustrate the embodiments or the technical solutions in the prior art more clearly, the drawings needed to be used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the application, and it is obvious for those skilled in the art that other drawings can be obtained according to these drawings without creative efforts.

Fig. 1 is a schematic circuit structure diagram of a single-stage driving unit in a display driving circuit according to an embodiment of the present disclosure;

FIG. 2 is a schematic diagram of a first cascade relationship of a display driving circuit according to an embodiment of the present application;

FIG. 3 is a first input/output timing diagram of a display driver circuit according to an embodiment of the present disclosure;

FIG. 4 is a diagram illustrating a second cascade relationship of a display driver circuit according to an embodiment of the present application;

fig. 5 is a second input/output timing diagram of a display driving circuit according to an embodiment of the present application.

Detailed Description

The following description of the various embodiments refers to the accompanying drawings, which are included to illustrate specific embodiments that can be implemented by the application. Directional phrases used in this application, such as [ upper ], [ lower ], [ front ], [ rear ], [ left ], [ right ], [ inner ], [ outer ], [ side ], etc., refer only to the directions of the attached drawings. Accordingly, the directional terminology is used for purposes of illustration and understanding, and is in no way limiting. In the drawings, elements having similar structures are denoted by the same reference numerals.

The embodiment of the application provides a display driving circuit, which comprises a plurality of stages of driving units, wherein each stage of driving unit is independently provided with a second high-voltage signal input end, and a high-voltage signal input by the second high-voltage signal input end is transmitted to a cascade signal output end through a pull-up unit, so that the display driving circuit outputs a high-voltage driving signal; meanwhile, the high-voltage signal input by the second high-voltage signal input end does not directly act on a thin film transistor gate in the display driving circuit, so that the increase of internal stress of the thin film transistor is avoided; the technical design obviously improves the driving capability and driving stability of the display driving circuit.

Fig. 1 is a schematic circuit structure diagram of a single-stage driving unit in a display driving circuit according to an embodiment of the present application, and is referred to fig. 1. The display driving circuit provided by the embodiment of the application comprises a plurality of stages of driving units, and the circuit structure of each stage of driving unit is shown in fig. 1. Each stage of the driving unit includes a pull-up control unit 10, a pull-up unit 20, a pull-down control unit 30, a transition control unit 40, a pull-down unit 50, and a feedback unit 60. It should be noted that, there are electrical connections between the unit modules in the display driving unit, and each unit module has its specific function and cooperates with other unit modules.

The pull-up control unit 10 is electrically connected to the first control signal input terminal 101, the first cascade signal input terminal 102, the first clock signal input terminal 106, the first high voltage signal input terminal 103, and the first node Q1. The pull-up control unit 10 is configured to transmit the signal input from the first clock signal input terminal 106 to the first node Q1 under the control of the signals input from the first control signal input terminal 101, the first cascade signal input terminal 102 and the first high voltage signal input terminal 103, so as to adjust the voltage state of the first node Q1.

Optionally, the pull-up control unit 10 includes a first transistor T1, a second transistor T2, a third transistor T3, and a first capacitor C1; a gate, a source and a drain of the first transistor T1 are electrically connected to the first cascade signal input terminal 102, the first control signal input terminal 101 and the second node Q2, respectively, a gate and a source of the second transistor T2 are electrically connected to the second node Q2 and the first clock signal input terminal 106, respectively, a gate and a drain of the third transistor T3 are electrically connected to the first high voltage signal input terminal 103 and the first node Q1, respectively, a drain of the second transistor T2 is electrically connected to a source of the third transistor T3, and two ends of the first capacitor C1 are electrically connected to a drain of the second transistor T2 and the second node Q2, respectively.

Note that the transistor used in the display driver circuit provided in the embodiment of the present application may be an n-type transistor or a p-type transistor. In order to facilitate understanding of the present application, n-type transistors are used as an example in the present embodiment. It should be understood that for an n-type transistor, when the gate of the transistor is at a high voltage, the source and drain of the transistor are on, the transistor is on, and vice versa the transistor is off; for a p-type transistor, when the gate of the transistor is at a low voltage, the source and drain of the transistor are turned on, the transistor is turned on, and vice versa.

Optionally, the transistor used in the display driving circuit provided in the embodiment of the present application is a thin film transistor based on LTPO technology.

The pull-up unit 20 is electrically connected to the second high voltage signal input terminal 105, the first node Q1 and the cascade signal output terminal 113. The pull-up unit 20 is configured to transmit the signal input from the second high voltage signal input terminal 105 to the cascade signal output terminal 113 under the control of the signal at the first node Q1. The voltage signal input by the second high voltage signal input terminal 105 is a high voltage, and specifically, the voltage input by the second high voltage signal input terminal 105 is greater than the voltage input by the first high voltage signal input terminal 103.

It should be understood that the high voltage signal input from the second high voltage signal input terminal 105 is directly transmitted to the cascade signal output terminal 113 through the pull-up unit 20, and is transmitted to each display unit of the display panel through the cascade signal output terminal 113; since the voltage signal input by the second high voltage signal input terminal 105 is higher, the whole row of display cells in the display panel is more easily lighted at the same time. In the display driving circuit based on the LTPO technology, the embodiment can realize high-level voltage output without increasing the length-width ratio of the LTPO semiconductor layer or increasing the gate-source voltage difference of the thin film transistor, and compared with the prior art, the aperture ratio of the display panel and the overall stability of the display driving circuit are improved.

Optionally, the pull-up unit 20 includes a fourth transistor T4, and a gate, a source and a drain of the fourth transistor T4 are electrically connected to the first node Q1, the second high voltage signal input terminal 105 and the cascade signal output terminal 113, respectively. It should be understood that the fourth transistor T4 can control the conducting state between the second high voltage signal input terminal 105 and the cascade signal output terminal 113 under the voltage of the first node Q1.

The pull-down control unit 30 is electrically connected to the first control signal input terminal 101, the second clock signal input terminal 107, the third clock signal input terminal 108, the second control signal input terminal 109, the first high-voltage signal input terminal 103, the low-voltage signal input terminal 104, the second cascade signal input terminal 110, and the third node P. The pull-down control unit 30 is configured to transmit the signal input by the first high-voltage signal input terminal 103 and/or the low-voltage signal input terminal 104 to the third node P under the common control of the signals input by the first control signal input terminal 101, the second clock signal input terminal 107, the third clock signal input terminal 108, the second control signal input terminal 109, and the second cascade signal input terminal 110. It should be understood that, by the above circuit structure design, it can be ensured that the voltage signal of the third node P is maintained between the voltage signal input by the first high voltage signal input terminal 103 and the voltage signal input by the low voltage signal input terminal 104.

Optionally, the pull-down control unit 30 includes a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, a ninth transistor T9, a tenth transistor T10 and a third capacitor C3, a gate and a source of the fifth transistor T5 are electrically connected to the first control signal input terminal 101 and the second clock signal input terminal 107, respectively, a drain of the fifth transistor T5 is electrically connected to a drain of the sixth transistor T6 and a gate of the seventh transistor T7, a gate and a source of the sixth transistor T6 are electrically connected to the second control signal input terminal 109 and the third clock signal input terminal 108, respectively, a source and a drain of the seventh transistor T7 are electrically connected to the first high voltage signal input terminal 103 and the third node P, respectively, a gate and a source of the eighth transistor T8 are electrically connected to the second cascade signal input terminal 110 and the second control signal input terminal 109, respectively, a drain of the eighth transistor T8 is electrically connected to the second node Q2 and a gate of the ninth transistor T9, a source and a drain of the ninth transistor T9 are electrically connected to the low voltage signal input terminal 104 and the third node P, respectively, a gate, a source and a drain of the tenth transistor T10 are electrically connected to the third node P, the low voltage signal input terminal 104 and a drain of the third transistor T3, respectively, and two ends of the third capacitor C3 are electrically connected to the low voltage signal input terminal 104 and the third node P, respectively. It should be understood that the highest voltage of the third node P is the voltage inputted from the first high voltage signal input terminal 103, and the voltage value is lower than the voltage inputted from the second high voltage signal input terminal 105, so that the voltage difference between the gate and the source of the tenth transistor T10 is not too large to generate too much stress, which is beneficial to the stability of the performance thereof.

The transition control unit 40 is electrically connected to the third node P, the low voltage signal input terminal 104, the first transition signal input terminal 111, the second transition signal input terminal 112, and the cascade signal output terminal 113. The transition control unit 40 is configured to transmit the signal input by the low voltage signal input terminal 112 to the third node P and/or the cascade signal output terminal 113 under the control of the signals input by the first transition signal input terminal 111 and the second transition signal input terminal 112. It should be noted that, the jump control unit 40 is configured to enable the cascade signal output terminal 113 to output a low voltage signal when the display panel is changed from the normal display mode to the touch mode, for example, when the display panel is changed from the normal display mode to the touch mode, the first jump signal input terminal 111 inputs a low voltage, the second jump signal input terminal 112 inputs a high voltage, and the low voltage signal input by the low voltage signal input terminal 104 is transmitted to the cascade signal output terminal 113 through the jump control unit 40, so as to transmit the low voltage signal to the display panel.

Optionally, the transition control unit 40 includes an eleventh transistor T11, a twelfth transistor T12 and a thirteenth transistor T13, a gate and a source of the eleventh transistor T11 and a gate of the twelfth transistor T12 are electrically connected to the first transition signal input 111, a drain of the eleventh transistor T11 is electrically connected to the cascade signal output 113, a source and a drain of the twelfth transistor T12 are electrically connected to the low voltage signal input 104 and the third node P, respectively, and a gate, a source and a drain of the thirteenth transistor T13 are electrically connected to the second transition signal input 112, the low voltage signal input 104 and the cascade signal output 113, respectively.

The pull-down unit 50 is electrically connected to the third node P, the low voltage signal input terminal 104 and the cascade signal output terminal 113. The pull-down unit 50 is configured to transmit a signal input by the low-voltage signal input terminal 104 to the cascade signal output terminal 113 under the control of a signal of the third node P, so that the cascade signal output terminal 113 transmits a low-voltage signal to the display panel.

Optionally, the pull-down unit 50 includes a fourteenth transistor T14, and a gate, a source and a drain of the fourteenth transistor T14 are electrically connected to the third node P, the low voltage signal input terminal 104 and the cascade signal output terminal 113, respectively.

The feedback unit 60 is electrically connected to the first node Q1 and the cascade signal output terminal 113, and is configured to feed back a signal output by the cascade signal output terminal 113 to the first node Q1, so as to adjust an operating state of the pull-up unit 20.

Optionally, the feedback unit 60 includes a second capacitor C2, and two ends of the second capacitor C2 are electrically connected to the first node Q1 and the cascade signal output terminal 113, respectively.

Fig. 2 is a schematic diagram of a first cascade relationship of a display driving circuit according to an embodiment of the present application. In this embodiment, the display driving circuit is connected to four clock signal lines, and it should be noted that, in some embodiments, the display driving circuit may also provide clock signals to the display driving circuit through six or eight clock signal lines. The first cascade signal input terminal 102 of the nth stage of the driving unit U (n) is electrically connected to the cascade signal output terminal 113 of the (n-1) th stage of the driving unit U (n), and the second cascade signal input terminal 110 of the nth stage of the driving unit U (n) is electrically connected to the cascade signal output terminal 113 of the (n +1) th stage of the driving unit U (n + 1); the cascade signal output end 113 of the nth stage of the driving unit u (n) outputs a cascade signal g (n); wherein n is an integer greater than 1. It should be noted that the first cascade signal input terminal 102 of the driving unit of the 1 st stage is electrically connected to a trigger signal line, and the display driving circuit is triggered integrally through the trigger signal line.

In the present embodiment, the display driving circuit is connected to four clock signal lines, which are a first clock signal line CK1, a second clock signal line CK2, a third clock signal line CK3, and a fourth clock signal line CK 4. Specifically, the first clock signal input terminal 106, the second clock signal input terminal 107 and the third clock signal input terminal 108 of the (k + 4) th stage of the driving unit are electrically connected to the first clock signal line CK1, the second clock signal line CK2 and the third clock signal line CK3, respectively, and correspond to the connection relationship between the clock signal input terminals and the clock signal lines of the nth stage of the driving unit u (n) shown in fig. 2; the first clock signal input terminal 106, the second clock signal input terminal 107 and the third clock signal input terminal 108 of the (k +4i +1) -th stage of the driving unit are electrically connected to the second clock signal line CK2, the third clock signal line CK3 and the fourth clock signal line CK4, respectively, corresponding to the connection relationship between the clock signal input terminal and the clock signal line of the (n +1) -th stage of the driving unit U (n +1) shown in fig. 2; the first clock signal input terminal 106, the second clock signal input terminal 107 and the third clock signal input terminal 108 of the (k +4i +2) -th stage of the driving unit are electrically connected to the third clock signal line CK3, the fourth clock signal line CK4 and the first clock signal line CK1, respectively, corresponding to the connection relationship between the clock signal input terminals and the clock signal lines of the (n +2) -th stage of the driving unit U (n +2) shown in fig. 2; the first clock signal input terminal 106, the second clock signal input terminal 107 and the third clock signal input terminal 108 of the (k +4i + 3) -th stage of the driving unit are electrically connected to the fourth clock signal line CK4, the first clock signal line CK1 and the second clock signal line CK2, respectively, corresponding to the connection relationship between the clock signal input terminal and the clock signal line of the driving unit U (n-1) of the (n-1) -th stage shown in fig. 2; wherein k is an integer greater than or equal to 1, and i is an integer greater than or equal to 0.

Optionally, the display driving circuit includes N stages of the driving units; the display driving circuit can perform forward scanning and can also perform reverse scanning. When the first control signal input terminal 101 inputs a high voltage and the second control signal input terminal 109 inputs a low voltage, the display driving circuit scans in the forward direction, that is: the driving units of the first stage to the Nth stage sequentially output cascade signals. When the first control signal input terminal 101 inputs a low voltage and the second control signal input terminal 109 inputs a high voltage, the display driving circuit performs reverse scanning, that is: and the driving units from the Nth stage to the first stage sequentially output cascade signals. Wherein N is an integer greater than or equal to 1.

The input/output timing of the display driving circuit provided in this embodiment is described with reference to fig. 1 to 3, where fig. 3 is a first input/output timing diagram of the display driving circuit provided in this embodiment.

For the description of the nth stage of the driving unit, the first control signal input terminal 101 inputs a high voltage, and the second control signal input terminal 109 inputs a low voltage:

in a T1 time period, the cascade signal G (n-1) output from the cascade signal output terminal 113 of the driving unit U (n-1) of the (n-1) th stage transitions to a high voltage, the first transistor T1 is turned on, the high voltage signal input from the first control signal input terminal 101 is transmitted to the second node Q2 to raise the voltage of the second node Q2, the second transistor T2 is turned on, the first clock signal input terminal 106 is connected to the first clock signal line CK1 to input a low voltage, the third transistor T3 is turned on, the low voltage signal input from the first clock signal input terminal 106 is transmitted to the first node Q1 to keep the first node Q1 in a low voltage state, and the fourth transistor T4 is turned off; under the action of the high voltage signal at the second node Q2, the ninth transistor T9 is turned on, the low voltage signal inputted from the low voltage signal input terminal 104 is transmitted to the third node P, and the voltage of the third node P is pulled down; the fourteenth transistor T14 is turned off, and the cascade signal output terminal 113 cannot accept any voltage signal and has no voltage output.

In a period T2, the first transistor T1 is turned off, the second node Q2 briefly maintains a high voltage state in a period T1 under the action of the first capacitor C1, the second transistor T2 is kept turned on, the first clock signal input terminal 106 is connected to the first clock signal line CK1 to input a high voltage signal, the voltage of the second node Q2 is further boosted under the action of the first capacitor C1, and the second transistor T2 is fully turned on; the third transistor T3 is turned on, the high voltage signal inputted from the first clock signal input terminal 106 is transmitted to the first node Q1, the fourth transistor T4 is turned on, and the high voltage signal inputted from the second high voltage signal input terminal 105 is transmitted to the cascade signal output terminal 113, so that the cascade signal g (n) outputted from the nth driving unit u (n) is a high voltage signal; the second node Q2 is a high voltage, the ninth transistor T9 maintains an on state, the third node P maintains a low voltage state, and the fourteenth transistor T14 is turned off. The cascade signal output terminal 113 outputs a high voltage signal.

In a time period T3, the second cascade signal input terminal 110 inputs a high voltage signal, the eighth transistor T8 is turned on, the low voltage signal input from the second control signal input terminal 109 is transmitted to the second node Q2, the voltage of the second node Q2 is pulled low, and the ninth transistor T9 is turned off; the fifth transistor T5 is turned on by the high voltage signal inputted from the first control signal input terminal 101, the second clock signal input terminal 107 is connected to the second clock signal line CK2 to input and output the high voltage signal, the seventh transistor T7 is turned on, the high voltage signal inputted from the high voltage signal input terminal 103 is transmitted to the third node P, the voltage of the third node P is raised, the fourteenth transistor T14 is turned on, the low voltage signal inputted from the low voltage signal input terminal 104 is transmitted to the cascade signal output terminal 113, and the voltage of the first node Q1 is pulled down by the second capacitor C2. The cascade signal output terminal 113 outputs a low voltage signal.

Fig. 4 is a schematic diagram of a second cascade relationship of the display driver circuit according to the embodiment of the present application. In this embodiment, the display driving circuit is connected to eight clock signal lines. The first cascade signal input terminal 102 of the nth stage of the driving unit U (n) is electrically connected to the cascade signal output terminal 113 of the nth-2 stage of the driving unit U (n-2), and the second cascade signal input terminal 110 of the nth stage of the driving unit U (n) is electrically connected to the cascade signal output terminal 113 of the (n +2) th stage of the driving unit U (n + 2); the cascade signal output end 113 of the nth stage of the driving unit u (n) outputs a cascade signal g (n); wherein n is an integer greater than 2. It should be noted that the first cascade signal input terminal 102 of the 1 st stage driving unit and the first cascade signal input terminal 102 of the 2 nd stage driving unit are electrically connected to a trigger signal line, and the display driving circuit is triggered integrally through the trigger signal line.

In this embodiment, the display driving circuit is connected to eight clock signal lines, namely, a first clock signal line CK1, a second clock signal line CK2, a third clock signal line CK3, a fourth clock signal line CK4, a fifth clock signal line CK5, a sixth clock signal line CK6, a seventh clock signal line CK7, and an eighth clock signal line CK 8. Specifically, the first clock signal input terminal, the second clock signal input terminal, and the third clock signal input terminal of the (k + 8) th stage of the driving unit are electrically connected to the first clock signal line, the third clock signal line, and the fifth clock signal line, respectively, and correspond to the connection relationship between the clock signal input terminal and the clock signal line of the nth stage of the driving unit u (n) shown in fig. 4; the first clock signal input end, the second clock signal input end and the third clock signal input end of the (k +8i +1) -th-stage driving unit are respectively and electrically connected to the second clock signal line, the fourth clock signal line and the sixth clock signal line, and correspond to the connection relationship between the clock signal input end and the clock signal line of the (n +1) -th-stage driving unit U (n +1) shown in fig. 4; the first clock signal input end, the second clock signal input end and the third clock signal input end of the (k +8i +2) th-stage driving unit are respectively and electrically connected to the third clock signal line, the fifth clock signal line and the seventh clock signal line, and correspond to the connection relationship between the clock signal input end and the clock signal line of the (n +2) th-stage driving unit U (n +2) shown in fig. 4; the first clock signal input end, the second clock signal input end and the third clock signal input end of the (k +8i + 3) -th-stage driving unit are respectively and electrically connected to the fourth clock signal line, the sixth clock signal line and the eighth clock signal line; the first clock signal input end, the second clock signal input end and the third clock signal input end of the (k +8i + 4) -th-stage driving unit are electrically connected to the fifth clock signal line, the seventh clock signal line and the first clock signal line respectively; the first clock signal input end, the second clock signal input end and the third clock signal input end of the (k +8i + 5) -th stage of the driving unit are electrically connected to the sixth clock signal line, the eighth clock signal line and the second clock signal line respectively; the first clock signal input end, the second clock signal input end and the third clock signal input end of the (k +8i + 6) -th-stage driving unit are respectively and electrically connected to the seventh clock signal line, the first clock signal line and the third clock signal line; the first clock signal input end, the second clock signal input end and the third clock signal input end of the (k +8i + 7) -th-stage driving unit are respectively and electrically connected to the eighth clock signal line, the second clock signal line and the fourth clock signal line; wherein k is an integer greater than or equal to 1, and i is an integer greater than or equal to 0.

The input/output timing of the display driving circuit provided in this embodiment is described below with reference to fig. 1, fig. 4, and fig. 5, where fig. 5 is a second input/output timing diagram of the display driving circuit provided in this embodiment.

The driving unit of the nth stage is taken as an example for explanation, and the first control signal input terminal 101 inputs a high voltage, and the second control signal input terminal 109 inputs a low voltage.

In a T1 time period, the cascade signal G (n-2) output from the cascade signal output terminal 113 of the driving unit U (n-2) of the n-2 th stage is transited to a high voltage, the first transistor T1 is turned on, the high voltage signal input from the first control signal input terminal 101 is transmitted to the second node Q2, the voltage of the second node Q2 is raised, the second transistor T2 is turned on, the first clock signal input terminal 106 is connected to the first clock signal line CK1 to input a low voltage, the third transistor T3 is turned on, the low voltage signal input from the first clock signal input terminal 106 is transmitted to the first node Q1, the first node Q1 is maintained in a low voltage state, and the fourth transistor T4 is turned off; under the action of the high voltage signal at the second node Q2, the ninth transistor T9 is turned on, the low voltage signal inputted from the low voltage signal input terminal 104 is transmitted to the third node P, and the voltage of the third node P is pulled down; the fourteenth transistor T14 is turned off, and the cascade signal output terminal 113 cannot accept any voltage signal and has no voltage output.

In a time period T2, the first transistor T1 is turned off, under the action of the first capacitor C1, the second node Q2 maintains a high voltage state in the time period T1, the second transistor T2 is kept turned on, the first clock signal input end 106 is connected to the first clock signal line CK1 to continuously input a low voltage signal, the first node Q1 maintains a low voltage state, and the fourth transistor T4 is kept turned off; the ninth transistor T9 maintains an on state, the third node P maintains a low voltage state, and the fourteenth transistor T14 is turned off. The cascade signal output 113 has no voltage output.

In a time period T3, the first clock signal input terminal 106 is connected to the first clock signal line CK1 to input a high voltage signal, and the voltage of the second node Q2 is further boosted by the first capacitor C1, and the second transistor T2 is fully turned on; the third transistor T3 is turned on, the high voltage signal inputted from the first clock signal input terminal 106 is transmitted to the first node Q1, the fourth transistor T4 is turned on, and the high voltage signal inputted from the second high voltage signal input terminal 105 is transmitted to the cascade signal output terminal 113, so that the cascade signal g (n) outputted from the nth driving unit u (n) is a high voltage signal; the second node Q2 is a high voltage, the ninth transistor T9 maintains an on state, the third node P maintains a low voltage state, and the fourteenth transistor T14 is turned off. The cascade signal output terminal 113 outputs a high voltage signal.

In summary, the display driving circuit provided in the embodiment of the present application includes multiple stages of driving units, each stage of the driving unit is separately provided with a second high voltage signal input end, and a high voltage signal input by the second high voltage signal input end is directly transmitted to a cascade signal output end through a pull-up unit, so that the display driving circuit outputs a high voltage driving signal; meanwhile, the high-voltage signal input by the second high-voltage signal input end does not directly act on the grid electrode of the thin film transistor in the display driving circuit, so that the increase of the internal stress of the thin film transistor is avoided. In the display driving circuit based on the LTPO technology, the embodiment can realize high-level voltage output without increasing the length-width ratio of the LTPO semiconductor layer or increasing the gate-source voltage difference of the thin film transistor, and compared with the prior art, the aperture ratio of the display panel and the overall stability of the display driving circuit are improved.

It should be noted that, although the present application has been described with reference to specific examples, the above-mentioned examples are not intended to limit the present application, and those skilled in the art can make various changes and modifications without departing from the spirit and scope of the present application, so that the scope of the present application shall be limited by the appended claims.

Claims

1. A display driving circuit comprising a plurality of stages of driving units, each of the stages of driving units comprising:

2. The display driving circuit according to claim 1, wherein the pull-up control unit comprises a first transistor, a second transistor, a third transistor and a first capacitor, wherein a gate, a source and a drain of the first transistor are electrically connected to the first cascade signal input terminal, the first control signal input terminal and a second node, respectively, a gate and a source of the second transistor are electrically connected to the second node and the first clock signal input terminal, respectively, a gate and a drain of the third transistor are electrically connected to the first high voltage signal input terminal and the first node, respectively, a drain of the second transistor is electrically connected to a source of the third transistor, and two ends of the first capacitor are electrically connected to a drain of the second transistor and the second node, respectively.

3. The display driving circuit according to claim 1, wherein the pull-up unit comprises a fourth transistor, and a gate, a source and a drain of the fourth transistor are electrically connected to the first node, the second high voltage signal input terminal and the cascade signal output terminal, respectively.

4. The display driving circuit according to claim 1, wherein the feedback unit comprises a second capacitor, and two ends of the second capacitor are electrically connected to the first node and the cascade signal output terminal, respectively.

5. The display driving circuit according to claim 1, wherein each stage of the driving unit further comprises:

6. The display driving circuit according to claim 5, wherein the pull-down control unit comprises a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, and a third capacitor, wherein a gate and a source of the fifth transistor are electrically connected to the first control signal input terminal and the second clock signal input terminal, respectively, a drain of the fifth transistor is electrically connected to a drain of the sixth transistor and a gate of the seventh transistor, a gate and a source of the sixth transistor are electrically connected to the second control signal input terminal and the third clock signal input terminal, respectively, a source and a drain of the seventh transistor are electrically connected to the first high voltage signal input terminal and the third node, respectively, a gate and a source of the eighth transistor are electrically connected to the second cascade signal input terminal and the second control signal input terminal, respectively, the drain of the eighth transistor is electrically connected to the gate of the ninth transistor, the source and the drain of the ninth transistor are electrically connected to the low-voltage signal input terminal and the third node, respectively, the gate and the source of the tenth transistor are electrically connected to the third node and the low-voltage signal input terminal, respectively, and two ends of the third capacitor are electrically connected to the low-voltage signal input terminal and the third node, respectively.

7. The display driving circuit according to claim 5, wherein the transition control unit comprises an eleventh transistor, a twelfth transistor and a thirteenth transistor, wherein a gate and a source of the eleventh transistor and a gate of the twelfth transistor are electrically connected to the first transition signal input terminal, a drain of the eleventh transistor is electrically connected to the cascade signal output terminal, a source and a drain of the twelfth transistor are electrically connected to the low voltage signal input terminal and the third node, respectively, and a gate, a source and a drain of the thirteenth transistor are electrically connected to the second transition signal input terminal, the low voltage signal input terminal and the cascade signal output terminal, respectively.

8. The display driving circuit according to claim 5, wherein the pull-down unit comprises a fourteenth transistor, and a gate, a source and a drain of the fourteenth transistor are electrically connected to the third node, the low voltage signal input terminal and the cascade signal output terminal, respectively.

9. The display driving circuit according to claim 5, wherein the first cascade signal input terminal of the nth stage of the driving unit is electrically connected to the cascade signal output terminal of the (n-1) th stage of the driving unit, and the second cascade signal input terminal of the nth stage of the driving unit is electrically connected to the cascade signal output terminal of the (n +1) th stage of the driving unit; wherein n is an integer greater than 1.

10. The display driving circuit according to claim 5, wherein the first cascade signal input terminal of the nth stage of the driving unit is electrically connected to the cascade signal output terminal of the n-2 th stage of the driving unit, and the second cascade signal input terminal of the nth stage of the driving unit is electrically connected to the cascade signal output terminal of the n +2 th stage of the driving unit; wherein n is an integer greater than 2.