CN110570800A - Gate drive circuit and display panel - Google Patents
Gate drive circuit and display panel Download PDFInfo
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- CN110570800A CN110570800A CN201910743576.XA CN201910743576A CN110570800A CN 110570800 A CN110570800 A CN 110570800A CN 201910743576 A CN201910743576 A CN 201910743576A CN 110570800 A CN110570800 A CN 110570800A
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
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Abstract
the invention provides a grid driving circuit and a display panel, wherein the grid driving circuit comprises a first pull-up circuit, a second pull-up circuit, a pull-down circuit, a phase inverter, a first pull-down maintaining circuit, a second pull-down maintaining circuit and a pull-up maintaining circuit, the pull-up control circuit is arranged to promote the electric potential of a first point under the control of a third clock signal, so that the electric potential of a second point can be reduced for a period of time in each period, the voltage-bearing time of a transistor of the pull-down maintaining circuit is reduced, the stability of the grid driving circuit is improved, the second pull-down maintaining circuit ensures that the electric potential of the first point is reduced when the first point is at a high electric potential at the second point, and the technical problem that the existing grid driving circuit is poor in stability is solved.
Description
Technical Field
the invention relates to the technical field of display, in particular to a gate driving circuit and a display panel.
background
As shown in fig. 1, a pull-down maintaining circuit in the GOA circuit is used to maintain a Q point, a Gate signal Cout (n) and an output signal G (n) at a low level, where a QB point controls a Gate pole of a TFT in the pull-down maintaining circuit, but the QB point is at a high potential for a long time, so that the TFT of the pull-down maintaining unit is in an on state for a long time.
Therefore, the conventional gate driving circuit has the technical problem of poor stability.
disclosure of Invention
The invention provides a gate driving circuit and a display panel, which are used for solving the technical problem of poor stability of the conventional gate driving circuit.
in order to solve the above problems, the technical scheme provided by the invention is as follows:
The present invention provides a gate driving circuit, including:
a first pull-up circuit;
a second pull-up circuit connected to the first pull-up circuit through a first point, the first point including a gate signal control node of the second pull-up circuit;
A pull-down circuit;
An inverter;
a first pull-down maintaining circuit connected to the inverter through a second point, the second point including a gate signal control node of the first pull-down maintaining circuit;
The second pull-down maintaining circuit comprises a fourth clock signal input end, is connected with the first point and is used for reducing the potential of the first point under the control of a fourth clock signal input by the fourth clock signal input end;
and the pull-up control circuit comprises a third clock signal input end, is connected with the first point and is used for raising the potential of the first point under the control of a third clock signal input by the third clock signal input end so as to reduce the potential of the second point.
In the gate driving circuit provided by the present invention, the first pull-up circuit includes a first transistor, a first signal input terminal, and a first stage signal terminal, a gate of the first transistor is connected to the first stage signal terminal, a first electrode of the first transistor is connected to the first signal input terminal, and a second electrode of the first transistor is connected to the first point.
in the gate driving circuit provided by the present invention, the gate driving circuit further includes a storage capacitor, a second level transmission signal terminal, and a second signal output terminal, the second pull-up circuit includes a second transistor, a third transistor, and a second clock signal input terminal, a gate of the second transistor is connected to the first point, a first electrode of the second transistor is connected to the second clock signal input terminal, a second electrode of the second transistor is connected to the second level transmission signal terminal, a gate of the third transistor is connected to the first point, a first electrode of the third transistor is connected to the second clock signal input terminal, a second electrode of the third transistor is connected to the second signal output terminal, the storage capacitor is connected to the first point, and the storage capacitor is connected to the second level transmission signal terminal.
in the gate driving circuit provided by the present invention, the second pull-down maintaining circuit further includes a fourth transistor and a low potential input terminal, a gate of the fourth transistor is connected to the fourth clock signal input terminal, a first electrode of the fourth transistor is connected to the low potential input terminal, and a second electrode of the fourth transistor is connected to the first point.
in the gate driving circuit provided by the present invention, the second pull-down holding circuit further includes a fifth transistor, a gate of the fifth transistor is connected to the second point, a first electrode of the fifth transistor is connected to the low potential input terminal, and a second electrode of the fifth transistor is connected to the first point.
In the gate driving circuit provided by the present invention, the first pull-down holding circuit includes a sixth transistor and a seventh transistor, a gate of the sixth transistor is connected to the second point, a first electrode of the sixth transistor is connected to the low potential input terminal, a second electrode of the sixth transistor is connected to the second stage signal terminal, a gate of the seventh transistor is connected to the second point, a first electrode of the seventh transistor is connected to the low potential input terminal, and a second electrode of the seventh transistor is connected to the second signal output terminal.
in the gate driving circuit provided by the present invention, the pull-down circuit includes an eighth transistor and a third level signal transmission end, a gate of the eighth transistor is connected to the third level signal transmission end, a first electrode of the eighth transistor is connected to the low potential input end, and a second electrode of the eighth transistor is connected to the second signal output end.
In the gate driving circuit provided by the present invention, the pull-up control circuit further includes a ninth transistor and a high potential input terminal, a gate of the ninth transistor is connected to the third clock signal input terminal, a first electrode of the ninth transistor is connected to the high potential input terminal, and a second electrode of the ninth transistor is connected to the first point.
in the gate driver circuit according to the present invention, the inverter includes a tenth transistor and an eleventh transistor, a gate of the tenth transistor is connected to the high potential input terminal, a first electrode of the tenth transistor is connected to the high potential input terminal, a second electrode of the tenth transistor is connected to the second point, a gate of the eleventh transistor is connected to the first point, a first electrode of the eleventh transistor is connected to the low potential input terminal, and a second electrode of the eleventh transistor is connected to the second point.
Meanwhile, the invention provides a display panel which comprises any one of the gate driving circuits.
has the advantages that: the invention provides a gate driving circuit and a display panel, the gate driving circuit comprising a first pull-up circuit, a second pull-up circuit, a pull-down circuit, an inverter, a first pull-down maintaining circuit, a second pull-down maintaining circuit and a pull-up maintaining circuit, the second pull-up circuit being connected to the first pull-up circuit through a first point, the first point comprising a gate signal control node of the second pull-up circuit, the first pull-down maintaining circuit being connected to the inverter through a second point, the second point comprising a gate signal control node of the first pull-down maintaining circuit, the second pull-down maintaining circuit comprising a fourth clock signal input terminal, the second pull-down maintaining circuit being connected to the first point for lowering a potential of the first point under control of a fourth clock signal input at the fourth clock signal input terminal, the pull-up control circuit comprising a third clock signal input terminal, the pull-up control circuit is connected with the first point and used for raising the potential of the first point under the control of a third clock signal input by a third clock signal input end so as to reduce the potential of the second point; through setting up the control circuit that draws, make the control circuit that draws promote the electric potential of first point under the control of third clock signal, thereby make the electric potential of second point reduce a period in each cycle, thereby reduced the pressurized time of pull-down holding circuit's transistor, the stability of gate drive circuit has been increased, and the second pull-down holding circuit has guaranteed that first point is when the second point is in high potential, the electric potential of first point reduces, the current gate drive circuit of having solved has had the relatively poor technical problem of stability.
Drawings
In order to illustrate the embodiments or the technical solutions in the prior art more clearly, the drawings needed to be used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the invention, and it is obvious for a person skilled in the art that other drawings can be obtained according to these drawings without creative efforts.
FIG. 1 is a diagram of a conventional gate driving circuit;
FIG. 2 is a timing diagram of a conventional gate driving circuit;
Fig. 3 is a schematic diagram of a gate driving circuit according to an embodiment of the invention;
Fig. 4 is a timing diagram of a gate driving circuit according to an embodiment of the invention.
Detailed Description
The following description of the various embodiments refers to the accompanying drawings that illustrate specific embodiments in which the invention may be practiced. The directional terms mentioned in the present invention, such as [ upper ], [ lower ], [ front ], [ rear ], [ left ], [ right ], [ inner ], [ outer ], [ side ], are only referring to the directions of the attached drawings. Accordingly, the directional terms used are used for explanation and understanding of the present invention, and are not used for limiting the present invention. In the drawings, elements having similar structures are denoted by the same reference numerals.
The embodiment of the invention is used for solving the technical problem that the existing gate drive circuit has poor stability.
As shown in fig. 1, the conventional GOA circuit includes a third pull-up circuit 111, a fourth pull-up circuit 112, an nth stage signal output terminal 113, an nth stage signal transmission terminal 114, a storage capacitor 115, a third pull-down circuit 121, a third pull-down maintaining circuit 122, an inverter 123, a fourth pull-down maintaining circuit 124, and a fourth pull-down circuit 125, the third pull-up circuit 111 includes an (n-1) th stage signal input terminal Out (n-1), an (n-1) th stage signal transmission terminal Cout (n-1), and a transistor T1, the fourth pull-up circuit 112 includes a second clock signal input terminal CK2, a transistor T22, and a transistor T21, the nth stage signal output terminal Out (n) is connected to the transistor T21, the nth stage signal transmission terminal Cout (n) is connected to the transistor T22, the storage capacitor is connected to a Q point, the third pull-down circuit 121 includes an (n +1) th stage signal terminal T83 and a transistor T51, the third pull-down sustain circuit 122 includes a transistor T31 and a transistor T32, the inverter 123 includes a high potential input terminal VGH, a transistor T41 and a transistor T42, the fourth pull-down sustain circuit 124 includes a transistor T33, and the fourth pull-down sustain circuit 125 includes an (n +1) th stage pass signal terminal Cout (n +1), a low potential input terminal VGL, and a transistor T34, as shown in fig. 2, as seen from the timing diagram, in the GOA circuit, the QB point is at a high potential for a long time, and is at a low potential only when the Q point is at the high potential, and point QB is connected to the gate of the transistor of the pull-down sustain circuit, so that the gate of the transistor is on for a long time, therefore, when the transistor is stressed, the threshold voltage of the transistor is positively biased, so that the pull-down maintaining capability of the QB point is weakened, and the stability of the circuit is reduced, namely the existing gate driving circuit has the technical problem of poor stability.
As shown in fig. 3, an embodiment of the present invention provides a gate driving circuit, including:
A first pull-up circuit 211;
a second pull-up circuit 213 connected to the first pull-up circuit 211 through a first point 231, the first point 231 including a gate signal control node of the second pull-up circuit 213;
A pull-down circuit 221;
An inverter 223;
A first pull-down sustain circuit 222 connected to the inverter 223 through a second point 232, the second point 232 including a gate signal control node of the first pull-down sustain circuit 222;
a second pull-down holding circuit 224 comprising a fourth clock signal input terminal CK4, the second pull-down holding circuit 224 being connected to the first point 231 for lowering the potential of the first point 231 under the control of the fourth clock signal 224 inputted from the fourth clock signal input terminal CK 4;
the pull-up control circuit 212 comprises a third clock signal input terminal CK3, and the pull-up control circuit 212 is connected to the first point 231 and is configured to raise the potential of the first point 231 under the control of the third clock signal input terminal CK3 so as to lower the potential of the second point 232.
An embodiment of the present invention provides a gate driving circuit, including a first pull-up circuit, a second pull-up circuit, a pull-down circuit, an inverter, a first pull-down maintaining circuit, a second pull-down maintaining circuit, and a pull-up maintaining circuit, the second pull-up circuit being connected to the first pull-up circuit through a first point, the first point including a gate signal control node of the second pull-up circuit, the first pull-down maintaining circuit being connected to the inverter through a second point, the second point including a gate signal control node of the first pull-down maintaining circuit, the second pull-down maintaining circuit including a fourth clock signal input terminal, the second pull-down maintaining circuit being connected to the first point for lowering a potential of the first point under control of a fourth clock signal input at the fourth clock signal input terminal, the pull-up control circuit including a third clock signal input terminal, the pull-up control circuit is connected with the first point and used for raising the potential of the first point under the control of a third clock signal input by a third clock signal input end so as to reduce the potential of the second point; through setting up the control circuit that draws, make the control circuit that draws promote the electric potential of first point under the control of third clock signal, thereby make the electric potential of second point reduce a period in each cycle, thereby reduced the pressurized time of pull-down holding circuit's transistor, the stability of gate drive circuit has been increased, and the second pull-down holding circuit has guaranteed that first point is when the second point is in high potential, the electric potential of first point reduces, the current gate drive circuit of having solved has had the relatively poor technical problem of stability.
It should be noted that, as shown in fig. 3, the gate signal control nodes of the second pull-up circuit 213 include the gate T2 of the second transistor and the gate T3 of the third transistor, that is, the first point includes the gate of the second transistor, the gate of the third transistor, the gate signal control node of the first pull-down sustain circuit 222 includes the gate of the sixth transistor T7, the gate of the seventh transistor T8, i.e. the second point comprises the gate of the sixth transistor, the gate of the seventh transistor, in practice the first point may be the connection point of the gate of the second transistor or the connection point of the gate of the third transistor, or a connection point of the gate of the second transistor and the gate of the third transistor, and the second point may be a connection point of the gate of the sixth transistor or the gate of the seventh transistor, or a connection point of the gate of the sixth transistor and the gate of the seventh transistor.
It should be noted that, as shown in fig. 3, a line crossing in the figure is marked with a first point or a second point to indicate that the line crossing is connected with a plurality of lines, such as the first point and the second point, and a line crossing in the figure is not marked with a first point or a second point to indicate that the line crossing is not connected with a plurality of connection lines, such as the first point is connected with the gate of the eleventh transistor T11, and the connection lines are not connected with the connection lines of the gate line of the fifth transistor T5 and the gate line of the sixth transistor T6, i.e., two connection lines are insulated therefrom.
It should be noted that, as shown in fig. 3, Out (n) represents a signal output end of any one stage in the gate driving circuit, corresponding Out (n-1) represents a signal output end of a stage above Out (n) and is also a signal input end of the gate driving circuit of the present stage, correspondingly, Cout (n) represents a stage transmission signal end of the gate driving circuit of the present stage, Cout (n-1) represents a stage transmission signal end of the gate driving circuit of the previous stage, and Cout (n +1) represents a stage transmission signal end of the gate driving circuit of the next stage.
in one embodiment, as shown in fig. 3, the first pull-up circuit 211 includes a first transistor T1, a first signal input terminal Out (n-1), and a first pass signal terminal Cout (n-1), a gate of the first transistor is connected to the first pass signal terminal, a first electrode of the first transistor is connected to the first signal input terminal, a second electrode of the first transistor is connected to the first point, and the first transistor is controlled by the first signal input terminal and the first pass signal terminal of the previous stage to raise the potential of the first point when the signals of the first signal input terminal and the first pass signal terminal are at a high potential.
In one embodiment, as shown in fig. 3, the gate driving circuit further includes a storage capacitor C, a second pass signal terminal Cout (n), a second signal output terminal Out (n), the second pull-up circuit 213 includes a second transistor T2, a third transistor T3, and a second clock signal input terminal CK2, a gate of the second transistor is connected to the first point, a first electrode of the second transistor is connected to the second clock signal input terminal, a second electrode of the second transistor is connected to the second-stage signal terminal, a gate of the third transistor is connected to the first point, a first electrode of the third transistor is connected to the second clock signal input terminal, a second electrode of the third transistor is connected to the second signal output terminal, the storage capacitor is connected with the first point, and the storage capacitor is connected with the second-stage signal transmission end.
in the embodiment of the present invention, when the second clock signal input terminal and the first point are at high potentials, the second transistor and the third transistor are turned on, so that the second level transmission signal terminal and the second signal output terminal output high potentials, and the storage capacitor can keep the second signal output terminal outputting the high potentials, thereby ensuring that the output high potentials are stable.
in one embodiment, as shown in fig. 3, the second pull-down maintaining circuit 224 further includes a fourth transistor T4 and a low potential input terminal VGL, a gate of the fourth transistor is connected to the fourth clock signal input terminal, a first electrode of the fourth transistor is connected to the low potential input terminal, a second electrode of the fourth transistor is connected to the first point, and the fourth transistor is turned on to lower the potential of the first point when a high potential is input to the fourth clock signal input terminal under the control of the fourth clock signal input terminal.
In one embodiment, as shown in fig. 3, the second pull-down maintaining circuit 224 further includes a fifth transistor T5, a gate of the fifth transistor is connected to the second point, a first electrode of the fifth transistor is connected to the low potential input terminal, and a second electrode of the fifth transistor is connected to the first point.
in one embodiment, as shown in fig. 3, the first pull-down maintaining circuit 222 includes a sixth transistor T6 and a seventh transistor T7, a gate of the sixth transistor is connected to the second point, a first electrode of the sixth transistor is connected to the low potential input terminal, a second electrode of the sixth transistor is connected to the second pass signal terminal, a gate of the seventh transistor is connected to the second point, a first electrode of the seventh transistor is connected to the low potential input terminal, a second electrode of the seventh transistor is connected to the second signal output terminal, and when the second point is at a high potential, the sixth transistor and the seventh transistor are turned on to enable the second pass signal terminal and the second signal output terminal to output a low potential.
In an embodiment, as shown in fig. 3, the pull-down circuit 221 includes an eighth transistor T8 and a third stage signal terminal Cout (n +1), a gate of the eighth transistor is connected to the third stage signal terminal, a first electrode of the eighth transistor is connected to the low potential input terminal, a second electrode of the eighth transistor is connected to the second signal output terminal, and when the third stage signal terminal outputs a high potential, the eighth transistor is turned on, so that the second signal output terminal outputs a low potential.
In one embodiment, as shown in fig. 3, the pull-up control circuit 212 further includes a ninth transistor T9 and a high voltage input terminal VGH, a gate of the ninth transistor is connected to the third clock signal input terminal, a first electrode of the ninth transistor is connected to the high voltage input terminal, a second electrode of the ninth transistor is connected to the first point, and when the third clock signal output terminal outputs a high voltage, the first point outputs a high voltage, so that the second point outputs a low voltage, and the second point is prevented from being at the high voltage for a long time.
In one embodiment, as shown in fig. 3, the inverter 223 includes a tenth transistor T10 and an eleventh transistor T11, a gate of the tenth transistor is connected to the high potential input terminal, a first electrode of the tenth transistor is connected to the high potential input terminal, a second electrode of the tenth transistor is connected to the second point, a gate of the eleventh transistor is connected to the first point, a first electrode of the eleventh transistor is connected to the low potential input terminal, and a second electrode of the eleventh transistor is connected to the second point.
In an embodiment of the present invention, a width-to-length ratio of the eleventh transistor is larger than a width-to-length ratio of the tenth transistor, that is, when both the tenth transistor and the eleventh transistor are turned on, a signal input to the eleventh transistor is output.
In one embodiment, the transistor is an N-type transistor.
In one embodiment, the first electrode of the transistor is a source and the second electrode of the transistor is a drain, or the first electrode of the transistor is a drain and the second electrode of the transistor is a source.
In one embodiment, the second pull-up circuit includes a second clock signal input terminal and a second transistor, a gate of the second transistor is connected to the first point, a first electrode of the second transistor is connected to the second clock signal terminal, a second electrode of the second transistor is connected to the second stage transfer signal terminal, and a second electrode of the second transistor is connected to the second signal output terminal, so that the second transistor can directly control the second stage transfer signal terminal and the second signal output terminal by connecting the second electrode of the second transistor to the second stage transfer signal terminal and the second signal output terminal.
In one embodiment, the first pull-down sustain circuit includes a sixth transistor, a gate of the sixth transistor is connected to the second point, a first electrode of the sixth transistor is connected to the low potential input terminal, a second electrode of the sixth transistor is connected to the second pass signal terminal, and a second electrode of the sixth transistor is connected to the second signal output terminal, so that the sixth transistor can directly control the second pass signal terminal and the second signal output terminal by connecting the second electrode of the sixth transistor to the second pass signal terminal and the second signal output terminal.
As shown in fig. 4, the timing diagram of Q in fig. 4 represents the timing diagram of the first point, and the timing diagram of QB in fig. 4 represents the timing diagram of the second point, and the operation process of the gate driving circuit in fig. 3 is analyzed with reference to fig. 4:
At the stage S1, when the third clock signal input terminal CK3 inputs a high potential, the first, second and fourth clock signal input terminals CK1, CK2 and CK4 input a low potential, and the first stage pass signal terminal Cout (n-1) inputs a low potential, the ninth transistor T9 is turned on, and the first transistor T1 is turned off, so that the potential at the first point is increased, which causes the second, third and eleventh transistors T2, T3 and T11 to be turned on, so that the second stage pass signal terminal Cout (n) and the second signal output terminal Out (n) output a low potential, and since the aspect ratio of the eleventh transistor T11 is greater than the aspect ratio of the tenth transistor T10, the second point outputs a low potential;
At the stage S2, the fourth clock signal input terminal CK4 inputs a high voltage, the first clock signal input terminal CK1, the second clock signal input terminal CK2 and the third clock signal input terminal CK3 input a low voltage, the first pass signal terminal Cout (n-1) inputs a low voltage, the fourth transistor T4 is turned on, the ninth transistor T9 is turned off, the first point outputs a low voltage, which results in the second transistor T2, the third transistor T3 and the eleventh transistor T11 being turned off, so that the second point outputs a low voltage, and the second pass signal terminal Cout (n) and the second signal output terminal Out (n) output a low voltage;
at the stage S3, when the first stage signal terminal Cout (n-1) inputs a low level and the first signal input terminal Out (n-1) inputs a high level, the second clock signal input terminal CK2, the third clock signal input terminal CK3 and the fourth clock signal input terminal CK4 input a low level, the first transistor T1 is turned on, so that the first point outputs a high level, which causes the second transistor T2, the third transistor T3 and the eleventh transistor T11 to be turned on, the second point outputs a low level, and the second stage signal terminal Cout (n) and the second signal output terminal Out (n) output a low level;
At the stage S4, the second clock signal input terminal CK2 inputs a high potential, the third clock signal input terminal CK3 and the fourth clock signal input terminal CK4 input a low potential, the first pass signal terminal Cout (n-1) inputs a low potential, the first transistor T1 is turned off because the second transistor T2 and the third transistor T3 are kept on, so that the second point outputs a low potential, the second pass signal terminal Cout (n) and the second signal output terminal Out (n) output a high potential, and the first point is raised to a higher potential due to the existence of the storage capacitor;
at the stage S5, the third stage signal transmission terminal Cout (n +1) inputs a high voltage, the third clock signal input terminal CK3 inputs a high voltage, the second clock signal input terminal CK2 and the fourth clock signal input terminal CK4 input a low voltage, the first stage signal transmission terminal Cout (n-1) inputs a low voltage, the ninth transistor T9 is turned on, the first transistor T1 is turned off, so that the first point outputs a high voltage, the second transistor T2, the third transistor T3 and the eleventh transistor T11 are turned on, the second point outputs a low voltage, and the second stage signal transmission terminal Cout (n) and the second signal output terminal Out (n) output a low voltage;
At the stage S6, the fourth clock signal input terminal CK4 inputs a high voltage, the second clock signal input terminal CK2 and the third clock signal input terminal CK3 input a low voltage, the first pass signal terminal Cout (n-1) inputs a low voltage, the fourth transistor T4 is turned on, the ninth transistor T9 is turned off, the first point outputs a low voltage, which causes the second transistor T2, the third transistor T3 and the eleventh transistor T11 to be turned off, so that the second point outputs a low voltage, and the second pass signal terminal Cout (n) and the second signal output terminal Out (n) output a low voltage.
Note that the first stage signal terminal and the first signal input terminal simultaneously input the same signal, for example, the first stage signal terminal and the first signal input terminal simultaneously input a high potential at S3.
as can be seen from fig. 4, in one frame time (16.6ms), except for one clock period T (i.e., 45 μ S) in which the previous gate driving circuit, the present gate driving circuit, and the next gate driving circuit operate (i.e., S3-S6), the second point maintains a low level for three-quarter clock periods (i.e., 30 μ S), and in other clock periods, every 45 μ S (i.e., one clock period T), the second point maintains a low level for 15 μ S, and the second pass signal terminal Cout (n) and the second signal output terminal Out (n) are maintained to output low levels in the non-operating time, so that the time that the second point is at a high level is reduced, the voltage-stressed time of the transistor of the pull-down maintaining circuit is reduced, and the stability of the gate driving circuit is increased.
Note that, one clock period T, that is, from the time when the high potential starts to be input to the first clock signal input terminal to the time when the high potential ends to be input to the fourth clock signal input terminal, is 45 μ s.
an embodiment of the present invention provides a display panel, including a gate driving circuit, where the gate driving circuit includes:
A first pull-up circuit;
a second pull-up circuit connected to the first pull-up circuit through a first point, the first point including a gate signal control node of the second pull-up circuit;
A pull-down circuit;
an inverter;
a first pull-down maintaining circuit connected to the inverter through a second point, the second point including a gate signal control node of the first pull-down maintaining circuit;
The second pull-down maintaining circuit comprises a fourth clock signal input end, is connected with the first point and is used for reducing the potential of the first point under the control of a fourth clock signal input by the fourth clock signal input end;
And the pull-up control circuit comprises a third clock signal input end, is connected with the first point and is used for raising the potential of the first point under the control of a third clock signal input by the third clock signal input end so as to reduce the potential of the second point.
In one embodiment, in the display panel provided in the embodiment of the present invention, the first pull-up circuit includes a first transistor, a first signal input terminal, and a first stage signal terminal, a gate of the first transistor is connected to the first stage signal terminal, a first electrode of the first transistor is connected to the first signal input terminal, and a second electrode of the first transistor is connected to the first point.
In one embodiment, in the display panel provided in the embodiment of the present invention, the gate driving circuit further includes a storage capacitor, a second stage signal terminal, and a second signal output terminal, the second pull-up circuit includes a second transistor, a third transistor and a second clock signal input terminal, a gate of the second transistor is connected to the first point, a first electrode of the second transistor is connected to the second clock signal input terminal, a second electrode of the second transistor is connected to the second-stage signal terminal, a gate of the third transistor is connected to the first point, a first electrode of the third transistor is connected to the second clock signal input terminal, a second electrode of the third transistor is connected to the second signal output terminal, the storage capacitor is connected with the first point, and the storage capacitor is connected with the second-stage signal transmission end.
In an embodiment, in the display panel provided in the embodiment of the present invention, the second pull-down sustain circuit further includes a fourth transistor and a low potential input terminal, a gate of the fourth transistor is connected to the fourth clock signal input terminal, a first electrode of the fourth transistor is connected to the low potential input terminal, and a second electrode of the fourth transistor is connected to the first point.
in an embodiment, in the display panel provided in the embodiment of the present invention, the second pull-down sustain circuit further includes a fifth transistor, a gate of the fifth transistor is connected to the second point, a first electrode of the fifth transistor is connected to the low potential input terminal, and a second electrode of the fifth transistor is connected to the first point.
in one embodiment, in the display panel provided in the embodiment of the present invention, the first pull-down sustain circuit includes a sixth transistor and a seventh transistor, a gate of the sixth transistor is connected to the second point, a first electrode of the sixth transistor is connected to the low potential input terminal, a second electrode of the sixth transistor is connected to the second stage signal terminal, a gate of the seventh transistor is connected to the second point, a first electrode of the seventh transistor is connected to the low potential input terminal, and a second electrode of the seventh transistor is connected to the second signal output terminal.
In an embodiment, in the display panel provided in the embodiment of the present invention, the pull-down circuit includes an eighth transistor and a third stage signal terminal, a gate of the eighth transistor is connected to the third stage signal terminal, a first electrode of the eighth transistor is connected to the low potential input terminal, and a second electrode of the eighth transistor is connected to the second signal output terminal.
In one embodiment, in the display panel provided in the embodiment of the present invention, the pull-up control circuit further includes a ninth transistor and a high potential input terminal, a gate of the ninth transistor is connected to the third clock signal input terminal, a first electrode of the ninth transistor is connected to the high potential input terminal, and a second electrode of the ninth transistor is connected to the first point.
In one embodiment, in the display panel provided in the embodiment of the present invention, the inverter includes a tenth transistor and an eleventh transistor, a gate of the tenth transistor is connected to the high potential input terminal, a first electrode of the tenth transistor is connected to the high potential input terminal, a second electrode of the tenth transistor is connected to the second point, a gate of the eleventh transistor is connected to the first point, a first electrode of the eleventh transistor is connected to the low potential input terminal, and a second electrode of the eleventh transistor is connected to the second point.
according to the above embodiment:
An embodiment of the present invention provides a gate driving circuit and a display panel, the gate driving circuit including a first pull-up circuit, a second pull-up circuit, a pull-down circuit, an inverter, a first pull-down sustain circuit, a second pull-down sustain circuit, and a pull-up sustain circuit, the second pull-up circuit being connected to the first pull-up circuit through a first point, the first point including a gate signal control node of the second pull-up circuit, the first pull-down sustain circuit being connected to the inverter through a second point, the second point including a gate signal control node of the first pull-down sustain circuit, the second pull-down sustain circuit including a fourth clock signal input terminal, the second pull-down sustain circuit being connected to the first point for lowering a potential of the first point under control of a fourth clock signal input at the fourth clock signal input terminal, the pull-up control circuit including a third clock signal input terminal, the pull-up control circuit is connected with the first point and used for raising the potential of the first point under the control of a third clock signal input by a third clock signal input end so as to reduce the potential of the second point; through setting up the control circuit that draws, make the control circuit that draws promote the electric potential of first point under the control of third clock signal, thereby make the electric potential of second point reduce a period in each cycle, thereby reduced the pressurized time of pull-down holding circuit's transistor, the stability of gate drive circuit has been increased, and the second pull-down holding circuit has guaranteed that first point is when the second point is in high potential, the electric potential of first point reduces, the current gate drive circuit of having solved has had the relatively poor technical problem of stability.
in summary, although the present invention has been described with reference to the preferred embodiments, the above-described preferred embodiments are not intended to limit the present invention, and those skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention, therefore, the scope of the present invention shall be determined by the appended claims.
Claims (10)
1. a gate drive circuit, comprising:
a first pull-up circuit;
A second pull-up circuit connected to the first pull-up circuit through a first point, the first point including a gate signal control node of the second pull-up circuit;
A pull-down circuit;
An inverter;
A first pull-down maintaining circuit connected to the inverter through a second point, the second point including a gate signal control node of the first pull-down maintaining circuit;
The second pull-down maintaining circuit comprises a fourth clock signal input end, is connected with the first point and is used for reducing the potential of the first point under the control of a fourth clock signal input by the fourth clock signal input end;
And the pull-up control circuit comprises a third clock signal input end, is connected with the first point and is used for raising the potential of the first point under the control of a third clock signal input by the third clock signal input end so as to reduce the potential of the second point.
2. A gate drive circuit as claimed in claim 1, wherein the first pull-up circuit comprises a first transistor, a first signal input terminal and a first stage signal terminal, a gate of the first transistor being connected to the first stage signal terminal, a first electrode of the first transistor being connected to the first signal input terminal, and a second electrode of the first transistor being connected to the first point.
3. The gate driver circuit of claim 2, further comprising a storage capacitor, a second stage signal terminal, a second signal output terminal, the second pull-up circuit includes a second transistor, a third transistor and a second clock signal input terminal, a gate of the second transistor is connected to the first point, a first electrode of the second transistor is connected to the second clock signal input terminal, a second electrode of the second transistor is connected to the second-stage signal terminal, a gate of the third transistor is connected to the first point, a first electrode of the third transistor is connected to the second clock signal input terminal, a second electrode of the third transistor is connected to the second signal output terminal, the storage capacitor is connected with the first point, and the storage capacitor is connected with the second-stage signal transmission end.
4. A gate drive circuit as claimed in claim 3, wherein the second pull-down sustain circuit further comprises a fourth transistor and a low potential input terminal, a gate of the fourth transistor being connected to the fourth clock signal input terminal, a first electrode of the fourth transistor being connected to the low potential input terminal, and a second electrode of the fourth transistor being connected to the first point.
5. the gate driving circuit according to claim 4, wherein the second pull-down holding circuit further includes a fifth transistor, a gate of the fifth transistor is connected to the second point, a first electrode of the fifth transistor is connected to the low potential input terminal, and a second electrode of the fifth transistor is connected to the first point.
6. The gate driver circuit according to claim 5, wherein the first pull-down holding circuit includes a sixth transistor and a seventh transistor, a gate of the sixth transistor is connected to the second point, a first electrode of the sixth transistor is connected to the low potential input terminal, a second electrode of the sixth transistor is connected to the second stage signal terminal, a gate of the seventh transistor is connected to the second point, a first electrode of the seventh transistor is connected to the low potential input terminal, and a second electrode of the seventh transistor is connected to the second signal output terminal.
7. the gate driving circuit according to claim 6, wherein the pull-down circuit comprises an eighth transistor and a third stage signal terminal, a gate of the eighth transistor is connected to the third stage signal terminal, a first electrode of the eighth transistor is connected to the low potential input terminal, and a second electrode of the eighth transistor is connected to the second signal output terminal.
8. The gate drive circuit of claim 7, wherein the pull-up control circuit further comprises a ninth transistor and a high potential input, a gate of the ninth transistor being connected to the third clock signal input, a first electrode of the ninth transistor being connected to the high potential input, and a second electrode of the ninth transistor being connected to the first point.
9. The gate driver circuit according to claim 8, wherein the inverter includes a tenth transistor and an eleventh transistor, a gate of the tenth transistor is connected to the high potential input terminal, a first electrode of the tenth transistor is connected to the high potential input terminal, a second electrode of the tenth transistor is connected to the second point, a gate of the eleventh transistor is connected to the first point, a first electrode of the eleventh transistor is connected to the low potential input terminal, and a second electrode of the eleventh transistor is connected to the second point.
10. A display panel comprising the gate driver circuit according to any one of claims 1 to 9.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910743576.XA CN110570800A (en) | 2019-08-13 | 2019-08-13 | Gate drive circuit and display panel |
| PCT/CN2019/113048 WO2021027067A1 (en) | 2019-08-13 | 2019-10-24 | Gate drive circuit and display panel |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201910743576.XA CN110570800A (en) | 2019-08-13 | 2019-08-13 | Gate drive circuit and display panel |
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| CN201910743576.XA Pending CN110570800A (en) | 2019-08-13 | 2019-08-13 | Gate drive circuit and display panel |
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| WO (1) | WO2021027067A1 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111681590A (en) * | 2020-06-24 | 2020-09-18 | 武汉华星光电技术有限公司 | Display driving circuit |
| WO2021168999A1 (en) * | 2020-02-26 | 2021-09-02 | 深圳市华星光电半导体显示技术有限公司 | Gate driving circuit and display panel |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20110002437A1 (en) * | 2009-07-01 | 2011-01-06 | Au Optronics Corp. | Shift registers |
| CN103426414A (en) * | 2013-07-16 | 2013-12-04 | 北京京东方光电科技有限公司 | Shifting register unit and driving method thereof, gate driving circuit and display device |
| CN103559868A (en) * | 2013-10-12 | 2014-02-05 | 深圳市华星光电技术有限公司 | Grid drive circuit and array substrate and display panel thereof |
| CN104091577A (en) * | 2014-07-15 | 2014-10-08 | 深圳市华星光电技术有限公司 | Gate drive circuit applied to 2D-3D signal setting |
| CN106486080A (en) * | 2016-12-30 | 2017-03-08 | 深圳市华星光电技术有限公司 | A kind of gate driver circuit for realizing GOA ultra-narrow frame |
| CN110111743A (en) * | 2019-05-07 | 2019-08-09 | 深圳市华星光电半导体显示技术有限公司 | GOA circuit and display panel |
| US20200090570A1 (en) * | 2016-06-24 | 2020-03-19 | Boe Technology Group Co., Ltd. | Shift register circuit, driving method, gate driving circuit and display device |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI373019B (en) * | 2007-05-09 | 2012-09-21 | Chunghwa Picture Tubes Ltd | Shift register and shift register apparatus therein |
| CN105355187B (en) * | 2015-12-22 | 2018-03-06 | 武汉华星光电技术有限公司 | GOA circuits based on LTPS semiconductor thin-film transistors |
| CN105976775B (en) * | 2016-05-18 | 2019-01-15 | 武汉华星光电技术有限公司 | GOA circuit based on LTPS semiconductor thin-film transistor |
| CN106098003B (en) * | 2016-08-08 | 2019-01-22 | 武汉华星光电技术有限公司 | GOA circuit |
| CN106531117B (en) * | 2017-01-05 | 2019-03-15 | 京东方科技集团股份有限公司 | Shift register, its driving method, grid integrated drive electronics and display device |
| CN108172181A (en) * | 2017-12-21 | 2018-06-15 | 深圳市华星光电技术有限公司 | A kind of GOA circuits and liquid crystal display panel |
-
2019
- 2019-08-13 CN CN201910743576.XA patent/CN110570800A/en active Pending
- 2019-10-24 WO PCT/CN2019/113048 patent/WO2021027067A1/en active Application Filing
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20110002437A1 (en) * | 2009-07-01 | 2011-01-06 | Au Optronics Corp. | Shift registers |
| CN103426414A (en) * | 2013-07-16 | 2013-12-04 | 北京京东方光电科技有限公司 | Shifting register unit and driving method thereof, gate driving circuit and display device |
| CN103559868A (en) * | 2013-10-12 | 2014-02-05 | 深圳市华星光电技术有限公司 | Grid drive circuit and array substrate and display panel thereof |
| CN104091577A (en) * | 2014-07-15 | 2014-10-08 | 深圳市华星光电技术有限公司 | Gate drive circuit applied to 2D-3D signal setting |
| US20200090570A1 (en) * | 2016-06-24 | 2020-03-19 | Boe Technology Group Co., Ltd. | Shift register circuit, driving method, gate driving circuit and display device |
| CN106486080A (en) * | 2016-12-30 | 2017-03-08 | 深圳市华星光电技术有限公司 | A kind of gate driver circuit for realizing GOA ultra-narrow frame |
| CN110111743A (en) * | 2019-05-07 | 2019-08-09 | 深圳市华星光电半导体显示技术有限公司 | GOA circuit and display panel |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2021168999A1 (en) * | 2020-02-26 | 2021-09-02 | 深圳市华星光电半导体显示技术有限公司 | Gate driving circuit and display panel |
| US11315460B1 (en) | 2020-02-26 | 2022-04-26 | Shenzhen China Star Optoelectronics Semiconductor Display Technology Co., Ltd. | Gate electrode driving circuit and display panel |
| CN111681590A (en) * | 2020-06-24 | 2020-09-18 | 武汉华星光电技术有限公司 | Display driving circuit |
| CN111681590B (en) * | 2020-06-24 | 2023-04-07 | 武汉华星光电技术有限公司 | Display driving circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| WO2021027067A1 (en) | 2021-02-18 |
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