CN111680037A - Dynamic data time scale obtaining method and device - Google Patents
Dynamic data time scale obtaining method and device Download PDFInfo
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- CN111680037A CN111680037A CN202010407945.0A CN202010407945A CN111680037A CN 111680037 A CN111680037 A CN 111680037A CN 202010407945 A CN202010407945 A CN 202010407945A CN 111680037 A CN111680037 A CN 111680037A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F16/00—Information retrieval; Database structures therefor; File system structures therefor
- G06F16/20—Information retrieval; Database structures therefor; File system structures therefor of structured data, e.g. relational data
- G06F16/22—Indexing; Data structures therefor; Storage structures
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F16/00—Information retrieval; Database structures therefor; File system structures therefor
- G06F16/20—Information retrieval; Database structures therefor; File system structures therefor of structured data, e.g. relational data
- G06F16/24—Querying
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- G06F16/2458—Special types of queries, e.g. statistical queries, fuzzy queries or distributed queries
- G06F16/2477—Temporal data queries
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
- H02J4/00—Circuit arrangements for mains or distribution networks not specified as ac or dc
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
- H02J2203/00—Indexing scheme relating to details of circuit arrangements for AC mains or AC distribution networks
- H02J2203/20—Simulating, e g planning, reliability check, modelling or computer assisted design [CAD]
Abstract
The invention discloses a method and a device for acquiring dynamic data time marks, wherein the method comprises the following steps: acquiring time data of a process layer and a device; judging whether the time difference value of the first millisecond bit data of the device time data and the second millisecond bit data of the process layer time data is smaller than a preset time length or not; when the time difference value between the first millisecond bit and the second millisecond bit is smaller than the preset time length, inputting the second bit data and the first millisecond bit data of the device time data into the protocol structure of the dynamic data time scale; and when the time difference is greater than or equal to the preset time length, correcting the second-bit data, and inputting the corrected second-bit data and the first millisecond-bit data into the protocol structure of the dynamic data time scale. The millisecond bit data of the device time data and the millisecond bit of the process layer are compared to judge whether the error value of the millisecond bit data and the millisecond bit data is smaller than the preset value or not so as to determine the specific numerical value of the dynamic data time scale of the synchronous phasor measurement device, and the problem of second bit jump errors of the dynamic data uploading time scale is solved.
Description
Technical Field
The invention relates to the technical field of power grid equipment, in particular to a method and a device for acquiring dynamic data time scales.
Background
The dynamic data recording and analyzing function of the synchronous phasor measuring device is widely applicable to places such as transformer substations and the like, is an important means for monitoring and analyzing dynamic characteristics of large power grids and new energy power generation, and plays an important role in safe operation of the current AC/DC large power grids. The time scale of the dynamic data is an important means for engineers to search and analyze the cause of the fault, so the time scale of the dynamic data must be effective and accurate.
The synchronous phasor measurement device dynamic data time scale needs to be formed by combining process layer time and device time. The millisecond bit in the dynamic data time mark comes from the sampling serial number of the process layer, but because the SV message of the process layer can not transmit other information related to time, the second bit in the dynamic data time mark is read from the device clock.
From the start of the dynamic data computation task to the end of the task, the sample pointer and sample sequence number are locked, i.e. the process level time is locked. At this time, the device clock is still in normal operation, so that when the dynamic data framing time is calibrated, the millisecond bit from the process layer is the calculation time of the dynamic data, and the second bit from the device clock is the current time. Combining milliseconds of process layer time and seconds of device time can create errors in which the two times are not synchronized.
Disclosure of Invention
The embodiment of the invention aims to provide a method and a device for acquiring a dynamic data time mark, wherein millisecond bit data of device time data is compared with millisecond bit data of a process layer, whether an error value of the millisecond bit data and the millisecond bit data is smaller than a preset value is judged, so that a specific numerical value of the dynamic data time mark of the device is determined, and the technical problem of second bit jump error of an uploading time mark of dynamic data is solved.
In order to solve the foregoing technical problem, a first aspect of an embodiment of the present invention provides a dynamic data time scale obtaining method, including: acquiring time data of a process layer and a device;
judging whether the time difference value of the first millisecond bit data of the device time data and the second millisecond bit data of the process layer time data is smaller than a preset time length or not;
when the time difference value between the first millisecond bit and the second millisecond bit is smaller than the preset time length, inputting second bit data of the device time data and the first millisecond bit data into a protocol structure of a dynamic data time scale;
and when the time difference is greater than or equal to the preset time length, correcting the second-bit data, and inputting the corrected second-bit data and the first millisecond-bit data into the protocol structure of the dynamic data time scale.
Further, the modifying the second bit time data includes:
adding 1 to the value of the second-millisecond time data when the first millisecond bit is greater than the second millisecond bit;
subtracting 1 from the value of the second-millisecond time data when the first-millisecond bit is less than the second-millisecond bit.
Further, before acquiring the time data of the process layer and the device, the method further includes:
judging whether the process layer sampling is interrupted;
when the process layer sampling is interrupted, acquiring the device time data and inputting the second bit data and the first millisecond bit data into a protocol structure of the dynamic data time scale;
acquiring time data of the process layer and the device when the process layer sampling is not interrupted.
Further, before acquiring the time data of the process layer and the device, the method further includes:
judging whether the device is powered on for the first time;
when the device is powered on for the first time, acquiring time data of the device and inputting the second bit data and the first millisecond bit data into a protocol structure of the dynamic data time scale;
and when the device is not powered on for the first time, acquiring time data of the process layer and the device.
Further, before acquiring the time data of the process layer and the device, the method further includes:
judging whether the device is in an out-of-step state;
and when the device is in an out-of-step state, adding the backup time by a second preset time length and then inputting the protocol structure of the dynamic data time scale.
Further, the acquiring time data of the process layer includes:
obtaining SV sampling sequence numbers of the process layers;
rounding the SV sampling sequence number forward by taking a preset numerical value as a unit to obtain the nearest SV sampling integer sequence number;
and obtaining the first millisecond bit data of the process layer time data according to the latest SV sampling integer serial number.
Further, before acquiring the time data of the process layer and the device, the method further includes:
obtaining SV sampling sequence numbers of the process layers;
judging whether the SV sampling sequence number of the process layer is in a first preset value range or not;
when the SV sampling sequence number of the process layer is in the first preset numerical range, inputting the second bit data and the first millisecond bit data of the device time data into a protocol structure of a dynamic data time scale;
and when the SV sampling sequence number of the process layer is not in the first preset value range, judging whether the difference value of the first millisecond bit data of the device time data and the second millisecond bit data of the process layer time data is less than a preset time length.
Accordingly, a second aspect of the embodiments of the present invention provides a dynamic data timestamp obtaining apparatus, including: the device comprises an acquisition module, a judgment module and a control module;
the acquisition module is used for acquiring time data of a process layer and a device;
the judging module is used for judging whether the time difference value of the first millisecond bit data of the device time data and the second millisecond bit data of the process layer time data is smaller than the preset time length or not;
the control module is used for inputting the second-millisecond data and the first-millisecond data of the device time data into the protocol structure of the dynamic data time scale when the time difference value of the first-millisecond bit and the second-millisecond bit is smaller than the preset time length;
and the control module is also used for correcting the second-bit data when the time difference value is greater than or equal to the preset time length, and inputting the corrected second-bit data and the first millisecond-bit data into a protocol structure of the dynamic data time scale.
A third aspect of an embodiment of the present invention provides an electronic device, including: at least one processor; and a memory coupled to the at least one processor; wherein the memory stores instructions executable by the one processor to cause the at least one processor to perform any of the above dynamic data time stamp acquisition methods.
A fourth aspect of the embodiments of the present invention provides a computer-readable storage medium having stored thereon computer instructions, which when executed by a processor, implement any of the above-mentioned methods for obtaining a dynamic data timestamp.
The technical scheme of the embodiment of the invention has the following beneficial technical effects:
whether the error value of the millisecond bit data of the device time data is smaller than the preset value or not is judged by comparing the millisecond bit data of the device time data with the millisecond bit of the process layer, so that the specific numerical value of the dynamic data time scale of the synchronous phasor measuring device is determined, the technical problem of second bit jump errors occurring in the dynamic data uploading time scale is solved, the technical problem of the synchronous phasor measuring device in the initial power-on, sampling terminal and out-of-step state is also solved, the accuracy of the dynamic data time scale of the synchronous vector measuring device is improved, and the running safety of the alternating current and direct current power grid is improved.
Drawings
Fig. 1 is a flowchart of a dynamic data timestamp acquisition method according to an embodiment of the present invention;
FIG. 2 is a block diagram of an apparatus for obtaining dynamic data timestamp according to an embodiment of the present invention;
FIG. 3 is a block diagram of an acquisition module provided by an embodiment of the present invention;
FIG. 4 is a block diagram of a sampling interrupt determination module according to an embodiment of the present invention;
fig. 5 is a block diagram of an initial power-on determining module according to an embodiment of the present invention;
FIG. 6 is a block diagram of an out-of-synchronization status determining module according to an embodiment of the present invention;
fig. 7 is a block diagram of an SV sampling sequence number determination module according to an embodiment of the present invention.
Reference numerals:
1. an obtaining module 11, a first obtaining unit 12, a first calculating unit 13, a second calculating unit 2, a judging module 3, a control module 4, a sampling interruption judging module 41, a first judging unit 42, a first control unit 5, a first power-on judging module 51, a second judging unit 52, a second control unit 6, a step-out state judging module 61, a third judging unit 62, a third control unit 7, an SV sampling sequence number judging module 71, a second obtaining unit 72, a fourth judging unit 73, a fourth control unit,
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention will be described in further detail with reference to the accompanying drawings in conjunction with the following detailed description. It should be understood that the description is intended to be exemplary only, and is not intended to limit the scope of the present invention. Moreover, in the following description, descriptions of well-known structures and techniques are omitted so as to not unnecessarily obscure the concepts of the present invention.
FIG. 1 is a flowchart of a dynamic data timestamp acquisition method according to an embodiment of the present invention
Referring to fig. 1, an embodiment of the present invention provides a dynamic data timestamp obtaining method, including the following steps:
s200, acquiring time data of a process layer and a device.
S400, judging whether the time difference value of the first millisecond bit data of the device time data and the second millisecond bit data of the process layer time data is smaller than a preset time length.
S600, when the time difference value between the first millisecond bit and the second millisecond bit is smaller than the preset time length, the second-bit data and the first millisecond-bit data of the device time data are input into the protocol structure of the dynamic data time scale.
And S800, when the time difference is greater than or equal to the preset time length, correcting the second-bit data, and inputting the corrected second-bit data and the first-millisecond bit data into a protocol structure of the dynamic data time scale.
In step S800, the dynamic data timestamp obtaining method modifies the second time data, which may include the following two cases:
and S810, when the first millisecond bit is larger than the second millisecond bit, adding 1 to the value of the second bit time data.
And S820, when the first millisecond bit is smaller than the second millisecond bit, subtracting 1 from the value of the second bit time data.
Before acquiring the time data of the process layer and the device, the dynamic data time scale acquisition method further comprises the following steps:
and S111, judging whether the process layer sampling is interrupted.
And S112, if the process layer sampling is interrupted, acquiring device time data and inputting the second-bit data and the first-millisecond-bit data into the reduction structure of the dynamic data time scale.
And S113, if the process layer sampling is not interrupted, acquiring the time data of the process layer and the device.
Before acquiring the time data of the process layer and the device, the dynamic data time scale acquisition method further comprises the following steps:
and S121, judging whether the device is powered on for the first time.
And S122, if the device is powered on for the first time, acquiring device time data and inputting the second-bit data and the first-millisecond-bit data into a reduction structure of the dynamic data time scale.
And S123, if the device is not powered on for the first time, acquiring time data of the process layer and the device.
Before acquiring the time data of the process layer and the device, the dynamic data time scale acquisition method further comprises the following steps:
s131, judging whether the device is in the out-of-step state.
And S132, if the device is in the out-of-step state, adding the backup time by a second preset time length and then inputting the protocol structure of the dynamic data time scale.
S133, if the device is in the synchronous state, the step S200 is executed.
In a specific implementation manner of the embodiment of the present invention, the acquiring the time data of the process layer may include the following steps:
s210, SV sampling sequence numbers of the process layers are obtained.
And S220, rounding the SV sampling sequence number forward by taking a preset numerical value as a unit to obtain the nearest SV sampling integer sequence number.
And S230, obtaining the first millisecond bit data of the process layer time data according to the latest SV sampling integer serial number.
In an implementation manner of the embodiment of the present invention, before acquiring time data of a process layer and a device, the dynamic data timestamp acquisition method further includes:
and S141, acquiring the SV sampling sequence number of the process layer.
And S142, judging whether the SV sampling sequence number of the process layer is in a first preset value range.
And S143, if the SV sampling sequence number of the process layer is in a first preset value range, inputting the second bit data and the first millisecond bit data of the device time data into a protocol structure of the dynamic data time scale.
S144, if the SV sampling sequence number of the process layer is not within the first preset value range, execute step S400.
Fig. 2 is a block diagram of an apparatus for acquiring a dynamic data timestamp according to an embodiment of the present invention.
Referring to fig. 2, a second aspect of the present invention provides a dynamic data timestamp obtaining apparatus, including: the device comprises an acquisition module, a judgment module and a control module. The acquisition module is used for acquiring time data of a process layer and a device; the judging module is used for judging whether the time difference value of the first millisecond bit data of the device time data and the second millisecond bit data of the process layer time data is smaller than the preset time length or not; the control module is used for inputting the second-millisecond data and the first-millisecond data of the device time data into the protocol structure of the dynamic data time scale when the time difference value of the first-millisecond bit and the second-millisecond bit is smaller than the preset time length; the control module is also used for correcting the second-bit data when the time difference value is larger than or equal to the preset time length, and inputting the corrected second-bit data and the first millisecond-bit data into a protocol structure of the dynamic data time scale.
Specifically, the step of correcting the second-bit data by the control module includes: when the first millisecond bit is larger than the second millisecond bit, adding 1 to the numerical value of the second bit time data; when the first millisecond bit is less than the second millisecond bit, the value of the second bit time data is decremented by 1.
Fig. 3 is a block diagram of an acquisition module according to an embodiment of the present invention.
Referring to fig. 3, in an embodiment of the present invention, the obtaining module includes: the device comprises a first acquisition unit, a first calculation unit and a second calculation unit. The first acquisition unit is used for acquiring SV sampling serial numbers of a process layer; the first calculation unit is used for rounding the SV sampling sequence number forward by taking a preset numerical value as a unit to obtain the nearest SV sampling integer sequence number; the second calculation unit obtains the first millisecond bit data of the process layer time data according to the nearest SV sampling integer sequence number.
Fig. 4 is a block diagram of a sampling interrupt determining module according to an embodiment of the present invention.
Referring to fig. 4, optionally, the dynamic data timestamp obtaining apparatus further includes: and a sampling interruption judgment module. The sampling interruption judgment module comprises: the device comprises a first judging unit and a first control unit. The first judgment unit is used for judging whether the process layer sampling is interrupted or not; the first control unit is used for acquiring device time data when process layer sampling is interrupted and inputting second-bit data and first-millisecond-bit data into a reduction structure of a dynamic data time scale.
Fig. 5 is a block diagram of an initial power-on determining module according to an embodiment of the present invention.
Referring to fig. 5, optionally, the dynamic data timestamp obtaining apparatus further includes: and a primary power-on judging module. The initial power-up judging module comprises: a second judging unit and a second control unit. The second judging unit is used for judging whether the device is powered on for the first time; the second control unit is used for acquiring device time data when the device is powered on for the first time and inputting second bit data and first millisecond bit data into a protocol structure of a dynamic data time scale; the second control unit is further configured to obtain time data for the process layer and the device when the device is not initially powered on.
Fig. 6 is a block diagram of an out-of-synchronization status determining module according to an embodiment of the present invention.
Referring to fig. 6, optionally, the dynamic data timestamp obtaining apparatus further includes: and an out-of-step state judgment module. The step-out state judging module comprises: a third judging unit and a third control unit. The third judging unit is used for judging whether the device is powered on for the first time; the third control unit is used for acquiring time data of the device when the device is powered on for the first time and inputting second bit data and first millisecond bit data into a protocol structure of a dynamic data time scale; the third control unit is further configured to obtain time data for the process layer and the device when the device is not initially powered up.
Fig. 7 is a block diagram of an SV sampling sequence number determination module according to an embodiment of the present invention.
Referring to fig. 7, optionally, the dynamic data timestamp obtaining apparatus further includes: and an SV sampling sequence number judging module. The SV sampling sequence number judging module comprises: the device comprises a second acquisition unit, a fourth judgment unit and a fourth control unit. The second acquisition unit is used for acquiring the SV sampling serial number of the process layer; the fourth judging unit judges whether the SV sampling sequence number of the process layer is in a first preset value range or not; the fourth control unit is used for inputting the second-bit data and the first millisecond-bit data of the device time data into the protocol structure of the dynamic data time scale when the SV sampling sequence number of the process layer is in a first preset numerical range; the fourth control unit is further configured to determine whether a difference between first millisecond bit data of the device time data and second millisecond bit data of the process layer time data is less than a preset duration when the SV sampling sequence number of the process layer is not within the first preset value range.
The dynamic data time mark acquisition device compares the millisecond bit data of the device time data with the millisecond bit of the process layer to judge whether the error value of the millisecond bit data and the millisecond bit data of the process layer is smaller than the preset value or not so as to determine the specific numerical value of the dynamic data time mark of the synchronous phasor measurement device, solve the technical problem of second bit jump error of the dynamic data uploading time mark, solve the technical problem of the synchronous phasor measurement device in the initial power-on, sampling terminal and out-of-step states, improve the accuracy of the dynamic data time mark of the synchronous vector measurement device and improve the running safety of the alternating current and direct current power grid.
A third aspect of an embodiment of the present invention provides an electronic device, including: at least one processor; and a memory coupled to the at least one processor; the memory stores instructions executable by the processor, and the instructions are executed by the processor to cause at least one processor to perform any one of the dynamic data time stamp obtaining methods described above.
A fourth aspect of the embodiments of the present invention provides a computer-readable storage medium, on which computer instructions are stored, and the computer instructions, when executed by a processor, implement any of the above dynamic data time stamp obtaining methods.
The embodiment of the invention aims to protect a method and a device for acquiring a dynamic data time mark, wherein the method comprises the following steps: acquiring time data of a process layer and a device; judging whether the time difference value of the first millisecond bit data of the device time data and the second millisecond bit data of the process layer time data is smaller than a preset time length or not; when the time difference value between the first millisecond bit and the second millisecond bit is smaller than the preset time length, inputting the second bit data and the first millisecond bit data of the device time data into the protocol structure of the dynamic data time scale; and when the time difference is greater than or equal to the preset time length, correcting the second-bit data, and inputting the corrected second-bit data and the first millisecond-bit data into the protocol structure of the dynamic data time scale. The technical scheme has the following effects:
whether the error value of the millisecond bit data of the device time data is smaller than the preset value or not is judged by comparing the millisecond bit data of the device time data with the millisecond bit of the process layer, so that the specific numerical value of the dynamic data time scale of the synchronous phasor measuring device is determined, the technical problem of second bit jump errors occurring in the dynamic data uploading time scale is solved, the technical problem of the synchronous phasor measuring device in the initial power-on, sampling terminal and out-of-step state is also solved, the accuracy of the dynamic data time scale of the synchronous vector measuring device is improved, and the running safety of the alternating current and direct current power grid is improved.
It is to be understood that the above-described embodiments of the present invention are merely illustrative of or explaining the principles of the invention and are not to be construed as limiting the invention. Therefore, any modification, equivalent replacement, improvement and the like made without departing from the spirit and scope of the present invention should be included in the protection scope of the present invention. Further, it is intended that the appended claims cover all such variations and modifications as fall within the scope and boundaries of the appended claims or the equivalents of such scope and boundaries.
Claims (10)
1. A dynamic data time scale acquisition method is characterized by comprising the following steps:
acquiring time data of a process layer and a device;
judging whether the time difference value of the first millisecond bit data of the device time data and the second millisecond bit data of the process layer time data is smaller than a preset time length or not;
when the time difference value between the first millisecond bit and the second millisecond bit is smaller than the preset time length, inputting second bit data of the device time data and the first millisecond bit data into a protocol structure of a dynamic data time scale;
and when the time difference is greater than or equal to the preset time length, correcting the second-bit data, and inputting the corrected second-bit data and the first millisecond-bit data into the protocol structure of the dynamic data time scale.
2. The dynamic data time stamp obtaining method according to claim 1, wherein said modifying the second bit time data comprises:
adding 1 to the value of the second-millisecond time data when the first millisecond bit is greater than the second millisecond bit;
subtracting 1 from the value of the second-millisecond time data when the first-millisecond bit is less than the second-millisecond bit.
3. The dynamic data time stamp obtaining method according to claim 1, wherein before obtaining the time data of the process layer and the device, further comprising:
judging whether the process layer sampling is interrupted;
when the process layer sampling is interrupted, acquiring the device time data and inputting the second bit data and the first millisecond bit data into a protocol structure of the dynamic data time scale;
acquiring time data of the process layer and the device when the process layer sampling is not interrupted.
4. The dynamic data time stamp obtaining method according to claim 3, wherein before obtaining the time data of the process layer and the device, further comprising:
judging whether the device is powered on for the first time;
when the device is powered on for the first time, acquiring time data of the device and inputting the second bit data and the first millisecond bit data into a protocol structure of the dynamic data time scale;
and when the device is not powered on for the first time, acquiring time data of the process layer and the device.
5. The dynamic data time stamp obtaining method according to claim 3, wherein before obtaining the time data of the process layer and the device, further comprising:
judging whether the device is in an out-of-step state;
and when the device is in an out-of-step state, adding the backup time by a second preset time length and then inputting the protocol structure of the dynamic data time scale.
6. The dynamic data time stamp obtaining method according to claim 1, wherein the obtaining of the time data at the process level includes:
obtaining SV sampling sequence numbers of the process layers;
rounding the SV sampling sequence number forward by taking a preset numerical value as a unit to obtain the nearest SV sampling integer sequence number;
and obtaining the first millisecond bit data of the process layer time data according to the latest SV sampling integer serial number.
7. The dynamic data time stamp obtaining method according to claim 1, wherein before obtaining the time data of the process layer and the device, further comprising:
obtaining SV sampling sequence numbers of the process layers;
judging whether the SV sampling sequence number of the process layer is in a first preset value range or not;
when the SV sampling sequence number of the process layer is in the first preset numerical range, inputting the second bit data and the first millisecond bit data of the device time data into a protocol structure of a dynamic data time scale;
and when the SV sampling sequence number of the process layer is not in the first preset value range, judging whether the difference value of the first millisecond bit data of the device time data and the second millisecond bit data of the process layer time data is less than a preset time length.
8. A dynamic data time stamp obtaining apparatus, comprising: the device comprises an acquisition module, a judgment module and a control module;
the acquisition module is used for acquiring time data of a process layer and a device;
the judging module is used for judging whether the time difference value of the first millisecond bit data of the device time data and the second millisecond bit data of the process layer time data is smaller than the preset time length or not;
the control module is used for inputting the second-millisecond data and the first-millisecond data of the device time data into the protocol structure of the dynamic data time scale when the time difference value of the first-millisecond bit and the second-millisecond bit is smaller than the preset time length;
and the control module is also used for correcting the second-bit data when the time difference value is greater than or equal to the preset time length, and inputting the corrected second-bit data and the first millisecond-bit data into a protocol structure of the dynamic data time scale.
9. An electronic device, comprising: at least one processor; and a memory coupled to the at least one processor; wherein the memory stores instructions executable by the one processor to cause the at least one processor to perform the dynamic data time stamp acquisition method of any one of claims 1-7.
10. A computer-readable storage medium having stored thereon computer instructions, which when executed by a processor, implement the dynamic data time stamp acquisition method of any of claims 1-7.
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| CN114089038A (en) * | 2021-11-16 | 2022-02-25 | 许昌许继软件技术有限公司 | Time scale second-bit jump processing method and system for dynamic data of synchrophasor measuring device |
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