CN111680001A

CN111680001A - Signal output control circuit in system-on-chip

Info

Publication number: CN111680001A
Application number: CN202010538403.7A
Authority: CN
Inventors: 不公告发明人
Original assignee: Individual
Current assignee: Individual
Priority date: 2020-06-13
Filing date: 2020-06-13
Publication date: 2020-09-18

Abstract

The invention discloses a signal output control circuit in a System On Chip (SOC), and introduces a signal output control mode designed for the SOC. The invention comprises code storage, a main control circuit, a clock and an output. By writing specific coded data in the chip in advance, the main control circuit can process the stored data read in sequence according to clock beats into a signal output sequence to be output to the chip pins, and the data read in each clock cycle can be converted into a specific level state to be output to the corresponding pins. The coded data format can be customized, respective serial data coding sequences can be output in parallel by multiple pins, and different coded data can represent different output level states in corresponding periods. Taking the current Microcontroller (MCU) product as an example, if the technology is incorporated therein, a completely new practical function can be defined for the application field of the microcontroller.

Description

Signal output control circuit in system-on-chip

Technical Field

The invention designs a signal output control mode for a System On Chip (SOC), and relates to a control circuit capable of generating specific signal excitation. A series of digital signal coding data are set through a register or a memory, and the control circuit can automatically and quickly read out the data according to the address sequence to perform specific logic processing and output the corresponding state to an external pin.

Background

With the widespread use of integrated circuits, various interfaces are required for connection, control, and communication between chips and between systems. The invention can design a special and flexible excitation signal group in a simple mode to drive a lower circuit. Conventional chip implementations typically design the corresponding Intellectual Property (IP) circuitry for a particular protocol or simulate implementation of a particular communication protocol through software programming. For hardware IP, the realization function aiming at a specific interface can be only realized, and the application of the functional interface cannot be expanded due to single target; for software-designed interface implementation, the overhead of a processor (CPU) is consumed on one hand, and the time overhead of instruction pipelining also results in a limited speed of output stimuli on the other hand. The scheme not only keeps the flexibility and the universality of software implementation in the aspect of generating the excitation signal, but also keeps the high-speed performance of hardware implementation and the effect of parallel execution with other main control circuits such as a CPU and the like.

The scheme has great flexibility and wide application range, and can realize functions which cannot be realized by software and hardware. For example, signal replication can be realized according to some specific stimuli collected by the logic analyzer, and the chip can prestore the collected data of the logic analyzer and then replicate similar stimuli through the control circuit. The timing sequence of any data signal, address signal and control signal on the communication interface can be changed by modifying the pre-stored data, and the timing sequence analysis, compatibility analysis and protocol analysis of the chip interface and the timing sequence attack on the lower chip can be realized.

The scheme has the advantages that the circuit is simple and easy to implement, the integration in the SOC chip can achieve good resource sharing, the configuration can be carried out by utilizing a clock source of the SOC and a universal memory space, and even the size of a self-defined coding space and the configuration in which section of specific storage interval can be supported by a control register.

Disclosure of Invention

The invention comprises a code storage part, a main control circuit part, a clock part and an output part, wherein the main control circuit and the output part are arranged in a system-on-chip, and the code storage part and the clock part can be arranged outside the system-on-chip or in the system-on-chip.

By writing specific coded data in a chip register or a memory in advance, the hardware main control circuit can be used as a bus master (master) to process the stored data sequentially read according to clock beats into a signal output sequence and output the signal output sequence to a chip pin, and the data read in each clock cycle can be converted into a specific level state and output on a corresponding output pin. The output coding data format can be customized, for example, multiple pins are supported to output respective serial data coding sequences in parallel, the output state of each clock cycle of each signal needs several bits to code, and the like. The pin level output control represented by the encoded data may include states of strong 0, weak 0, strong 1, weak 1, and high impedance.

Claims

1. A control circuit that can generate specific signal stimuli.

2. The system-on-chip multi-functional chip comprises a coding storage part, a main control circuit part, a clock part and an output part, wherein the main control circuit part and the output part are arranged inside the system-on-chip, and the coding storage part and the clock part can be arranged outside the system-on-chip or inside the system-on-chip.

3. The control circuit of claim 2, wherein the master control circuit reads the encoded sequence, decodes the read data with a clock, and generates the output sequence of specific levels to the corresponding pins.

4. The control circuit of claim 2, wherein there is a correspondence between the encoded data and the output level state.