CN111679714A - Cross-chip signal synchronization method and device and chip - Google Patents
Cross-chip signal synchronization method and device and chip Download PDFInfo
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Abstract
The application belongs to the technical field of signal synchronization, and provides a cross-chip signal synchronization method, a device and a chip, wherein a first chip is used as an execution main body, and the method comprises the following steps: sending a synchronous signal to a second chip according to preset time so that the second chip records a phase count value corresponding to a clock signal of the second chip when receiving the synchronous signal; the preset time is a phase counting value corresponding to a clock signal of the first chip when the synchronous signal is sent; acquiring the synchronous signal output to a first chip pin and feeding back the synchronous signal to the first chip; and sending the phase counting value of the first chip and the preset time when the fed-back synchronous signal is received to the second chip so that the second chip corrects the clock signal of the second chip according to the phase counting value of the first chip, the preset time and the recorded phase counting value when the fed-back synchronous signal is received. The embodiment of the application solves the problem of delay introduced when the chip signal is corrected.
Description
Technical Field
The invention relates to the technical field of signal synchronization, in particular to a cross-chip signal synchronization method, a cross-chip signal synchronization device and a chip.
Background
The intelligent machine can complete various complicated works, and is usually because a plurality of working chips are arranged inside the intelligent machine. And a plurality of chips with the same model can be arranged for simultaneously operating for improving the performance of the intelligent machine. In order to implement unified operation of a plurality of chips with the same model, it is necessary to ensure clock signal synchronization between each chip. However, in reality, there are factors such as uncertain circuit delay caused by external capacitance in the internal working circuit of a chip, inconsistent start-up time of different chips, and the like, so that the internal clocks of two chips or a plurality of chips are asynchronous to each other.
In the prior art, a synchronous correction method for clock signals among chips is to perform clock synchronization and edge detection on chips to be corrected according to synchronous signals sent by a standard chip, but the synchronous signals generate delay when being transmitted by an internal working circuit of the chips, and uncertain delay is introduced in the process that the synchronous signals are sent from the standard chip to be corrected and received by the chips to be corrected by performing clock correction through the method, so that the chips cannot be accurately synchronized.
Disclosure of Invention
In view of this, embodiments of the present invention provide a method, an apparatus, and a chip for cross-chip signal synchronization, so as to solve the problem of introducing delay when correcting a chip clock signal.
A first aspect of an embodiment of the present invention provides a method for cross-chip signal synchronization, which is performed by a first chip, and includes:
sending a synchronous signal to a second chip according to preset time so that the second chip records a phase count value corresponding to a clock signal of the second chip when receiving the synchronous signal; the preset time is a phase count value corresponding to a clock signal of the first chip when the synchronous signal is sent; the first chip is the same as the second chip;
acquiring the synchronous signal output to the pin of the first chip and feeding back the synchronous signal to the first chip;
and sending the phase counting value of the first chip and the preset time when the feedback synchronization signal is received to the second chip so that the second chip corrects the clock signal of the second chip according to the phase counting value of the first chip, the preset time and the phase counting value recorded by the second chip when the feedback synchronization signal is received.
In one embodiment, after the synchronization signal output to the first chip pin is obtained and fed back to the first chip, the method further includes:
and calculating the phase difference of the chip receiving signals according to the phase counting value of the first chip when the fed-back synchronous signal is received and the preset time.
In an implementation example, the sending the phase count value of the first chip and the predetermined time when the feedback synchronization signal is received to the second chip to enable the second chip to correct the clock signal of the second chip according to the phase count value of the first chip when the feedback synchronization signal is received, the predetermined time and the phase count value recorded by the second chip includes:
and sending the phase difference to the second chip, and sending the phase counting value of the first chip when the phase difference is in the preset time or the fed back synchronous signal is received to the second chip, so that the second chip corrects the clock signal of the second chip according to the phase difference, the phase counting value recorded by the second chip, the phase counting value of the first chip when the phase difference is in the preset time or the fed back synchronous signal is received.
In an implementation example, before sending a synchronization signal to a second chip according to a predetermined time to enable the second chip to record a phase count value corresponding to a clock signal of the second chip when receiving the synchronization signal, the method further includes:
and determining a preset time for sending the synchronous signal to the second chip, and sending the preset time to the second chip.
In an implementation example, the sending a synchronization signal to a second chip according to a predetermined time to enable the second chip to record a phase count value corresponding to a clock signal of the second chip when receiving the synchronization signal includes:
and sending a synchronous signal to a second chip according to preset time, so that the second chip updates a phase count value corresponding to a clock signal of the second chip to be the preset time when receiving the synchronous signal.
In an implementation example, the sending the phase count value of the first chip and the predetermined time when the feedback synchronization signal is received to the second chip to enable the second chip to correct the clock signal of the second chip according to the phase count value of the first chip when the feedback synchronization signal is received, the predetermined time and the phase count value recorded by the second chip includes:
and sending the phase difference to the second chip so that the second chip corrects the phase of the current clock signal of the second chip according to the phase difference.
In an implementation example, the sending the phase count value of the first chip and the predetermined time when the feedback synchronization signal is received to the second chip to enable the second chip to correct the clock signal of the second chip according to the phase count value of the first chip when the feedback synchronization signal is received, the predetermined time and the phase count value recorded by the second chip includes:
sending a synchronous signal to a second pin of the second chip through a first pin of the first chip according to preset time; wherein the first pin and the second pin are the same pin of the chip.
In one example of implementation, the method includes:
and acquiring a phase count value of the first chip when the fed-back synchronous signal is received through a signal detection circuit.
In one embodiment, the calculating a phase difference of chip receiving signals according to the phase count value of the first chip when the fed-back synchronization signal is received and the predetermined time includes:
reading a phase count value corresponding to a clock signal of the first chip when the fed-back synchronous signal is detected through the signal detection circuit;
and calculating the phase difference of the chip receiving signals according to the read phase counting value and the preset time.
A second aspect of an embodiment of the present invention provides a device for cross-chip signal synchronization, including:
the synchronous signal sending module is used for sending a synchronous signal to a second chip according to preset time so that the second chip records a phase counting value corresponding to a clock signal of the second chip when receiving the synchronous signal; the preset time is a phase count value corresponding to a clock signal of the first chip when the synchronous signal is sent; the first chip is the same as the second chip;
the synchronous signal feedback module is used for acquiring the synchronous signal output to the pin of the first chip and feeding back the synchronous signal to the first chip;
and the clock correction module is used for sending the phase counting value of the first chip and the preset time when the feedback synchronous signal is received to the second chip so that the second chip corrects the clock signal of the second chip according to the phase counting value of the first chip when the feedback synchronous signal is received, the preset time and the phase counting value recorded by the second chip.
A third aspect of an embodiment of the present invention provides a chip, including: memory, a processor and a computer program stored in the memory and executable on the processor, the processor implementing the method of cross-chip signal synchronization of the first aspect when executing the computer program.
According to the method, the device and the chip for cross-chip signal synchronization, provided by the embodiment of the invention, a first chip sends a synchronization signal to a second chip according to preset time, so that the second chip records a phase count value corresponding to a clock signal of the second chip when receiving the synchronization signal; the preset time is a phase count value corresponding to a clock signal of the first chip when the synchronous signal is sent; the first chip is the same as the second chip; acquiring the synchronous signal output to the pin of the first chip and feeding back the synchronous signal to the first chip; and sending the phase counting value of the first chip and the preset time when the feedback synchronization signal is received to the second chip so that the second chip corrects the clock signal of the second chip according to the phase counting value of the first chip, the preset time and the phase counting value recorded by the second chip when the feedback synchronization signal is received. The phase difference of the received signals of the chip can be calculated by the second chip according to the phase counting value corresponding to the clock signal of the first chip when the fed-back synchronous signal is received and the preset time by sending the phase counting value of the first chip when the fed-back synchronous signal is received and the preset time to the second chip, so that the time delay of the signals in the internal circuit of the chip is obtained. And the second chip can determine the clock asynchrony condition between the first chip and the second chip according to the preset time and the phase count value corresponding to the clock signal of the second chip when the synchronous signal is received, and eliminate the delay error according to the phase difference. And the second chip performs phase correction of the clock signal according to the phase difference, the preset time and the recorded phase counting value, so that the clock of the first chip and the clock of the second chip are accurately synchronized.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed for the embodiments or the prior art descriptions will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings without creative efforts.
Fig. 1 is a schematic flowchart of a cross-chip signal synchronization method according to an embodiment of the present invention;
FIG. 2 is a flowchart illustrating a cross-chip signal synchronization method according to a second embodiment of the present invention;
fig. 3 is a schematic flowchart of a method for cross-chip signal synchronization according to a third embodiment of the present invention;
fig. 4 is a schematic structural diagram of a device for synchronizing signals across chips according to a fourth embodiment of the present invention;
fig. 5 is a schematic structural diagram of a chip according to a fifth embodiment of the present invention.
Detailed Description
In order to make the technical solutions of the present invention better understood by those skilled in the art, the technical solutions in the embodiments of the present invention will be clearly described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some embodiments of the present invention, but not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The terms "comprises" and "comprising," and any variations thereof, in the description and claims of this invention and the above-described drawings are intended to cover non-exclusive inclusions. For example, a process, method, or system, article, or apparatus that comprises a list of steps or elements is not limited to only those steps or elements listed, but may alternatively include other steps or elements not listed, or inherent to such process, method, article, or apparatus. Furthermore, the terms "first," "second," and "third," etc. are used to distinguish between different objects and are not used to describe a particular order.
Example one
Fig. 1 is a schematic flowchart of a cross-chip signal synchronization method according to an embodiment of the present invention. The method can be executed by a device for synchronizing signals across chips, and the device can be a chip; in the embodiment of the present application, a first chip is taken as an execution subject, and the method specifically includes the following steps:
s110, sending a synchronous signal to a second chip according to preset time so that the second chip records a phase count value corresponding to a clock signal of the second chip when receiving the synchronous signal; the preset time is a phase counting value corresponding to a clock signal of the first chip when the synchronous signal is sent; the first chip is the same as the second chip;
because the existing clock correction process can introduce uncertain delay in the process of sending out the synchronous signal from the standard chip to receiving the synchronous signal by the chip to be corrected. In order to solve the problem, the synchronous signal sent by the standard chip can be fed back to the standard chip, so that the standard chip calculates the phase difference according to the clock signal when the fed-back synchronous signal is received, and uncertain delay is prevented from being introduced in the process that the synchronous signal is sent from the standard chip to the chip to be corrected to receive.
Specifically, no matter clock synchronization correction among a plurality of identical chips or clock synchronization correction among two identical chips, a specific process is to select one chip as a standard chip, and to send a synchronization signal to the chip to be corrected through the standard chip to complete synchronization correction of the chip to be corrected by taking a phase count value corresponding to a clock signal of the standard chip as a reference. In the present embodiment example, the first chip is taken as a standard chip, and the second chip is taken as a chip to be corrected; the first chip and the second chip can be chips with the same model and structure. Specifically, the frequency of the clock signal in the chip is controlled by the phase count value of the counter. The counter of a chip as a timer can manage a plurality of clock signals correspondingly, the phase count value of the timer is accumulated one by one from 0, each clock signal has a corresponding count turnover period, and the clock signal is turned over once when the phase count value in the timer meets the count turnover period of a certain clock signal. For example, it is assumed that a clock signal is defined in the chip, the clock signal is generated by a counter with a count value of at most 999 and the count inversion period is 500, when the count value is 0, the clock signal changes from 0 to 1, and when the count value is 500, the clock signal changes from 1 to 0. The clock signal output by the counter when the phase counting value of the counter is counted for one counting turnover period is turned over for one cycle period, the absolute frequency of the clock signal is determined by the speed of change of the counter value, if the counter is increased by 1 every 2 nanoseconds, the frequency of the clock signal is 0.5MHZ, and if the counter is increased by 1 every 1 nanosecond, the frequency of the clock signal is 1 MHZ.
When the clock correction is carried out on the second chip, the first chip sends a synchronous signal to the second chip according to preset time; the synchronous correction of the clock signals of the first chip and the second chip is actually the correction of the phase count values in the counters of the first chip and the second chip. The preset time is a phase counting value corresponding to the clock signal of the first chip. Specifically, after the first chip sends the synchronization signal to the second chip, the second chip may record a phase count value corresponding to a current clock signal of the second chip when receiving the synchronization signal.
In an implementation example, the specific process of sending the synchronization signal to the second chip according to the predetermined time to enable the second chip to record the phase count value corresponding to the clock signal of the second chip when receiving the synchronization signal may be: sending a synchronous signal to a second pin of the second chip through a first pin of the first chip according to preset time; wherein the first pin and the second pin are the same pin of the chip.
Specifically, since the predetermined time may be a phase count value corresponding to a preset clock signal, when the counter value of the first chip is the predetermined time, a synchronization signal is generated and sent to the second pin of the second chip through the first pin of the first chip; the second chip receives the synchronous signal through a second pin of the second chip.
S120, acquiring the synchronous signal output to the pin of the first chip and feeding back the synchronous signal to the first chip;
when the synchronous signal is output to the first chip pin from the inside of the first chip, the synchronous signal output to the first pin of the first chip can be obtained and fed back to the first chip. Specifically, after the synchronization signal output to the first pin of the first chip is obtained, the synchronization signal output to the first pin of the first chip may be fed back to the inside of the first chip through the first pin of the first chip. Optionally, the first pin of the first chip may be further connected to another pin of the first chip, and when the synchronization signal is output from the inside of the first chip to the first chip pin, the synchronization signal output to the first pin of the first chip may be obtained through another pin connected to the first pin, and the synchronization signal is fed back to the inside of the first chip through another pin connected to the first pin, in which case, the another pin of the first chip and the second pin of the second chip are the same pin of the chip.
S130, sending the phase counting value of the first chip and the preset time when the feedback synchronization signal is received to the second chip, so that the second chip corrects the clock signal of the second chip according to the phase counting value of the first chip when the feedback synchronization signal is received, the preset time and the phase counting value recorded by the second chip.
And when the first chip receives the fed-back synchronous signal, reading a phase count value corresponding to the clock signal of the first chip. In one implementation example, the phase count value of the first chip when the fed-back synchronization signal is received is obtained by an edge detection circuit, which is a signal detection circuit provided inside the first chip. And the signal detection circuit arranged in the chip is connected with the clock counter of the first chip. And when the signal detection circuit detects the inversion edge of the synchronous signal fed back to the first chip, reading the current phase count value from the clock counter of the first chip to obtain the phase count value of the first chip when the fed-back synchronous signal is received. Optionally, the first chip and the second chip operate using the same clock source. Since the synchronization signal is fed back to the first chip and undergoes two internal circuit transmissions of the chip, it is equivalent to the transmission of the synchronization signal from the internal circuit of the first chip to the internal circuit of the second chip.
After the first chip sends the synchronous signal to the second chip, the second chip can record a phase counting value corresponding to a current clock signal of the second chip when receiving the synchronous signal through a second pin of the second chip, so that after the phase counting value of the first chip and the preset time when the second chip receives the synchronous signal sent by the first chip and received by feedback, the second chip can calculate the phase difference of the received signal of the chip according to the phase counting value of the first chip and the preset time when receiving the synchronous signal sent by the first chip, and the clock asynchronization condition between the first chip and the second chip, namely the clock signal phase difference between the first chip and the second chip can be determined according to the preset time by combining the phase difference, the preset time and the recorded phase counting value; and time errors are excluded from the phase difference. The second chip can correct the current phase count value of the counter of the second chip by subtracting the phase difference according to the determined clock asynchronization condition, so that the phase count value of the counter of the second chip is consistent with the phase count value of the counter of the first chip, and the clock precision synchronization between the first chip and the second chip is realized.
According to the cross-chip signal synchronization method provided by the embodiment of the invention, a first chip sends a synchronization signal to a second chip according to preset time, so that the second chip records a phase count value corresponding to a clock signal of the second chip when receiving the synchronization signal; the preset time is a phase count value corresponding to a clock signal of the first chip when the synchronous signal is sent; the first chip is the same as the second chip; acquiring the synchronous signal output to the pin of the first chip and feeding back the synchronous signal to the first chip; and sending the phase counting value of the first chip and the preset time when the feedback synchronization signal is received to the second chip so that the second chip corrects the clock signal of the second chip according to the phase counting value of the first chip, the preset time and the phase counting value recorded by the second chip when the feedback synchronization signal is received. The phase difference of the received signals of the chip can be calculated by the second chip according to the phase counting value corresponding to the clock signal of the first chip when the fed-back synchronous signal is received and the preset time by sending the phase counting value of the first chip when the fed-back synchronous signal is received and the preset time to the second chip, so that the time delay of the signals in the internal circuit of the chip is obtained. And the second chip can determine the clock asynchrony condition between the first chip and the second chip according to the preset time and the phase count value corresponding to the clock signal of the second chip when the synchronous signal is received, and eliminate the delay error according to the phase difference. And the second chip performs phase correction of the clock signal according to the phase difference, the preset time and the recorded phase counting value, so that the clock of the first chip and the clock of the second chip are accurately synchronized.
Example two
Fig. 2 is a schematic flowchart of a cross-chip signal synchronization method according to a second embodiment of the present invention. On the basis of the first embodiment, the present embodiment further provides another method for synchronizing signals across chips, so as to achieve accurate synchronization of the first chip and the second chip. The method specifically comprises the following steps:
s210, sending a synchronization signal to a second chip according to preset time so that the second chip records a phase count value corresponding to a clock signal of the second chip when receiving the synchronization signal; the preset time is a phase count value corresponding to a clock signal of the first chip when the synchronous signal is sent; the first chip is the same as the second chip;
when the clock correction is carried out on the second chip, the first chip sends a synchronous signal to the second chip according to preset time; the synchronous correction of the clock signals of the first chip and the second chip is actually the correction of the phase count values in the counters of the first chip and the second chip. The preset time is a phase counting value corresponding to the clock signal of the first chip. Specifically, after the first chip sends the synchronization signal to the second chip, the second chip may record a phase count value corresponding to a current clock signal of the second chip when receiving the synchronization signal.
In an implementation example, the specific process of sending the synchronization signal to the second chip according to the predetermined time to enable the second chip to record the phase count value corresponding to the clock signal of the second chip when receiving the synchronization signal may be: sending a synchronous signal to a second pin of the second chip through a first pin of the first chip according to preset time; wherein the first pin and the second pin are the same pin of the chip.
Specifically, since the predetermined time may be a phase count value corresponding to a preset clock signal, when the counter value of the first chip is the predetermined time, a synchronization signal is generated and sent to the second pin of the second chip through the first pin of the first chip; the second chip receives the synchronous signal through a second pin of the second chip.
S220, acquiring the synchronous signal output to the pin of the first chip and feeding back the synchronous signal to the first chip;
when the synchronous signal is output to the first chip pin from the inside of the first chip, the synchronous signal output to the first pin of the first chip can be obtained and fed back to the first chip. Specifically, after the synchronization signal output to the first pin of the first chip is obtained, the synchronization signal output to the first pin of the first chip may be fed back to the inside of the first chip through the first pin of the first chip. Optionally, the first pin of the first chip may be further connected to another pin of the first chip, and when the synchronization signal is output from the inside of the first chip to the first chip pin, the synchronization signal output to the first pin of the first chip may be obtained through another pin connected to the first pin, and the synchronization signal is fed back to the inside of the first chip through another pin connected to the first pin, in which case, the another pin of the first chip and the second pin of the second chip are the same pin of the chip.
S230, calculating the phase difference of the chip receiving signals according to the phase counting value of the first chip when the fed-back synchronous signals are received and the preset time;
and when the first chip receives the fed-back synchronous signal, reading a phase count value corresponding to the clock signal of the first chip. In one implementation example, the phase count value of the first chip when the fed-back synchronization signal is received is obtained by an edge detection circuit, which is a signal detection circuit provided inside the first chip. And the signal detection circuit arranged in the chip is connected with the clock counter of the first chip. And when the signal detection circuit detects the inversion edge of the synchronous signal fed back to the first chip, reading the current phase count value from the clock counter of the first chip to obtain the phase count value of the first chip when the fed-back synchronous signal is received. Optionally, the first chip and the second chip operate using the same clock source.
Since the synchronization signal is fed back to the first chip and undergoes two internal circuit transmissions of the chip, which is equivalent to the transmission of the synchronization signal from the internal circuit of the first chip to the internal circuit of the second chip, the difference between the phase count value corresponding to the clock signal of the first chip when the fed-back synchronization signal is received and the predetermined time is calculated, and the phase difference, i.e., the delay, in the process of transmitting the synchronization signal from the first chip to receiving the synchronization signal by the second chip can be obtained.
In an embodiment, the specific process of calculating the phase difference of the chip receiving signal according to the clock signal of the first chip when the fed-back synchronization signal is received and the predetermined time may be: reading a phase count value corresponding to a clock signal of the first chip when the fed-back synchronous signal is detected through the signal detection circuit; and calculating the phase difference of the chip receiving signals according to the read phase counting value and the preset time.
Specifically, the signal detection circuit can be arranged to be connected with a first pin of the first chip for outputting the synchronization signal so as to acquire the synchronization signal output to the first chip pin; the signal detection circuit is connected with the first chip and used for feeding back a synchronous signal output to a first pin of the first chip to the interior of the first chip; and the signal detection circuit is connected with a clock of the first chip, namely a counter. After the signal detection circuit obtains the synchronization signal output to the first pin of the first chip and feeds back the synchronization signal to the first chip, the signal detection circuit reads a phase count value, namely a counter value, corresponding to the clock signal of the first chip when detecting the inversion edge of the fed-back synchronization signal.
S240, the phase difference is sent to the second chip, and the phase counting value of the first chip when the phase difference is preset or the fed-back synchronous signal is received is sent to the second chip, so that the second chip corrects the clock signal of the second chip according to the phase difference, the phase counting value recorded by the second chip and the phase counting value of the first chip when the phase difference is preset or the fed-back synchronous signal is received.
After the first chip calculates and obtains the phase difference in the process that the synchronous signal is sent from the first chip to the second chip for receiving, the first chip sends the phase difference to the second chip; and the first chip also counts the phase value of the first chip at a preset time or the time when the fed-back synchronization signal is received. After the first chip sends the synchronous signal to the second chip, the second chip can record a phase count value corresponding to a current clock signal of the second chip when receiving the synchronous signal through a second pin of the second chip, and then after the second chip receives a phase difference sent by the first chip and a phase count value of the first chip at a preset time or receives a feedback of the synchronous signal, the phase difference, the recorded phase count value and the preset time or the phase count value of the first chip at the feedback of the synchronous signal are combined to determine a clock asynchronization condition between the first chip and the second chip according to a preset time, namely a clock signal phase difference between the first chip and the second chip; and time errors are excluded from the phase difference. The second chip can correct the current phase count value of the counter of the second chip by subtracting the phase difference according to the determined clock asynchronization condition, so that the phase count value of the counter of the second chip is consistent with the phase count value of the counter of the first chip, and the clock precision synchronization between the first chip and the second chip is realized.
EXAMPLE III
Fig. 3 is a schematic flowchart of a cross-chip signal synchronization method according to a second embodiment of the present invention. On the basis of the second embodiment, the present embodiment further provides another method for synchronizing signals across chips, so as to achieve accurate synchronization of the first chip and the second chip. The method specifically comprises the following steps:
s310, determining the preset time for sending the synchronous signal to the second chip, and sending the preset time to the second chip; the preset time is a phase counting value corresponding to a clock signal of the first chip when the synchronous signal is sent;
specifically, before the first chip transmits the synchronization signal to the second chip at a predetermined time, the first chip may determine the predetermined time to transmit the synchronization signal to the second chip in advance and transmit the determined predetermined time to the second chip.
S320, sending a synchronous signal to a second chip according to preset time, so that the second chip updates a phase count value corresponding to a clock signal of the second chip to be the preset time when receiving the synchronous signal; wherein the first chip is the same as the second chip;
and sending a synchronization signal to the second chip by the first chip according to preset time so that the second chip can directly update the phase count value corresponding to the clock signal of the second chip to be the preset time corresponding to the received synchronization signal when receiving the synchronization signal, wherein the phase error of the clock signal of the second chip and the first chip is only the delay in the process of sending the synchronization signal from the first chip to receiving the synchronization signal by the second chip.
Optionally, the predetermined time may be a phase count value corresponding to one clock signal when the synchronization signal is preset to be transmitted. And generating a synchronous signal and sending the synchronous signal to the second chip when the value in the counter of the first chip is preset time.
S330, acquiring the synchronous signal output to the first chip pin and feeding back the synchronous signal to the first chip;
specifically, when the synchronization signal is output from the inside of the first chip to the first chip pin, the synchronization signal output to the first pin of the first chip may be acquired and fed back to the first chip. Specifically, after the synchronization signal output to the first pin of the first chip is obtained, the synchronization signal output to the first pin of the first chip may be fed back to the inside of the first chip through the first pin of the first chip. Optionally, the first pin of the first chip may be further connected to another pin of the first chip, and when the synchronization signal is output from the inside of the first chip to the first chip pin, the synchronization signal output to the first pin of the first chip may be obtained through another pin connected to the first pin, and the synchronization signal is fed back to the inside of the first chip through another pin connected to the first pin, in which case, the another pin of the first chip and the second pin of the second chip are the same pin of the chip.
S340, calculating the phase difference of signals received by the chip according to the phase counting value of the first chip when the fed-back synchronous signal is received and the preset time;
specifically, when the first chip receives the fed-back synchronization signal, the phase count value corresponding to the clock signal of the first chip at this time may be read. In one implementation example, the phase count value of the first chip when the fed-back synchronization signal is received is obtained by an edge detection circuit, which is a signal detection circuit provided inside the first chip. And the signal detection circuit arranged in the chip is connected with the clock counter of the first chip. And when the signal detection circuit detects the inversion edge of the synchronous signal fed back to the first chip, reading the current phase count value from the clock counter of the first chip to obtain the phase count value of the first chip when the fed-back synchronous signal is received. Optionally, the first chip and the second chip operate using the same clock source. Since the synchronization signal is fed back to the first chip and undergoes two internal circuit transmissions of the chip, it is equivalent to the transmission of the synchronization signal from the internal circuit of the first chip to the internal circuit of the second chip. Then, the difference between the phase count value corresponding to the clock signal of the first chip when the fed-back synchronization signal is received and the predetermined time is calculated, and the phase difference of the synchronization signal in the process from the transmission of the first chip to the reception of the second chip can be obtained.
And S350, sending the phase difference to the second chip so that the second chip corrects the phase of the current clock signal of the second chip according to the phase difference.
The first chip sends the determined preset time to the second chip before the synchronous signal is sent, so that the second chip can directly update the phase count value corresponding to the clock signal of the second chip to be the preset time corresponding to the received synchronous signal when the second chip receives the synchronous signal, and the phase error of the clock signal of the second chip and the first chip is only the delay in the process that the synchronous signal is sent from the first chip to the second chip for receiving. After the first chip calculates and obtains the phase difference of the synchronous signal in the process of sending the synchronous signal from the first chip to the second chip for receiving, the first chip sends the phase difference to the second chip, so that the second chip can obtain the phase counting value corresponding to the clock signal of the current second chip when receiving the phase difference, and updates the phase counting value corresponding to the current clock signal of the second chip into the sum of the phase counting value corresponding to the obtained clock signal and the phase difference. Therefore, the phase correction of the clock signal of the second chip is completed, and the clock synchronization between the first chip and the second chip is accurately realized.
Example four
Fig. 4 shows a device for cross-chip signal synchronization according to a third embodiment of the present invention. On the basis of the first or second embodiment, the embodiment of the present invention further provides a device 4 for synchronizing signals across chips, the device comprising:
a synchronization signal sending module 301, configured to send a synchronization signal to a second chip according to a predetermined time, so that the second chip records a phase count value corresponding to a clock signal of the second chip when receiving the synchronization signal; the preset time is a phase count value corresponding to a clock signal of the first chip when the synchronous signal is sent; the first chip is the same as the second chip;
in an implementation example, when a synchronization signal is sent to a second chip according to a predetermined time, so that the second chip records a phase count value corresponding to a clock signal of the second chip when receiving the synchronization signal, the synchronization signal sending module 401 further includes:
the first synchronous signal sending unit is used for sending a synchronous signal to a second pin of the second chip through a first pin of the first chip according to preset time; wherein the first pin and the second pin are the same pin of the chip.
In an implementation example, when a synchronization signal is sent to a second chip according to a predetermined time, so that the second chip records a phase count value corresponding to a clock signal of the second chip when receiving the synchronization signal, the synchronization signal sending module 401 further includes:
and the second synchronous signal sending unit is used for sending a synchronous signal to a second chip according to preset time so that the second chip updates a phase count value corresponding to the clock signal of the second chip to be the preset time when receiving the synchronous signal.
In an implementation example, before the synchronization signal sending module 301 sends a synchronization signal to a second chip according to a predetermined time, so that the second chip records a phase count value corresponding to a clock signal of the second chip when receiving the synchronization signal, the apparatus further includes:
and the preset time sending module is used for determining the preset time for sending the synchronization signal to the second chip and sending the preset time to the second chip.
A synchronization signal feedback module 402, configured to obtain the synchronization signal output to the first chip pin and feed back the synchronization signal to the first chip;
in an implementation example, when the synchronization signal output to the first chip pin is obtained and fed back to the first chip, the synchronization signal feedback module 402 includes:
in one example, the apparatus further comprises:
the phase difference calculating module is used for calculating the phase difference of signals received by the chip according to the phase counting value of the first chip when the fed-back synchronous signals are received and the preset time;
in one embodiment, when the phase difference of the chip receiving signal is calculated according to the phase count value of the first chip when the fed-back synchronization signal is received and the predetermined time, the phase difference calculation module includes:
the clock signal reading unit is used for reading a phase counting value corresponding to the clock signal of the first chip when the fed-back synchronous signal is detected through the signal detection circuit;
and the phase difference calculating unit is used for calculating the phase difference of the signals received by the chip according to the read phase counting value and the preset time.
The clock correction module 403 is configured to send the phase count value of the first chip and the predetermined time when the synchronization signal is received, to the second chip, so that the second chip corrects the clock signal of the second chip according to the phase count value of the first chip, the predetermined time and the recorded phase count value when the synchronization signal is received.
In an implementation example, when the phase count value of the first chip and the predetermined time when the feedback synchronization signal is received are sent to the second chip, so that the second chip corrects the clock signal of the second chip according to the phase count value of the first chip when the feedback synchronization signal is received, the predetermined time and the recorded phase count value, the clock correction module 403 further includes:
and the phase count value reading unit is used for acquiring the phase count value of the first chip when the fed-back synchronization signal is received through the signal detection circuit.
And the first clock correction unit is used for sending the phase difference and the preset time to the second chip so as to enable the second chip to correct the phase of the clock signal of the second chip according to the phase difference, the preset time and the recorded phase counting value.
And the second clock correction unit is used for sending the phase difference to the second chip so as to enable the second chip to correct the phase of the current clock signal of the second chip according to the phase difference.
According to the cross-chip signal synchronization device provided by the embodiment of the invention, a first chip sends a synchronization signal to a second chip according to preset time, so that the second chip records a phase count value corresponding to a clock signal of the second chip when receiving the synchronization signal; the preset time is a phase count value corresponding to a clock signal of the first chip when the synchronous signal is sent; the first chip is the same as the second chip; acquiring the synchronous signal output to the pin of the first chip and feeding back the synchronous signal to the first chip; calculating the phase difference of the chip receiving signals according to the phase counting value of the first chip when the fed-back synchronous signals are received and the preset time; and sending the phase difference and the preset time to the second chip so that the second chip corrects the clock signal of the second chip according to the phase difference, the preset time and the phase counting value recorded by the second chip. And calculating the phase difference of the received signals of the chip by the first chip according to the phase counting value corresponding to the clock signal of the first chip when the fed-back synchronous signal is received and the preset time, so as to obtain the delay of the signals in the internal circuit transmission of the chip. And sending the phase difference and the preset time to the second chip to correct the clock signal of the second chip, so that the second chip can determine the clock asynchrony condition between the first chip and the second chip according to the preset time and the phase count value corresponding to the clock signal of the second chip recorded when the synchronous signal is received, and eliminate delay errors according to the phase difference. And the second chip performs phase correction of the clock signal according to the phase difference, the preset time and the recorded phase counting value, so that the clock of the first chip and the clock of the second chip are accurately synchronized.
EXAMPLE five
Fig. 5 is a schematic structural diagram of a chip according to a fourth embodiment of the present invention. The chip includes: a processor 51, a memory 52 and a computer program 53 stored in said memory 52 and executable on said processor 51, such as a program for a method of cross-chip signal synchronization. The processor 51 implements the steps in the above-mentioned method embodiment of cross-chip signal synchronization when executing the computer program 53, such as the steps S110 to S130 shown in fig. 1.
Illustratively, the computer program 53 may be partitioned into one or more modules that are stored in the memory 52 and executed by the processor 51 to accomplish the present application. The one or more modules may be a series of computer program instruction segments capable of performing specific functions, which are used to describe the execution of the computer program 53 in the chip. For example, the computer program 53 may be divided into a synchronization signal sending module, a synchronization signal feedback module and a clock correction module, and each module has the following specific functions:
the synchronous signal sending module is used for sending a synchronous signal to a second chip according to preset time so that the second chip records a phase counting value corresponding to a clock signal of the second chip when receiving the synchronous signal; the preset time is a phase count value corresponding to a clock signal of the first chip when the synchronous signal is sent; the first chip is the same as the second chip;
the synchronous signal feedback module is used for acquiring the synchronous signal output to the pin of the first chip and feeding back the synchronous signal to the first chip;
and the clock correction module is used for sending the phase counting value of the first chip and the preset time when the feedback synchronous signal is received to the second chip so that the second chip corrects the clock signal of the second chip according to the phase counting value of the first chip when the feedback synchronous signal is received, the preset time and the phase counting value recorded by the second chip.
The chip may include, but is not limited to, a processor 51, a memory 52, and a computer program 53 stored in the memory 52. Those skilled in the art will appreciate that fig. 5 is merely an example of a chip and is not meant to be limiting and may include more or fewer components than those shown, or some components may be combined, or different components, e.g., the chip may also include input-output devices, network access devices, buses, etc.
The Processor 51 may be a Central Processing Unit (CPU), other general purpose Processor, a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), an off-the-shelf Programmable Gate Array (FPGA) or other Programmable logic device, discrete Gate or transistor logic device, discrete hardware component, etc. A general purpose processor may be a microprocessor or the processor may be any conventional processor or the like.
The memory 52 may be an internal storage unit of the chip, such as a hard disk or a memory of the chip. The memory 52 may also be an external storage device, such as a plug-in hard disk provided on a chip, a Smart Media Card (SMC), a Secure Digital (SD) Card, a Flash memory Card (Flash Card), and the like. Further, the memory 52 may also include both internal memory units of the chip and external memory devices. The memory 52 is used to store the computer program and other programs and data required for the method of cross-chip signal synchronization. The memory 52 may also be used to temporarily store data that has been output or is to be output.
It will be apparent to those skilled in the art that, for convenience and brevity of description, only the above-mentioned division of the functional units and modules is illustrated, and in practical applications, the above-mentioned function distribution may be performed by different functional units and modules according to needs, that is, the internal structure of the apparatus is divided into different functional units or modules to perform all or part of the above-mentioned functions. Each functional unit and module in the embodiments may be integrated in one processing unit, or each unit may exist alone physically, or two or more units are integrated in one unit, and the integrated unit may be implemented in a form of hardware, or in a form of software functional unit. In addition, specific names of the functional units and modules are only for convenience of distinguishing from each other, and are not used for limiting the protection scope of the present application. The specific working processes of the units and modules in the system may refer to the corresponding processes in the foregoing method embodiments, and are not described herein again.
In the above embodiments, the descriptions of the respective embodiments have respective emphasis, and reference may be made to the related descriptions of other embodiments for parts that are not described or illustrated in a certain embodiment.
Those of ordinary skill in the art will appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware or combinations of computer software and electronic hardware. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the implementation. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present invention.
In the embodiments provided in the present invention, it should be understood that the disclosed apparatus/terminal device and method may be implemented in other ways. For example, the above-described embodiments of the apparatus/terminal device are merely illustrative, and for example, the division of the modules or units is only one logical division, and there may be other divisions when actually implemented, for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices or units, and may be in an electrical, mechanical or other form.
The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment. In addition, functional units in the embodiments of the present invention may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit. The integrated unit can be realized in a form of hardware, and can also be realized in a form of a software functional unit.
The integrated modules/units, if implemented in the form of software functional units and sold or used as separate products, may be stored in a computer readable storage medium. Based on such understanding, all or part of the flow of the method according to the embodiments of the present invention may also be implemented by a computer program, which may be stored in a computer-readable storage medium, and when the computer program is executed by a processor, the steps of the method embodiments may be implemented. Wherein the computer program comprises computer program code, which may be in the form of source code, object code, an executable file or some intermediate form, etc. The computer-readable medium may include: any entity or device capable of carrying the computer program code, recording medium, usb disk, removable hard disk, magnetic disk, optical disk, computer Memory, Read-Only Memory (ROM), Random Access Memory (RAM), electrical carrier wave signals, telecommunications signals, software distribution medium, and the like. It should be noted that the computer readable medium may contain content that is subject to appropriate increase or decrease as required by legislation and patent practice in jurisdictions, for example, in some jurisdictions, computer readable media does not include electrical carrier signals and telecommunications signals as is required by legislation and patent practice.
The above-mentioned embodiments are only used for illustrating the technical solutions of the present invention, and not for limiting the same; although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications and substitutions do not substantially depart from the spirit and scope of the embodiments of the present invention, and are intended to be included within the scope of the present invention.
Claims (10)
1. A method of cross-chip signal synchronization, performed by a first chip, the method comprising:
sending a synchronous signal to a second chip according to preset time so that the second chip records a phase count value corresponding to a clock signal of the second chip when receiving the synchronous signal; the preset time is a phase count value corresponding to a clock signal of the first chip when the synchronous signal is sent; the first chip is the same as the second chip;
acquiring the synchronous signal output to the pin of the first chip and feeding back the synchronous signal to the first chip;
and sending the phase counting value of the first chip and the preset time when the feedback synchronization signal is received to the second chip so that the second chip corrects the clock signal of the second chip according to the phase counting value of the first chip, the preset time and the phase counting value recorded by the second chip when the feedback synchronization signal is received.
2. The method of cross-chip signal synchronization of claim 1, further comprising, after obtaining and feeding back the synchronization signal output to the first chip pin to the first chip:
and calculating the phase difference of the chip receiving signals according to the phase counting value of the first chip when the fed-back synchronous signal is received and the preset time.
3. The method for synchronizing signals across chips according to claim 2, wherein the sending the phase count value of the first chip and the predetermined time when the fed back synchronization signal is received to the second chip so that the second chip corrects the clock signal of the second chip according to the phase count value of the first chip when the fed back synchronization signal is received, the predetermined time and the phase count value recorded by the second chip comprises:
and sending the phase difference to the second chip, and sending the phase counting value of the first chip when the phase difference is in the preset time or the fed back synchronous signal is received to the second chip, so that the second chip corrects the clock signal of the second chip according to the phase difference, the phase counting value recorded by the second chip, the phase counting value of the first chip when the phase difference is in the preset time or the fed back synchronous signal is received.
4. The method for synchronizing signals across chips according to claim 2, before sending a synchronization signal to a second chip according to a predetermined time to make the second chip record a phase count value corresponding to a clock signal of the second chip when receiving the synchronization signal, further comprising:
and determining a preset time for sending the synchronous signal to the second chip, and sending the preset time to the second chip.
5. The method for synchronizing signals across chips according to claim 4, wherein the sending a synchronization signal to a second chip according to a predetermined time to make the second chip record a phase count value corresponding to a clock signal of the second chip when receiving the synchronization signal comprises:
and sending a synchronous signal to a second chip according to preset time, so that the second chip updates a phase count value corresponding to a clock signal of the second chip to be the preset time when receiving the synchronous signal.
6. The method for synchronizing signals across chips according to claim 5, wherein the sending the phase count value of the first chip and the predetermined time when the fed back synchronization signal is received to the second chip so that the second chip corrects the clock signal of the second chip according to the phase count value of the first chip when the fed back synchronization signal is received, the predetermined time and the phase count value recorded by the second chip comprises:
and sending the phase difference to the second chip so that the second chip corrects the phase of the current clock signal of the second chip according to the phase difference.
7. The method for synchronizing signals across chips according to any one of claims 1 to 6, wherein the sending a synchronization signal to a second chip according to a predetermined time to make the second chip record a phase count value corresponding to a clock signal of the second chip when receiving the synchronization signal comprises:
sending a synchronous signal to a second pin of the second chip through a first pin of the first chip according to preset time; wherein the first pin and the second pin are the same pin of the chip.
8. The method of claim 7, wherein the sending the phase count value of the first chip and the predetermined time when the feedback synchronization signal is received to the second chip to enable the second chip to correct the clock signal of the second chip according to the phase count value of the first chip when the feedback synchronization signal is received, the predetermined time and the phase count value recorded by the second chip comprises:
and acquiring a phase count value of the first chip when the fed-back synchronous signal is received through a signal detection circuit.
9. An apparatus for cross-chip signal synchronization, comprising:
the synchronous signal sending module is used for sending a synchronous signal to a second chip according to preset time so that the second chip records a phase counting value corresponding to a clock signal of the second chip when receiving the synchronous signal; the preset time is a phase count value corresponding to a clock signal of a first chip when the synchronous signal is sent; the first chip is the same as the second chip;
the synchronous signal feedback module is used for acquiring the synchronous signal output to the pin of the first chip and feeding back the synchronous signal to the first chip;
and the clock correction module is used for sending the phase counting value of the first chip and the preset time when the feedback synchronous signal is received to the second chip so that the second chip corrects the clock signal of the second chip according to the phase counting value of the first chip when the feedback synchronous signal is received, the preset time and the phase counting value recorded by the second chip.
10. A chip comprising a memory, a processor and a computer program stored in the memory and executable on the processor, wherein the processor when executing the computer program implements the steps of the method for cross-chip signal synchronization according to any of claims 1 to 7.
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