CN111669326B - Shortest route implementation method based on FPGA - Google Patents
Shortest route implementation method based on FPGA Download PDFInfo
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- CN111669326B CN111669326B CN202010377485.1A CN202010377485A CN111669326B CN 111669326 B CN111669326 B CN 111669326B CN 202010377485 A CN202010377485 A CN 202010377485A CN 111669326 B CN111669326 B CN 111669326B
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L45/00—Routing or path finding of packets in data switching networks
- H04L45/12—Shortest path evaluation
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L45/00—Routing or path finding of packets in data switching networks
- H04L45/02—Topology update or discovery
Abstract
The invention discloses a shortest route implementation method based on FPGA, which is characterized in that a shortest route algorithm is respectively executed for the combination of a source exchanger of each group of topology information and a target exchanger of the topology information by traversing all the combinations of the source exchanger of the topology information and the target exchanger of the topology information to obtain the adjacent matrix information after the iteration of an inserted node. The invention realizes the coordination of the SDN controller and the network topology synchronization in a high-speed network environment by utilizing the FPGA, accelerates the data transmission and reduces the influence on the network performance caused by the decision and configuration of the transmission link performance.
Description
Technical Field
The invention relates to the technical field of SDN (software defined network), in particular to a shortest route implementation method based on FPGA (field programmable gate array).
Background
With continuous expansion of network scale and rapid growth of traffic, the conventional network structure and switching device cannot meet the current network data transmission and performance requirements, and a novel SDN network structure is produced at the same time. The SDN realizes the complete decoupling of a control plane and a data plane, abstracts the control function bound in the forwarding equipment to an upper layer, and has the characteristics of centralized control and network programming. When a complex network is faced, because a single SDN controller cannot meet the network requirements, the complex network needs to be divided, one SDN controller is configured for each divided area, and the network is controlled in a multi-control cooperative control mode. However, in a network with multiple SDN controllers, how to select a path to help the multiple SDN controllers perform efficient communication is a troublesome problem.
Disclosure of Invention
The invention aims to solve the problems of control cooperation and data forwarding efficiency among a plurality of SDN controllers in a complex network, and provides a shortest routing implementation method based on an FPGA.
In order to solve the problems, the invention is realized by the following technical scheme:
the shortest route implementation method based on the FPGA comprises the following steps:
step S1: the SDN controller packages the topology information into UDP topology data through a UDP protocol and transmits the UDP topology data upwards to the FPGA;
step S2: the method comprises the steps that an FPGA receives UDP topological data sent by each SDN controller, decapsulates the UDP topological data to extract topological information, and counts the number N of topological information switches; the write address of the 8-bit RAM _1 is increased from 1, and the source switch, the destination switch and the weight of the topology information are written into the RAM _1 one by one;
step S3: initializing a RAM _2, and setting an initial value of an insertion node to be 1;
step S4: data of the RAM _1 is extracted into the RAM _2, namely:
firstly, taking a source switch of topology information as an RAM _1 read address with high 4 bits, taking a target switch of the topology information as an RAM _1 read address with low 4 bits, and reading the source switch of the topology information, the target switch of the topology information and the weight from the RAM _ 1;
Then, taking a source exchanger of the topological information as an RAM _2 write address high 4 bits, taking a target exchanger of the topological information as an RAM _2 write address low 4 bits, and writing the weight and the current insertion node into the RAM _ 2;
step S5: traversing all combinations of the source switch of the topology information and the destination switch of the topology information, and for each group of combinations of the source switch of the topology information and the destination switch of the topology information, respectively executing the following operations to obtain the adjacency matrix information after the insertion node iteration:
step S5.1: the weight _1 from the source switch of the topology information to the inserted node is read from the RAM _2, the weight _2 from the current inserted node to the destination switch of the topology information, and the weight _3 from the source switch of the topology information to the destination switch of the topology information; wherein:
taking a source switch of the topology information as an RAM _2 read address with high 4 bits, taking a current insertion node as an RAM _2 read address with low 4 bits, reading the weight from the RAM _2, and taking the weight as the weight _1 from the source switch of the topology information to the insertion node;
taking the current inserted node as the high 4 bits of the RAM _2 read address and the target switch of the topology information as the low 4 bits of the RAM _2 read address, reading the weight from the RAM _2 and taking the weight as the weight _2 from the current inserted node to the target switch of the topology information;
Taking a source switch of the topology information as an RAM _2 read address with high 4 bits, taking a target switch of the topology information as an RAM _2 read address with low 4 bits, reading the weight from the RAM _2, and taking the weight as the weight _3 from the source switch of the topology information to the target switch of the topology information;
step S5.2: adding the weight _1 from the source switch of the topology information to the inserted node and the weight _2 from the current inserted node to the destination switch of the topology information to obtain the comprehensive weight _ S, and comparing the comprehensive weight _ S with the weight _3 from the source switch of the topology information to the destination switch of the topology information:
if weight _ S is less than weight _3, updating the weight _ S and the inserting node from the source switch of the topology information to the destination switch of the topology information to RAM _2 by taking the source switch of the topology information as the high 4 bits of the RAM _2 write address and taking the destination switch of the topology information as the low 4 bits of the RAM _2 write address; otherwise, not processing;
step S6: judging whether the current insertion node is more than or equal to the number N of the topology information switches: if yes, the shortest path algorithm is ended, at this time, the shortest path information stored in the RAM _2 is the final shortest path information, and the process goes to step S7; otherwise, adding 1 to the insertion node, and going to step S5;
Step S7: when a user initiates an access request, the SDN controller encapsulates request information through a UDP (user Datagram protocol) protocol to form UDP request data and transmits the UDP request data upwards to the FPGA;
step S8: the FPGA receives UDP request data sent by each SDN controller, decapsulates the UDP request data to extract request information, takes a source switch of the request information as the high 4 bits of a RAM _2 read address, takes a target switch of the request information as the low 4 bits of the RAM _2 read address, and reads final shortest path information from the RAM _ 2.
In the above scheme, the storage format of the RAM _1 is:
in the above scheme, the storage format of the RAM _2 is:
the topology information of step S1 includes the source switch, the source port, the destination switch, the destination port and the weight.
The request message of step S8 includes the source switch, the source port, the destination switch and the destination port.
Compared with the prior art, the method realizes the coordination of the SDN controller and the network topology synchronization under the high-speed network environment by utilizing the FPGA, accelerates the data transmission, and reduces the influence on the network performance caused by the decision and configuration of the transmission link performance.
Drawings
Fig. 1 is an overall flowchart of an FPGA-based shortest route implementation method.
Fig. 2 is a flowchart of the shortest path algorithm in fig. 1.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is further described in detail below with reference to specific examples.
A shortest route implementation method based on FPGA, as shown in fig. 1 and 2, specifically includes the following steps:
step S1: and the SDN controller packages the topology information through a UDP protocol to form UDP topology data, and the UDP topology data is upwards transmitted to the FPGA.
The topology information includes src _ Switch (source Switch), src _ Port (source Port), dst _ Switch (destination Switch), dst _ Port (destination Port), and weight.
Step S2: the FPGA receives UDP topology data sent by each SDN controller, decapsulates the UDP topology data to extract topology information, stores each piece of topology information into the RAM _1, counts the number of topology information switches, and records the number as N. The writing address of the RAM _1 is increased from the sequence number 1, and 1 is added when one piece of topological information is stored.
The storage format of the RAM _1 is as follows:
step S3: in the algorithm execution process, an on-chip RAM is needed to maintain shortest path information, an RAM _2 is initialized, an initial value of a pre _ node of an insertion node is set to be 1 (the insertion node is an intermediate variable for calculating the shortest path subsequently, belongs to a switch passing through a path from a source switch to a destination switch, and the value range is from 1 to the number N of topology information switches), and the operation enters step S4;
Step S4: before the algorithm is executed, the topological information of the RAM _1 is extracted and stored in the RAM _ 2. The address part takes src _ Switch as the upper 4 bits of the RAM _2 write address, and dst _ Switch as the lower 4 bits of the RAM _2 write address; the data part writes weight into the upper 8 bits of the RAM _2 data, the middle 4 bits are reserved (default is 0), and the lower 4 bits are initially 0 (namely, the current shortest path does not contain an inserted node);
the storage format of the RAM _2 is as follows:
step S5: after the RAM _1 data extraction is completed, the algorithm executes flag position 1. And with src _ Switch as the upper 4 bits of the RAM _2 address, and dst _ Switch as the lower 4 bits of the RAM _2 address, reading the weight (direct connection weight) of the upper 8 bits of the RAM _2 data. Proceeding to step S51;
step S51: using src _ Switch as the upper 4 bits of the RAM _2 read address, and pre _ node as the lower 4 bits of the RAM _2 read address, and reading weight _1 of the upper 8 bits of the RAM _2 data; and taking pre _ node as the upper 4 bits of the RAM _2 read address, dst _ Switch as the lower 4 bits of the RAM _2 read address, and reading the weight _2 of the upper 8 bits of the RAM _2 data. Weight _1 is added to weight _2 to obtain weight _ S (i.e., containing the weight of the inserted node), and compared to weight _ 3.
Step S54: if weight _ S is smaller than weight _3, writing weight _ S and insertion node pre _ node into RAM _2 of step S5; otherwise, the RAM _2 is kept unchanged.
Step S6: and judging whether the inserted node pre _ node is more than or equal to the number N of the topology information switches. If so, the algorithm executes flag position 0, the shortest path algorithm ends, and RAM _2 holds the shortest path information. Otherwise, adding 1 to the inserted node pre _ node, and jumping to step S5;
step S7: and a user initiates an access request, and the SDN controller encapsulates the request information through a UDP protocol to form UDP request data and transmits the UDP request data upwards to the FPGA.
The request information includes src _ Switch (source Switch), src _ Port (source Port), dst _ Switch (destination Switch), and dst _ Port (destination Port).
Step S8: the method comprises the steps that an FPGA receives UDP request data sent by each SDN controller, decapsulates the UDP request data to extract request information, uses a source switch in each piece of request information as the high 4 bits of a RAM _2 read address, uses a target switch as the low 4 bits of the RAM _2 read address, and reads corresponding shortest path information from the RAM _ 2;
step S9: and the FPGA packages the shortest path information into UDP path data through a UDP protocol, and sends the UDP path data to the corresponding SDN controller.
According to the invention, by utilizing the high-speed concurrency characteristic of the FPGA, the SDN controller uploads the topology information through a UDP protocol, and the FPGA analyzes the UDP data packet to obtain the topology information which is stored in the DDR 2. When a user initiates an access request, the access DDR2 obtains topology information and obtains global optimal transmission path information through a shortest routing algorithm, packages the information into UDP data and sends the UDP data to the SDN controller. The invention can improve the data transmission efficiency under the high-speed network environment.
It should be noted that, although the above-mentioned embodiments of the present invention are illustrative, the present invention is not limited thereto, and thus the present invention is not limited to the above-mentioned embodiments. Other embodiments, which can be made by those skilled in the art in light of the teachings of the present invention, are considered to be within the scope of the present invention without departing from its principles.
Claims (3)
1. The shortest route implementation method based on the FPGA is characterized by comprising the following steps:
step S1: the SDN controller packages the topology information into UDP topology data through a UDP protocol and transmits the UDP topology data upwards to the FPGA;
step S2: the method comprises the steps that an FPGA receives UDP topological data sent by each SDN controller, decapsulates the UDP topological data to extract topological information, and counts the number N of topological information switches; the write address of the 8-bit RAM _1 is increased from 1, and the source switch, the destination switch and the weight of the topology information are written into the RAM _1 one by one; the storage format of the RAM _1 is as follows:
step S3: in the algorithm execution process, an on-chip RAM is needed to maintain shortest path information, RAM _2 is initialized, and the initial value of an inserted node is set to be 1;
step S4: data of the RAM _1 is extracted into the RAM _2, namely: firstly, taking a source switch of topology information as an RAM _1 read address with high 4 bits, taking a target switch of the topology information as an RAM _1 read address with low 4 bits, and reading the source switch of the topology information, the target switch of the topology information and the weight from the RAM _ 1; then, taking a source exchanger of the topology information as an RAM _2 write address high 4 bits, taking a target exchanger of the topology information as an RAM _2 write address low 4 bits, and writing the weight and the current insertion node into the RAM _ 2; the storage format of the RAM _2 is as follows:
Step S5: traversing all combinations of the source switch of the topology information and the destination switch of the topology information, and for each group of combinations of the source switch of the topology information and the destination switch of the topology information, respectively executing the following operations to obtain the adjacency matrix information after the insertion node iteration:
step S5.1: the weight _1 from the source switch of the topology information to the inserted node is read from the RAM _2, the weight _2 from the current inserted node to the destination switch of the topology information, and the weight _3 from the source switch of the topology information to the destination switch of the topology information; wherein:
taking a source switch of the topology information as an RAM _2 read address with high 4 bits, taking a current insertion node as an RAM _2 read address with low 4 bits, reading the weight from the RAM _2, and taking the weight as the weight _1 from the source switch of the topology information to the insertion node;
taking the current inserted node as the high 4 bits of the RAM _2 read address and the target switch of the topology information as the low 4 bits of the RAM _2 read address, reading the weight from the RAM _2 and taking the weight as the weight _2 from the current inserted node to the target switch of the topology information;
taking a source switch of the topology information as an RAM _2 read address with high 4 bits, taking a target switch of the topology information as an RAM _2 read address with low 4 bits, reading the weight from the RAM _2, and taking the weight as the weight _3 from the source switch of the topology information to the target switch of the topology information;
Step S5.2: adding the weight _1 from the source switch of the topology information to the inserted node and the weight _2 from the current inserted node to the destination switch of the topology information to obtain the comprehensive weight _ S, and comparing the comprehensive weight _ S with the weight _3 from the source switch of the topology information to the destination switch of the topology information:
if weight _ S is less than weight _3, updating the weight _ S and the inserting node from the source switch of the topology information to the destination switch of the topology information to RAM _2 by taking the source switch of the topology information as the high 4 bits of the RAM _2 write address and taking the destination switch of the topology information as the low 4 bits of the RAM _2 write address; otherwise, not processing;
step S6: judging whether the current insertion node is more than or equal to the number N of the topology information switches: if yes, the shortest path algorithm is ended, at this time, the shortest path information stored in the RAM _2 is the final shortest path information, and the process goes to step S7; otherwise, adding 1 to the insertion node, and going to step S5;
step S7: when a user initiates an access request, the SDN controller encapsulates request information through a UDP (user Datagram protocol) protocol to form UDP request data and transmits the UDP request data upwards to the FPGA;
step S8: the FPGA receives UDP request data sent by each SDN controller, decapsulates the UDP request data to extract request information, takes a source switch of the request information as the high 4 bits of a RAM _2 read address, takes a target switch of the request information as the low 4 bits of the RAM _2 read address, and reads final shortest path information from the RAM _ 2.
2. The FPGA-based shortest route implementation method of claim 1, wherein the topology information of step S1 includes a source switch, a source port, a destination switch, a destination port and a weight.
3. The FPGA-based shortest route implementation method of claim 1, wherein the request information of step S8 includes a source switch, a source port, a destination switch and a destination port.
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104615510A (en) * | 2015-03-09 | 2015-05-13 | 中国科学院自动化研究所 | Programmable device-based dual-mode redundant fault-tolerant method |
| CN105553855A (en) * | 2015-12-18 | 2016-05-04 | 航天恒星科技有限公司 | Method and system for dynamically adjusting topological structures of underlying network spanning trees |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US7684264B2 (en) * | 2007-01-26 | 2010-03-23 | Freescale Semiconductor, Inc. | Memory system with RAM array and redundant RAM memory cells having a different designed cell circuit topology than cells of non redundant RAM array |
| CN105049353B (en) * | 2015-07-28 | 2018-11-16 | 华为技术有限公司 | A kind of method and controller for business configuration routed path |
| US11019038B2 (en) * | 2016-02-03 | 2021-05-25 | Ted H. Szymanski | Methods to strengthen cyber-security and privacy in a deterministic internet of things |
| CN107276898B (en) * | 2017-08-02 | 2021-06-29 | 桂林电子科技大学 | Shortest route implementation method based on FPGA |
| CN107689919B (en) * | 2017-09-20 | 2019-12-27 | 北京科技大学 | Dynamic adjustment weight fuzzy routing method for SDN network |
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN104615510A (en) * | 2015-03-09 | 2015-05-13 | 中国科学院自动化研究所 | Programmable device-based dual-mode redundant fault-tolerant method |
| CN105553855A (en) * | 2015-12-18 | 2016-05-04 | 航天恒星科技有限公司 | Method and system for dynamically adjusting topological structures of underlying network spanning trees |
Non-Patent Citations (1)
| Title |
|---|
| 交换式局域网物理拓扑发现系统的研究与设计;崔婧昱等;《现代电子技术》;20080915(第18期);全文 * |
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Application publication date: 20200915 Assignee: Guangxi Boyan Technology Co.,Ltd. Assignor: GUILIN University OF ELECTRONIC TECHNOLOGY Contract record no.: X2022450000542 Denomination of invention: Implementation of shortest route based on FPGA Granted publication date: 20220729 License type: Common License Record date: 20221229 |