CN107276898B

CN107276898B - Shortest route implementation method based on FPGA

Info

Publication number: CN107276898B
Application number: CN201710651401.7A
Authority: CN
Inventors: 王勇; 何雄森; 张学庆; 叶苗; 俸皓
Original assignee: Guilin University of Electronic Technology
Current assignee: Guilin University of Electronic Technology
Priority date: 2017-08-02
Filing date: 2017-08-02
Publication date: 2021-06-29
Anticipated expiration: 2037-08-02
Also published as: CN107276898A

Abstract

The invention discloses a shortest routing implementation method based on an FPGA (field programmable gate array). by utilizing the high-speed concurrency characteristic of the FPGA, an SDN (software defined network) controller uploads topology information through a UDP (user datagram protocol), and the FPGA analyzes a UDP (user datagram protocol) data packet to obtain the topology information which is stored in a DDR 2. When a user initiates an access request, the access DDR2 obtains the topology information and obtains the optimal transmission path information through the shortest routing algorithm, packages the information into UDP data and sends the UDP data to the SDN controller. The invention can improve the data transmission efficiency under the high-speed network environment.

Description

Shortest route implementation method based on FPGA

Technical Field

The invention relates to the technical field of internet, in particular to a shortest route implementation method based on an FPGA (field programmable gate array).

Background

With the rapid development of network technologies and the emergence of massive data processing technologies such as cloud computing and big data, the traditional switching equipment cannot meet the requirements of current network data transmission and performance. The SDN (software defined network) separates forwarding and control, and can flexibly control the forwarding at the same time. However, the centralized SDN control method facilitates network data transmission, and meanwhile, there is a problem that when the network is complex, the network structure of the SDN becomes very large, so that a single controller cannot efficiently control forwarding of data by a switch. The use of a plurality of controllers to control a relatively simple network can reduce the stress on each controller, but there are a series of problems such as topology synchronization and transmission path selection.

Disclosure of Invention

The invention aims to solve the problems of cooperation among a plurality of controllers and data transmission efficiency, and provides a shortest route implementation method based on an FPGA (field programmable gate array).

In order to solve the problems, the invention is realized by the following technical scheme:

a shortest routing implementation method based on FPGA comprises the following steps:

step 1, uploading topology information to an FPGA by an SDN controller;

step 2, the FPGA receives topology information uploaded by each SDN controller, a memory address is obtained according to a source transponder in each piece of topology information, each source transponder corresponds to a storage space of 1 DDR2, and each piece of topology information is stored into a DDR2 storage space corresponding to the source transponder in each piece of topology information one by one; that is, topology information having the same source repeater is stored in the same memory space of the DDR2, and topology information having different source repeaters is stored in different memory spaces of the DDR 2;

step 3, a user initiates an access request, and the SDN controller receives the request and uploads request information to the FPGA;

step 4, the FPGA receives user request information, and obtains a memory address according to the source forwarders of the request information, each source forwarder corresponds to 1 DDR2 storage space, and the storage space of the DDR2 corresponding to the source forwarders in the request information is accessed;

step 5, the FPGA extracts all topology information of the same storage space in the DDR2, adds the weight values in the topology information to the weight values of the source forwarders corresponding to the storage space from the source forwarder in the request information to the current DDR2 to obtain the weight values of the target forwarders in all the topology information from the source forwarder in the request information to the storage space of the current DDR2, and finds out the updated shortest path;

step 6, the FPGA judges whether the destination transponder of the shortest path found in the step 5 is the destination transponder in the request information; if yes, entering step 7; otherwise, the target transponder in the found shortest path is used as a new source transponder, a memory address is obtained according to the new source transponder, each source transponder corresponds to 1 DDR2 storage space, the DDR2 storage space corresponding to the memory address is accessed, and the step 5 is carried out;

and 7, generating path information of the shortest path by the FPGA, and sending the path information to each SDN controller.

In the above method, the topology information includes a source forwarder, a source port number, a destination forwarder, a destination port number, and a performance weight of the link.

In the above method, the request information includes a source forwarder, a source port number, a destination forwarder, and a destination port number.

In the step 5, a Dijkstra algorithm is used for the performance weight of the link to find out the shortest path among the paths.

In the method, the memory address is composed of a high-order address and a low-order address, the high-order address is the ID of the source transponder, and the low-order address is dynamically changed according to the number of topology information stored in the memory space.

In the method, the memory space of the DDR2 is composed of memory cells of DDR2 corresponding to all memory addresses with the higher order address in the same memory address.

Compared with the prior art, the invention has the beneficial effects that: the invention can utilize the FPGA to realize the network topology synchronization under the high-speed network environment through the coordination of the SDN controller, accelerate the data transmission and reduce the influence on the network performance caused by the decision and configuration on the transmission link performance.

Drawings

Fig. 1 is an overall flow chart of the shortest routing algorithm implemented by the present invention.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is further described in detail below with reference to the accompanying drawings in conjunction with specific examples.

A shortest route implementation method based on FPGA, as shown in fig. 1, specifically includes the following steps:

step S1: the SDN controller packages topology information through a UDP protocol and transmits the topology information upwards to the FPGA, wherein the topology information comprises src _ Switch (source Switch), src _ Port (source Port number), dst _ Switch (destination Switch), dst _ Port (destination Port number) and weight;

step S2: the FPGA receives UDP data sent by each SDN controller, decapsulates the UDP data to extract topology information, uses src _ Switch as an address RAM1_ addr (address of on-chip RAM 1) of the RAM1, and reads write _ addr corresponding to the RAM 1;

step S21: write _ addr is used as a lower 8-bit write address of DDR2_ addr (DDR2 address), the address is added with update RAM1 data, src _ Switch is used as an upper 8-bit write address of DDR2_ addr, the middle 11 bits are 0, topology information is used as DDR2_ data [39:0], 88'd 1234 is used as the basis for judging the topology information and is stored into DDR2_ data [127:40] and is also stored into DDR 2;

step S3: a user initiates an access request, a switch uploads user information to an SDN controller through an openflow protocol, the SDN controller receives the request, the controller packages topology information through a UDP protocol, and uploads request information to an FPGA (a source forwarder, a source port number, a target forwarder and a target port number);

step S4: the FPGA receives UDP data sent by the SDN controller, decapsulates the UDP data and extracts user request information, wherein the request information comprises src _ Switch, src _ Port, dst _ Switch and dst _ Port;

step S5: taking src _ Switch as the upper 8-bit address of DDR2_ addr, taking read _ addr as the lower 7-bit address of DDR2_ addr, and taking 0 from the middle 11 bits to obtain data in DDR 2;

step S51: judging whether the data is topology information data, namely judging whether ddr2_ data [127:40] is equal to 1234, if so, going to step S52, and if not, going to step S6;

step S52: read the data in RAM2 with dst _ Switch as RAM2_ addr (address of on-chip RAM 2);

step S53: adding weight in the topology information and the weight of the path and S, comparing the sum with the weight in the read data, and storing the data with smaller weight into a RAM 2;

step S54: the read _ addr is increased and the step S5 is repeated;

step S6: and acquiring the shortest path (namely the highest bit is 0) in the failed paths in the RAM2, and judging whether RAM2_ addr is the target switch in the user request information. If so, the step S7 is entered, otherwise, the highest position in the data is 1, src _ Switch is made equal to ddr2_ addr, the weight and S are updated to the weight in the shortest path, and the step S5 is repeated;

step S7: adding the data read from the RAM2 into UDP data to be sent, judging whether src _ Switch in the RAM2 data is a user source Switch or not, and if so, constructing a UDP data packet and sending path information to each Switch. Otherwise, go to step S8;

step S8: step S7 is repeated with src _ Switch of the RAM2 data as RAM2_ addr.

According to the invention, by utilizing the high-speed concurrency characteristic of the FPGA, the SDN controller uploads the topology information through a UDP protocol, and the FPGA analyzes the UDP data packet to obtain the topology information which is stored in the DDR 2. When a user initiates an access request, the access DDR2 obtains the topology information and obtains the optimal transmission path information through the shortest routing algorithm, packages the information into UDP data and sends the UDP data to the SDN controller. The invention can improve the data transmission efficiency under the high-speed network environment.

It should be noted that, although the above-mentioned embodiments of the present invention are illustrative, the present invention is not limited thereto, and thus the present invention is not limited to the above-mentioned embodiments. Other embodiments, which can be made by those skilled in the art in light of the teachings of the present invention, are considered to be within the scope of the present invention without departing from its principles.

Claims

1. A shortest route implementation method based on FPGA is characterized by comprising the following steps:

step 1, uploading topology information to an FPGA by an SDN controller;

step 2, the FPGA receives topology information uploaded by each SDN controller, and then obtains an address of a corresponding memory according to a source repeater in each piece of topology information, so that the source repeater in each piece of topology information corresponds to a storage space of 1 DDR2, and then stores each piece of topology information into a DDR2 storage space corresponding to the source repeater in each piece of topology information, so that topology information with the same source repeater is stored in the same storage space of the DDR2, and topology information with different source repeaters is stored in different storage spaces of the DDR 2;

step 4, the FPGA receives the user request information, and then obtains the address of a corresponding memory according to the source transponder of the request information, so that the source transponder in each request information corresponds to the storage space of 1 DDR2, and then accesses the storage space of the DDR2 corresponding to the source transponder in the request information, and takes the storage space as the current source transponder of the shortest path;

step 5, the FPGA extracts all topology information of the same storage space in the DDR2 corresponding to the current source transponder of the shortest path, then adds the weight values in the topology information and the weight values of the source transponder in the request information to the source transponder corresponding to the storage space of the current DDR2, namely the current source transponder of the shortest path, obtains the weight values of the target transponders in all topology information in the storage space from the source transponder in the request information to the current DDR2, namely the weight value sum, and then finds out the target transponder of the topology information with the smallest weight value and the smallest weight value to serve as the current target transponder of the shortest path;

step 6, the FPGA judges whether the current destination transponder of the shortest path found in the step 5 is the destination transponder in the request information; if yes, entering step 7; otherwise, the current destination transponder of the found shortest path is taken as the current source transponder of the new shortest path, and the step 5 is carried out;

2. The FPGA-based shortest route implementation method of claim 1, wherein said topology information comprises a source forwarder, a source port number, a destination forwarder, a destination port number, and a performance weight of said link.

3. The FPGA-based shortest route implementation method of claim 1, wherein the request information comprises a source forwarder, a source port number, a destination forwarder and a destination port number.

4. The method as claimed in claim 1, wherein in step 5, Dijkstra algorithm is applied to the performance weight of the link to find the shortest path among the paths.

5. The FPGA-based shortest routing implementation method of claim 1, wherein the memory address is composed of a higher address and a lower address, the higher address is the ID of the source forwarder, and the lower address is dynamically changed according to the number of topology information already stored in the memory space.

6. The FPGA-based shortest route implementation method of claim 1 or 5, wherein the storage space of DDR2 is composed of DDR2 storage units corresponding to all the memory addresses with the higher order address in the same memory address.