CN111669173A - Timestamp phase discrimination method and device - Google Patents
Timestamp phase discrimination method and device Download PDFInfo
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- CN111669173A CN111669173A CN202010432070.XA CN202010432070A CN111669173A CN 111669173 A CN111669173 A CN 111669173A CN 202010432070 A CN202010432070 A CN 202010432070A CN 111669173 A CN111669173 A CN 111669173A
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- 230000015654 memory Effects 0.000 claims description 17
- 238000001514 detection method Methods 0.000 claims description 14
- 230000001360 synchronised effect Effects 0.000 claims description 7
- 238000009825 accumulation Methods 0.000 claims description 4
- 238000004364 calculation method Methods 0.000 description 4
- 238000004590 computer program Methods 0.000 description 4
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
- H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
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Abstract
The method comprises the steps that a system clock output by an oscillating circuit is used as an input clock of a time-to-digital converter in a phase discriminator; stamping a time stamp on the input clock, and determining the phase difference between a local clock and the input clock according to the time stamp; and adjusting the frequency of the system clock output by the oscillation circuit according to the phase difference, and adjusting the input clock of the digital converter according to the adjusted frequency of the output system clock. The frequency stability of the local clock and the input clock is ensured, thereby reducing the error of the input clock, improving the phase discrimination accuracy and greatly reducing the cost.
Description
Technical Field
The present application relates to the field of signal processing, and in particular, to a method and apparatus for timestamp phase discrimination.
Background
The traditional phase discriminator adopts a high-frequency clock to input and feed back clocks, but the scheme is limited by the reference clock frequency of a counter, and the single-time phase discrimination precision is difficult to improve; when a Digital converter (TDC) is used, since a TDC reference clock or a reference clock of a counter generally uses a clock asynchronous to a reference source, measurement has an error, and particularly, the error is large under a condition that a low-frequency input clock has a large difference. There are schemes that use 2-to-Digital converters (TDCs), but the cost of such schemes is relatively high.
Disclosure of Invention
An object of the present application is to provide a method and an apparatus for timestamp phase discrimination, which solve the problems of low phase discrimination accuracy, large measurement error and relatively high cost in the prior art.
According to an aspect of the present application, there is provided a method of time stamp phase detection, the method comprising:
taking a system clock output by the oscillating circuit as an input clock of a time-to-digital converter in the phase discriminator;
stamping a time stamp on the input clock, and determining the phase difference between a local clock and the input clock according to the time stamp;
and adjusting the frequency of the system clock output by the oscillation circuit according to the phase difference, and adjusting the input clock of the digital converter according to the adjusted frequency of the output system clock.
Further, timestamping the input clock, comprising:
and accumulating according to the period of the input clock, and determining the timestamp carried by each rising edge in the input clock correspondingly.
Further, accumulating according to the period of the input clock, and determining the timestamp carried by each rising edge in the input clock includes:
determining a reference timestamp according to the period of the input clock;
and generating a timestamp carried by each rising edge correspondingly in the phase discriminator according to the period of the self-accumulation of the reference timestamps.
Further, determining a phase difference of a local clock and the input clock according to the timestamp, comprising:
acquiring a reference input timestamp determined when a rising edge of a local reference input clock reaches the time-to-digital converter;
and determining the phase difference between the local clock and the input clock according to the timestamp correspondingly carried by each rising edge and the reference timestamp.
Further, determining a phase difference between a local clock and the input clock according to the timestamp correspondingly carried by each rising edge and the reference timestamp, including:
synchronizing the timestamp correspondingly carried by the first rising edge with the first reference timestamp;
and calculating the time difference between the timestamp correspondingly carried by each synchronized rising edge and the reference timestamp, and determining the phase difference between the local clock and the input clock according to the time difference.
According to another aspect of the present application, there is also provided a system for timestamp detection, the system comprising:
an oscillating circuit, a phase discriminator, the phase discriminator includes a digital converter,
the oscillation circuit is used for inputting a system clock output by the oscillation circuit to the phase discriminator, and the digital converter is used for taking the acquired system clock as an input clock;
the phase discriminator is used for stamping a timestamp on the input clock and determining the phase difference between the local clock and the input clock according to the timestamp;
the oscillation circuit is used for adjusting the frequency of the output system clock of the oscillation circuit according to the phase difference and adjusting the input clock of the digital converter according to the adjusted frequency of the output system clock.
According to yet another aspect of the present application, there is also provided an apparatus for time stamp phase detection, the apparatus comprising:
one or more processors; and
a memory storing computer readable instructions that, when executed, cause the processor to perform the operations of the method as previously described.
According to yet another aspect of the present application, there is also provided a computer readable medium having computer readable instructions stored thereon, the computer readable instructions being executable by a processor to implement the method as described above.
Compared with the prior art, the system clock output by the oscillating circuit is used as the input clock of the time-to-digital converter in the phase discriminator; stamping a time stamp on the input clock, and determining the phase difference between a local clock and the input clock according to the time stamp; and adjusting the frequency of the system clock output by the oscillation circuit according to the phase difference, and adjusting the input clock of the digital converter according to the adjusted frequency of the output system clock. The frequency stability of the local clock and the input clock is ensured, thereby reducing the error of the input clock, improving the phase discrimination accuracy and greatly reducing the cost.
Drawings
Other features, objects and advantages of the present application will become more apparent upon reading of the following detailed description of non-limiting embodiments thereof, made with reference to the accompanying drawings in which:
fig. 1 illustrates a flow diagram of a method of timestamp detection provided in accordance with an aspect of the present application;
fig. 2 shows a schematic diagram of a framework of a phase detection system in an embodiment of the present application;
fig. 3 is a schematic diagram illustrating a system for timestamp detection according to another aspect of the present application.
The same or similar reference numbers in the drawings identify the same or similar elements.
Detailed Description
The present application is described in further detail below with reference to the attached figures.
In a typical configuration of the present application, the terminal, the device serving the network, and the trusted party each include one or more processors (e.g., Central Processing Units (CPUs)), input/output interfaces, network interfaces, and memory.
The Memory may include volatile Memory in a computer readable medium, Random Access Memory (RAM), and/or nonvolatile Memory such as Read Only Memory (ROM) or flash Memory (flash RAM). Memory is an example of a computer-readable medium.
Computer-readable media, including both non-transitory and non-transitory, removable and non-removable media, may implement information storage by any method or technology. The information may be computer readable instructions, data structures, modules of a program, or other data. Examples of computer storage media include, but are not limited to, Phase-Change RAM (PRAM), Static Random Access Memory (SRAM), Dynamic Random Access Memory (DRAM), other types of Random Access Memory (RAM), Read Only Memory (ROM), Electrically Erasable Programmable Read-Only Memory (EEPROM), flash Memory or other Memory technology, Compact Disc Read-Only Memory (CD-ROM), Digital Versatile Disc (DVD) or other optical storage, magnetic cassette tape, magnetic tape storage or other magnetic storage devices, or any other non-transmission medium that can be used to store information that can be accessed by a computing device. As defined herein, computer readable media does not include non-transitory computer readable media (transmyedia), such as modulated data signals and carrier waves.
Fig. 1 illustrates a schematic flow chart of a method for timestamp detection provided in accordance with an aspect of the present application, the method including: step S11 to step S13,
in step S11, the system clock output by the oscillation circuit is used as the input clock of the time-to-digital converter in the phase detector; here, the phase detection system shown in fig. 2 includes a phase detector, a low pass filter, and an oscillation circuit (VCO/NCO), where the phase detector includes a time-to-digital converter (TDC), and a clock output by the system is used as a working clock of the TDC, where the clock output by the system is the clock output by the oscillation circuit for the first time, the clock output by the system is the clock fed back to the TDC by the oscillation circuit according to the clock output after the TDC phase detection, and the working clock is an input clock of the TDC, and the system clock is provided to the TDC by using a phase-locked loop, so as to avoid a problem of a large error of the output clock of the oscillation circuit when the oscillation frequency is low.
Next, in step S12, the input clock is time-stamped, and the phase difference between the local clock and the input clock is determined according to the time stamp; here, an input clock obtained from the oscillation circuit is time-stamped, and the phase difference between the local clock and the input clock is calculated using the time stamp. Subsequently, in step S13, the frequency of the oscillation circuit output system clock is adjusted according to the phase difference, and the input clock of the digital converter is adjusted according to the adjusted frequency of the output system clock. The frequency difference obtained by the phase difference calculation is used for adjusting the frequency output by the oscillation circuit, the adjusted system clock is used as the input clock of the TDC again, the input clock of the TDC is adjusted, and the phase difference between the local clock and the input clock is continuously adjusted, so that the frequency stability of the local clock and the input reference clock is ensured.
In an embodiment of the present application, in step S12, the input clock is accumulated according to the period of the input clock, and a timestamp carried by each rising edge in the input clock is determined. Here, it is preferable that the input clock is time-stamped for each rising edge of the input clock, and the time signal is processed by the low-pass filter and then input to the oscillation circuit when the input clock reaches the rising edge. Specifically, the period of the input clock is determined, and then the period is accumulated, and the timestamp carried by each rising edge is calculated.
Further, determining a reference timestamp according to the period of the input clock; and generating a timestamp carried by each rising edge correspondingly in the phase discriminator according to the period of the self-accumulation of the reference timestamps. Here, as shown in fig. 2, the reference timestamp is tod _ ref, for example, if the input clock frequency is 8kHz, the period is 125us, the reference timestamp tod _ ref determined according to the period is 125us, and the phase discriminator obtains the timestamp carried by each rising edge according to the tod _ ref self-accumulation period, that is, tod _ timestamp ═ tod _ timestamp + tod _ ref. The input clock is a pulse signal, when the period of the next pulse changes, the corresponding reference time stamp also changes, the time stamp of each rising edge in the period of the next pulse is also adjusted, and the error of time stamp caused by the difference of pulse periods is avoided.
Next, in step S12, a reference input timestamp determined when the rising edge of the local reference input clock reaches the time-to-digital converter is acquired; and determining the phase difference between the local clock and the input clock according to the timestamp correspondingly carried by each rising edge and the reference timestamp. Here, when the phase difference between the local clock and the input clock is calculated, a reference input Timestamp (Ref _ Timestamp) when the rising edge of the local reference input clock reaches the TDC can be determined, and the Timestamp obtained from the TDC is a Timestamp obtained with reference to the local system output clock.
According to the embodiment, the timestamp carried correspondingly by the first rising edge is synchronized with the first reference timestamp; and calculating the time difference between the timestamp correspondingly carried by each synchronized rising edge and the reference timestamp, and determining the phase difference between the local clock and the input clock according to the time difference. In order to facilitate calculation, a Timestamp carried by a first rising edge correspondingly is synchronized with a first reference Timestamp, that is, the first time tod _ Timestamp is synchronized with Ref _ Timestamp, so that the values of the first time tod _ Timestamp and Ref _ Timestamp are relatively small, and calculation is facilitated; and then, calculating the time difference between the Timestamp (tod _ Timestamp) correspondingly carried by each synchronized rising edge and Ref _ Timestamp, and further calculating the phase difference between the local clock and the TDC input clock by using the time difference.
Fig. 3 is a schematic structural diagram of a system for timestamp detection according to another aspect of the present application, where the system includes: the phase detector 12 comprises an oscillating circuit 11 and a phase detector 12, wherein the phase detector 12 comprises a digital converter 13, the oscillating circuit 11 is used for inputting a system clock output by the oscillating circuit 11 to the phase detector 12, and the digital converter 13 is used for taking the obtained system clock as an input clock; the phase discriminator 12 is configured to stamp the input clock with a timestamp, and determine a phase difference between the local clock and the input clock according to the timestamp; the oscillation circuit 11 is configured to adjust a frequency of an output system clock of the oscillation circuit according to the phase difference, and adjust an input clock of the digital converter according to the adjusted frequency of the output system clock. Here, an input clock obtained from the oscillation circuit is time-stamped, and the phase difference between the local clock and the input clock is calculated using the time stamp. And the frequency difference obtained by phase difference calculation is used for adjusting the frequency output by the oscillating circuit, the adjusted system clock is used as the input clock of the TDC again, the input clock of the TDC is adjusted, and the phase difference between the local clock and the input clock is continuously adjusted so as to ensure the frequency stability of the local clock and the input reference.
Furthermore, an embodiment of the present application further provides a computer readable medium, on which computer readable instructions are stored, where the computer readable instructions are executable by a processor to implement the aforementioned method for timestamp phase detection.
In an embodiment of the present application, there is also provided an apparatus for timestamp detection, including:
one or more processors; and
a memory storing computer readable instructions that, when executed, cause the processor to perform the operations of the method as previously described.
For example, the computer readable instructions, when executed, cause the one or more processors to:
taking a system clock output by the oscillating circuit as an input clock of a time-to-digital converter in the phase discriminator;
stamping a time stamp on the input clock, and determining the phase difference between a local clock and the input clock according to the time stamp;
and adjusting the frequency of the system clock output by the oscillation circuit according to the phase difference, and adjusting the input clock of the digital converter according to the adjusted frequency of the output system clock.
It will be apparent to those skilled in the art that various changes and modifications may be made in the present application without departing from the spirit and scope of the application. Thus, if such modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is intended to include such modifications and variations as well.
It should be noted that the present application may be implemented in software and/or a combination of software and hardware, for example, implemented using Application Specific Integrated Circuits (ASICs), general purpose computers or any other similar hardware devices. In one embodiment, the software programs of the present application may be executed by a processor to implement the steps or functions described above. Likewise, the software programs (including associated data structures) of the present application may be stored in a computer readable recording medium, such as RAM memory, magnetic or optical drive or diskette and the like. Additionally, some of the steps or functions of the present application may be implemented in hardware, for example, as circuitry that cooperates with the processor to perform various steps or functions.
In addition, some of the present application may be implemented as a computer program product, such as computer program instructions, which when executed by a computer, may invoke or provide methods and/or techniques in accordance with the present application through the operation of the computer. Program instructions which invoke the methods of the present application may be stored on a fixed or removable recording medium and/or transmitted via a data stream on a broadcast or other signal-bearing medium and/or stored within a working memory of a computer device operating in accordance with the program instructions. An embodiment according to the present application comprises an apparatus comprising a memory for storing computer program instructions and a processor for executing the program instructions, wherein the computer program instructions, when executed by the processor, trigger the apparatus to perform a method and/or a solution according to the aforementioned embodiments of the present application.
It will be evident to those skilled in the art that the present application is not limited to the details of the foregoing illustrative embodiments, and that the present application may be embodied in other specific forms without departing from the spirit or essential attributes thereof. The present embodiments are therefore to be considered in all respects as illustrative and not restrictive, the scope of the application being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein. Any reference sign in a claim should not be construed as limiting the claim concerned. Furthermore, it is obvious that the word "comprising" does not exclude other elements or steps, and the singular does not exclude the plural. A plurality of units or means recited in the apparatus claims may also be implemented by one unit or means in software or hardware. The terms first, second, etc. are used to denote names, but not any particular order.
Claims (8)
1. A method of time stamp phase detection, the method comprising:
taking a system clock output by the oscillating circuit as an input clock of a time-to-digital converter in the phase discriminator;
stamping a time stamp on the input clock, and determining the phase difference between a local clock and the input clock according to the time stamp;
and adjusting the frequency of the system clock output by the oscillation circuit according to the phase difference, and adjusting the input clock of the digital converter according to the adjusted frequency of the output system clock.
2. The method of claim 1, wherein time stamping the input clock comprises:
and accumulating according to the period of the input clock, and determining the timestamp carried by each rising edge in the input clock correspondingly.
3. The method of claim 2, wherein accumulating according to the period of the input clock, and determining the timestamp carried by each rising edge in the input clock comprises:
determining a reference timestamp according to the period of the input clock;
and generating a timestamp carried by each rising edge correspondingly in the phase discriminator according to the period of the self-accumulation of the reference timestamps.
4. The method of claim 2, wherein determining a phase difference between a local clock and the input clock based on the timestamp comprises:
acquiring a reference input timestamp determined when a rising edge of a local reference input clock reaches the time-to-digital converter;
and determining the phase difference between the local clock and the input clock according to the timestamp correspondingly carried by each rising edge and the reference timestamp.
5. The method according to claim 4, wherein determining the phase difference between the local clock and the input clock according to the timestamp carried by each rising edge and the reference timestamp comprises:
synchronizing the timestamp correspondingly carried by the first rising edge with the first reference timestamp;
and calculating the time difference between the timestamp correspondingly carried by each synchronized rising edge and the reference timestamp, and determining the phase difference between the local clock and the input clock according to the time difference.
6. A system for time stamp phase detection, the system comprising:
an oscillating circuit, a phase discriminator, the phase discriminator includes a digital converter,
the oscillation circuit is used for inputting a system clock output by the oscillation circuit to the phase discriminator, and the digital converter is used for taking the acquired system clock as an input clock;
the phase discriminator is used for stamping a timestamp on the input clock and determining the phase difference between the local clock and the input clock according to the timestamp;
the oscillation circuit is used for adjusting the frequency of the output system clock of the oscillation circuit according to the phase difference and adjusting the input clock of the digital converter according to the adjusted frequency of the output system clock.
7. An apparatus for time stamp phase discrimination, the apparatus comprising:
one or more processors; and
memory storing computer readable instructions that, when executed, cause the processor to perform the operations of the method of any of claims 1 to 5.
8. A computer readable medium having computer readable instructions stored thereon which are executable by a processor to implement the method of any one of claims 1 to 5.
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| CN202010432070.XA CN111669173A (en) | 2020-05-20 | 2020-05-20 | Timestamp phase discrimination method and device |
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| CN202010432070.XA CN111669173A (en) | 2020-05-20 | 2020-05-20 | Timestamp phase discrimination method and device |
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2020
- 2020-05-20 CN CN202010432070.XA patent/CN111669173A/en active Pending
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| DE102014109471A1 (en) * | 2014-07-07 | 2016-01-07 | Lear Corporation Gmbh | Clock recovery with frequency synchronization |
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