CN111653665B - ZnO-Li resistive random access memory and integrated manufacturing process method thereof - Google Patents

ZnO-Li resistive random access memory and integrated manufacturing process method thereof Download PDF

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CN111653665B
CN111653665B CN201910839059.2A CN201910839059A CN111653665B CN 111653665 B CN111653665 B CN 111653665B CN 201910839059 A CN201910839059 A CN 201910839059A CN 111653665 B CN111653665 B CN 111653665B
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layer
random access
resistive random
access memory
resistance change
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CN111653665A (en
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赵晓锋
李易
温殿忠
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Heilongjiang University
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Heilongjiang University
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
    • H10B63/80—Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/011—Manufacture or treatment of multistable switching devices
    • H10N70/021—Formation of the switching material, e.g. layer deposition
    • H10N70/026—Formation of the switching material, e.g. layer deposition by physical vapor deposition, e.g. sputtering
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/881—Switching materials
    • H10N70/883—Oxides or nitrides
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/881—Switching materials
    • H10N70/883—Oxides or nitrides
    • H10N70/8833—Binary metal oxides, e.g. TaOx

Abstract

The invention discloses a resistive random access memory and an integrated manufacturing process method thereof, wherein the resistive random access memory comprises a substrate (1) and one or more resistive random access units arranged on the substrate, wherein each resistive random access unit comprises a bottom electrode (2), a resistive layer (3) and a top electrode (4) which are sequentially arranged, and the resistive layer (3) is a Li-doped ZnO film (ZnO: Li), so that the performance of the resistive random access memory is remarkably improved, and the resistive random access memory has long retention time and excellent durability. The integrated manufacturing process method combines the radio frequency magnetron sputtering method and the stripping process, realizes the integrated process manufacturing of the chip, has simple operation, can realize the large-area, high-consistency and integrated manufacturing of the resistive random access memory, and reduces the manufacturing cost.

Description

ZnO-Li resistive random access memory and integrated manufacturing process method thereof
Technical Field
The invention relates to the technical field of memories, in particular to a ZnO-Li resistive random access memory and an integrated manufacturing process method thereof.
Background
With the advent of the big data era and artificial intelligence, a new challenge is presented to a memory with a traditional Metal Oxide Semiconductor (MOS) structure, and the practical requirements of the traditional memory technology represented by a flash memory are difficult to meet due to the factors of low read-write speed, low storage density, high power consumption, short data retention time and the like. In order to meet data storage requirements, recently, ferroelectric memories (ferams), magnetic memories (MRAMs), phase change memories (PRAMs), Resistive Random Access Memories (RRAMs), and the like have been receiving attention. The resistive random access memory has the advantages of low power consumption, high storage density, excellent durability and the like, particularly has the advantages which are difficult to compare with the memory with the traditional structure in the field of simulating artificial neural networks and the like, and is easy to become the most powerful competitor in the new-generation nonvolatile memory.
The resistive random access memory realizes data storage by utilizing two or more different resistance states of certain thin film materials under the action of an external electric field, and is a novel nonvolatile memory which is widely concerned in academia and industry in recent years. The resistive random access memory has the advantages of high storage density, high erasing and writing speed, high repeated erasing and writing frequency, three-dimensional storage, multi-value storage and the like, and the storage potential shown as the next generation of nonvolatile memory greatly exceeds that of other nonvolatile memories.
The basic structure of the resistive random access memory comprises two layers of conductive electrode materials and one layer of semiconductor (or insulating) storage medium material. The dielectric material is a carrier for resistance transformation of the resistive random access memory and has the most direct influence on the performance of the resistive random access memory.
The existing resistive random access memory has unstable performance and directly influences the resistance values and erasing voltages of high and low resistance states of the resistive random access memory, so that the phenomena of misreading and misreading occur, the reliability of data is influenced, and the practical application of the resistive random access memory is further influenced.
Therefore, it is necessary to provide a resistive random access memory having a relatively high switching ratio and excellent retention and durability, and an integrated manufacturing process thereof.
Disclosure of Invention
In order to overcome the problems, the inventor of the present invention has made intensive studies to design a resistive random access memory using a Li-doped ZnO thin film as a resistive layer and an integrated manufacturing process thereof, wherein the resistive random access memory can effectively improve the on-off ratio of the resistive random access memory by doping Li element into the ZnO thin film, and significantly improve the stability of the resistive random access memory, so that the resistive random access memory has a long retention time and excellent durability; the method has the advantages that the integrated process manufacturing of the chip is realized by combining the radio frequency magnetron sputtering method and the stripping process, the operation is simple, the large-area, high-consistency and integrated manufacturing of the resistive random access memory can be realized, more memory units can be formed on the substrate, and the manufacturing cost is obviously reduced, so that the method is completed.
Specifically, the present invention aims to provide the following:
in a first aspect, there is provided a resistive random access memory comprising a substrate 1 and one or more resistive cells disposed thereon, wherein,
the resistance change unit comprises a bottom electrode 2, a resistance change layer 3 and a top electrode 4 which are sequentially arranged, wherein the resistance change layer 3 is a Li-doped ZnO thin film (ZnO: Li).
In a second aspect, there is provided a method for integrated manufacturing process of the memory according to the first aspect, wherein the method includes the following steps:
step 1, oxidizing for the first time, cleaning a substrate, and growing a first silicon dioxide layer 5;
step 2, performing first photoetching, namely spin-coating a bottom layer and a positive photoresist on the upper surface of the first silicon dioxide layer 5, and photoetching to form a bottom electrode window;
step 3, preparing a bottom electrode by adopting a magnetron sputtering method;
step 4, stripping for the first time to realize the imaging of the bottom electrode;
step 5, oxidizing for the second time, and growing a second silicon dioxide layer 6 on the first silicon dioxide layer 5;
step 6, carrying out second photoetching to etch the second silicon dioxide layer 6, forming a resistance layer window and a bottom electrode pressure welding point window on the bottom electrode, and removing the photoresist;
step 7, carrying out third photoetching to form a resistance change layer pattern;
step 8, preparing a resistance change layer on the photoetching pattern by using a radio frequency magnetron sputtering method;
step 9, stripping for the second time to form the resistance change layer 3;
step 10, photoetching for the fourth time to form a top electrode pattern, and preparing a top electrode layer by adopting a magnetron sputtering method;
step 11, stripping for the third time to form a top electrode 4;
step 12, oxidizing for the third time to grow a silicon dioxide passivation layer 7;
and step 13, photoetching the silicon dioxide passivation layer 7 for the fifth time to form a pressure welding point.
In a third aspect, a resistive random access memory prepared by the method of the second aspect is provided.
The invention has the advantages that:
(1) according to the resistive random access memory provided by the invention, the resistive layer is the Li-doped ZnO film, and the high-resistance value of the resistive random access memory is better changed through impurity compensation, so that the on-off ratio is improved;
(2) the integrated manufacturing process method of the resistive random access memory provided by the invention is simple to operate, low in cost, easy to realize miniaturization and integration of the resistive random access memory unit and suitable for large-scale industrial application;
(3) the integrated manufacturing process method of the resistive random access memory provided by the invention realizes the integrated process manufacturing of the resistive random access memory by combining the radio frequency magnetron sputtering method and the stripping process, so that the switching ratio of the prepared resistive random access memory is up to 106Retention of up to 104s, pulse durability up to 103Next, the process is carried out.
Drawings
Fig. 1 is a schematic view showing an overall structure of a resistance change memory according to a preferred embodiment of the present invention;
fig. 2 is a schematic diagram illustrating a top view structure of a resistance change memory according to a preferred embodiment of the present invention;
FIG. 3 shows a cross-sectional view A-A' of a preferred embodiment of the present invention;
fig. 4-1 to 4-6 show a flow chart of a manufacturing process of a resistive random access memory according to a preferred embodiment of the present invention;
fig. 5 shows a current-voltage characteristic curve diagram of the resistive random access memory in different oxygen-argon ratios during the preparation process in the experimental example of the present invention;
fig. 6 shows a current-voltage characteristic curve of a resistive random access memory with different Li doping concentrations in an experimental example of the present invention;
fig. 7-1 shows a plurality of repeatedly detected current-voltage curves of the resistance change memory at an annealing temperature of 200 ℃ in the experimental example of the present invention;
fig. 7-2 shows a plurality of repeatedly detected current-voltage curves of the resistive random access memory at an annealing temperature of 300 ℃ in the experimental example of the present invention;
fig. 7-3 show a plurality of repeatedly detected current-voltage curves of the resistive random access memory at an annealing temperature of 400 ℃ in the experimental example of the present invention;
fig. 8 shows a plurality of repeatedly detected current-voltage curves of the resistance change memory in embodiment 1 of the present invention;
fig. 9 is a graph showing a result of a retention characteristic test of the resistance change memory in embodiment 1 of the invention;
fig. 10 is a graph showing the results of the endurance test of the resistance change memory in example 1 of the present invention.
The reference numbers illustrate:
1-a substrate;
2-a bottom electrode;
21-Ti layer;
a 22-Pt layer;
3-a resistance change layer;
4-a top electrode;
5-a first silicon dioxide layer;
6-a second silicon dioxide layer;
7-silicon dioxide passivation layer.
Detailed Description
The invention is explained in more detail below with reference to the figures and examples. The features and advantages of the present invention will become more apparent from the description. In which, although various aspects of the embodiments are shown in the drawings, the drawings are not necessarily drawn to scale unless specifically indicated.
The inventor finds that the materials which can be used for the resistive random access memory medium layer are very many, and mainly comprise binary metal oxides, multi-element oxides, high molecular organic materials and the like. In a plurality of resistive switching medium materials, ZnO is used as a direct wide-band-gap semiconductor, the forbidden band width of the ZnO is 3.3eV, the ZnO has excellent photoelectric performance, the cost is low, and the preparation process is mature.
Therefore, the present invention provides a Resistive Random Access Memory (RRAM) comprising a substrate 1 and a single or a plurality of RRAM cells disposed thereon, as shown in FIGS. 1 to 3, wherein,
the resistance change unit comprises a bottom electrode 2, a resistance change layer 3 and a top electrode 4 which are sequentially arranged, wherein the resistance change layer 3 is a Li-doped ZnO thin film (ZnO: Li).
Wherein the plurality of resistive switching units are arranged in a crisscross array.
According to a preferred embodiment of the invention, the substrate 1 is a monocrystalline silicon substrate, on the upper surface of which a first layer of silicon dioxide 5 is provided, having a thickness of between 300nm and 500nm, preferably 400 nm.
In a more preferred embodiment, a second silicon dioxide layer 6 is provided on the upper surface of the first silicon dioxide layer 5, and the thickness of the second silicon dioxide layer 6 is 250nm to 350nm, preferably 280nm to 300 nm.
According to a preferred embodiment of the present invention, the bottom electrode 2 is disposed on the upper surface of the first silicon dioxide layer 5, and comprises an adhesion layer of titanium (Ti) 21 and a platinum (Pt) layer 22 disposed from bottom to top,
the thickness of the Ti layer 21 is 10 nm-60 nm, preferably 30 nm-40 nm;
the thickness of the Pt layer 22 is 50nm to 150nm, preferably 80nm to 100 nm.
Wherein, the purity of the Ti layer is 99.995 percent, and the purity of the Pt layer is 99.99 percent.
According to a preferred embodiment of the present invention, the resistance-change layer 3 is disposed on the upper surface of the Pt layer 22, and the doping concentration of Li is 3% to 10%, preferably 4% to 7%, and more preferably 5%.
And the doping concentration of the Li is the mass fraction of the Li in the ZnO.
The inventor researches and discovers that the on-off ratio of the resistive random access memory can be effectively improved and the performance of the resistive random access memory can be remarkably improved by doping Li into the zinc oxide thin film, and the doping concentration is 3-10%, preferably 4-7%, and more preferably 5%, so that the resistive random access memory has excellent retention time and durability.
When the doping concentration of Li is lower than 4%, the performance of the resistive random access memory is not remarkably improved; when the doping concentration of Li is higher than 7%, the resistance change performance of the device becomes poor.
In a further preferred embodiment, the thickness of the resistance change layer 3 is 90nm to 180nm, preferably 120nm to 160nm, and more preferably 130-140 nm.
In the invention, when the thickness of the resistive layer is 90 nm-180 nm, preferably 120 nm-160 nm, and more preferably 130-140nm, the resistive random access memory has high on-off ratio and high stability; when the thickness is less than 90nm, permanent breakdown occurs after a setting voltage is applied, leading to conduction of the upper and lower electrodes, the upper and lower electrodes cannot return to the high resistance state from the low resistance state, when the thickness is greater than 180nm, a higher setting voltage is required, and a conductive filament is difficult to form between the top electrode and the bottom electrode, so that the device is difficult to change from the high resistance state to the low resistance state.
In a further preferred embodiment, the resistance change layer 3 is prepared by a radio frequency magnetron sputtering method.
According to a preferred embodiment of the invention, the top electrode 4 is arranged above the resistive layer 3, preferably on the upper surface of the second silicon dioxide layer 6,
preferably, the top electrode is an Ag electrode with a thickness of 80nm to 150nm, preferably 100nm to 120 nm.
In the present invention, the purity of the Ag electrode was 99.99%.
In a further preferred embodiment, the top electrode 4 is circular or square.
In a further preferred embodiment, the top electrode 4 is circular and has a diameter of 20 μm to 500 μm, preferably 30 μm to 50 μm.
In another preferred embodiment, the top electrode 4 is square with sides of 20 μm to 500 μm, preferably 30 μm to 50 μm.
According to a preferred embodiment of the present invention, as shown in fig. 3, the bottom electrode 2 and the top electrode 4 are in a crisscross structure, and the resistive layer 3 is disposed in an overlapping region of the bottom electrode and the top electrode.
In a further preferred embodiment, the area of the resistance change layer 3 is not smaller than the area of the overlapping region of the bottom electrode and the top electrode, so that there is no contact between the top electrode and the bottom electrode.
According to a preferred embodiment of the invention, a passivation layer 7 of silicon dioxide is provided above the top electrode 4, with a thickness of 100nm to 200nm, preferably 150 nm.
The invention also provides an integrated manufacturing process method of the resistive random access memory, which comprises the following steps of:
step 1, first oxidation, substrate cleaning, and first silicon dioxide layer 5 growth (as shown in fig. 4-1).
In the present invention, it is preferable to use a 4-inch single crystal silicon wafer as a substrate, and to clean the single crystal silicon substrate by the RCA standard cleaning method, the cleaning being performed as follows: the monocrystalline silicon substrate is boiled to be white smoke by concentrated sulfuric acid, is washed by a large amount of deionized water after being cooled, and is washed twice by electronic cleaning liquids No. 1 and No. 2 respectively (the main components and the volume ratio of the No. 1 liquid are ammonia water, hydrogen peroxide and water are 1:1:5, wherein the concentration of the ammonia water is 27 percent, and the concentration of the hydrogen peroxide is 30 percent, and the main components and the volume ratio of the No. 2 liquid are hydrochloric acid, hydrogen peroxide and water are 1:1:5, wherein the concentration of the hydrochloric acid is 37 percent, and the concentration of the hydrogen peroxide is 30 percent), and then is washed by a large amount of deionized water, and finally is put into a spin dryer for spin drying.
According to a preferred embodiment of the invention, the first silicon dioxide layer is grown by a thermal growth method, namely, the cleaned monocrystalline silicon piece is put into a high-temperature oxidation furnace for oxidation, and oxygen is used as a gas source for oxidation growth of the first silicon dioxide layer.
In a further preferred embodiment, the thickness of the first silica layer 5 is 300 to 500nm, preferably 400 nm.
And 2, carrying out first photoetching, namely spin-coating a bottom layer and a positive photoresist on the upper surface of the first silicon dioxide layer 5, and photoetching to form a bottom electrode window.
In the present invention, the photolithography process is a common method in the prior art, and includes spin coating, pre-baking, exposure, development, film hardening, etching, and photoresist stripping.
The type of the primer adopted in the glue homogenizing process is preferably LOR10B, and the type of the positive photoresist adopted is preferably AZ 1500.
And 3, preparing the bottom electrode by adopting a magnetron sputtering method.
Wherein the bottom electrode is a Ti/Pt bottom electrode.
According to a preferred embodiment of the invention, high-purity titanium and high-purity platinum are used as sputtering targets, wherein the high-purity titanium is titanium with the purity of 99.995%, and the diameter is preferably 50.8 mm;
the high-purity platinum is platinum with the purity of 99.99%, and the diameter is preferably 50.8 mm.
In a further preferred embodiment, the power of the Ti sputtering is 80 to 120W, preferably 100W, the sputtering time is 3 to 7min, preferably 5min,
the vacuum degree is 1.0Pa, the sputtering gas is high-purity argon, and the flow rate is 47 sccm;
the power of the Pt sputtering is 85-115W, preferably 100W, the sputtering time is 10-20 min, preferably 15min,
the degree of vacuum was 1.0Pa, and the sputtering gas was high-purity argon gas at a flow rate of 47 sccm.
In a further preferred embodiment, the thickness of the Ti layer 21 obtained is from 10nm to 60nm, preferably from 30nm to 40 nm;
the thickness of the Pt layer 22 is 50nm to 150nm, preferably 80nm to 100 nm.
And 4, stripping for the first time to realize the patterning of the bottom electrode (as shown in figure 4-2).
Specifically, 4-inch monocrystalline silicon is placed in a degumming solution to be soaked to form a bottom electrode pattern, and then is sequentially washed by absolute ethyl alcohol and deionized water and is subjected to spin-drying treatment.
The type of the degumming solution is preferably AZ 400T.
Step 5, a second oxidation, a second silicon dioxide layer 6 is grown on the first silicon dioxide layer 5 (as shown in fig. 4-3).
Wherein, a chemical vapor deposition process is adopted to grow the second silicon dioxide layer.
According to a preferred embodiment of the present invention, the thickness of the second silicon dioxide layer 6 is 250 to 350nm, preferably 280 to 300 nm.
And 6, carrying out second photoetching to etch the second silicon dioxide layer 6, forming a resistance layer window and a bottom electrode pressure welding point window on the bottom electrode, and removing the photoresist.
And 7, carrying out third photoetching to form a resistance change layer pattern.
And 8, preparing the resistance change layer on the photoetching pattern by using a radio frequency magnetron sputtering method.
According to a preferred embodiment of the present invention, the sputtering target is a Li-doped ZnO target, and the doping content of Li is 3% to 10%, preferably 4% to 7%, and more preferably 5%.
Wherein Li in the Li-doped ZnO ceramic target is generalPerLi2CO3Is incorporated into ZnO. The Li-doped ZnO target described in the present invention is custom made by commercial companies, such as: pure ZnO target (D50.8 mm. times.5 mm, purity: 99.99%), Li-doped ZnO target (D50.8 mm. times.5 mm, ZnO/Li)2CO3,95/5wt％,92/8wt％,90/10wt％)。
According to a preferred embodiment of the present invention, the rf magnetron sputtering is performed in a gas atmosphere, and the gas includes argon or a mixed gas of argon and oxygen.
Wherein the purity of the oxygen and the argon is 99.999 percent.
In a further preferred embodiment, the flow ratio of the oxygen gas to the argon gas is (0 to 47) sccm:47 sccm.
In a further preferred embodiment, the flow ratio of oxygen to argon is (10 to 20) sccm:47sccm, preferably 15sccm and 47sccm, for example, the flow rate of oxygen is 15sccm and the flow rate of argon is 47 sccm.
The inventor researches and discovers that when the flow ratio of oxygen to argon is in the range, the resistance change layer film preferentially grows along the (002) crystal face direction, the formed film is uniform and compact, and the prepared resistance change memory has larger switching current ratio and stable resistance change switching characteristics.
According to a preferred embodiment of the present invention, the sputtering gas pressure is 0.1 to 1.2Pa, preferably 0.5 to 1.1Pa, and more preferably 1.0 Pa.
In a further preferred embodiment, the sputtering background vacuum is 1 × 10-4Pa。
The sputtering temperature is 150-300 ℃, preferably 180-250 ℃, and more preferably 200 ℃.
The inventor researches and discovers that the sputtering deposition temperature influences the preferential growth of the resistive layer film, and the preferential growth of the <002> crystal face direction is easy to improve the performance of the resistive random access memory. In the invention, when the sputtering temperature is 150-300 ℃, preferably 180-250 ℃, and more preferably 200 ℃, the resistance change layer film formed by sputtering preferentially grows along the (002) crystal plane direction, and the prepared resistance change memory has larger switching current and more stable resistance change switching characteristics.
And 9, stripping for the second time to form the resistance change layer 3 (shown in figures 4-4).
The method comprises the steps of placing 4-inch monocrystalline silicon in a degumming solution for soaking, forming a resistance change layer through a stripping process, sequentially cleaning with absolute ethyl alcohol and deionized water, and performing spin-drying treatment.
The type of the degumming solution is preferably AZ 400T.
And step 10, photoetching for the fourth time to form a top electrode pattern, and preparing a top electrode layer by adopting a magnetron sputtering method.
According to a preferred embodiment of the present invention, the target material used in the magnetron sputtering is silver (Ag), and the purity of the target material is 99.99%.
In a further preferred embodiment, the degree of vacuum of the magnetron sputtering is > 1X 10-4Pa, the substrate temperature is room temperature, and the working pressure is 1.0 Pa.
In a further preferred embodiment, the magnetron sputtering power is 80-130W, preferably 100W, and the magnetron sputtering time is 8-15 min, preferably 10 min.
Preferably, the sputtering is performed in an inert gas environment, wherein the inert gas is argon, and the flow rate of the argon is 40-55 sccm, preferably 47 sccm.
In a further preferred embodiment, the thickness of the top electrode Ag is 80 to 150nm, preferably 100 to 120 nm.
Step 11, stripping for the third time, and forming the top electrode 4 (as shown in fig. 4-5).
The method comprises the steps of placing 4-inch monocrystalline silicon in a degumming solution for soaking, forming a top electrode (Ag electrode) through a stripping process, sequentially cleaning with absolute ethyl alcohol and deionized water, and performing spin-drying treatment.
The type of the degumming solution is preferably AZ 400T.
And step 12, oxidizing for the third time, and growing a silicon dioxide passivation layer 7.
Wherein, the thickness of the silicon dioxide passivation layer 7 is 100nm to 200nm, preferably 150 nm.
Step 13, a fifth photolithography is performed to lithographically etch the silicon dioxide passivation layer 7 to form a pressure pad (as shown in fig. 4-6).
Wherein the crisscross array is formed by the five times of photoetching, three times of sputtering and three times of stripping processes.
And step 14, cleaning, and forming ohmic contact through alloying treatment.
Wherein the alloying treatment is carried out according to the following operations: and (3) treating for 20-40 min in a vacuum environment at 200-400 ℃, preferably treating for 30min in a vacuum environment at 300 ℃.
In the invention, the alloying treatment is carried out for 20-40 min in a vacuum environment at 200-400 ℃, preferably for 30min in a vacuum environment at 300 ℃, so that the resistive random access memory has stable resistive random access switching characteristics; when the alloying temperature is lower than 200 ℃, the resistance change performance is not obviously changed due to the lower temperature; when the alloying temperature is higher than 400 ℃, the crystallization quality of the film is reduced, and the resistance change performance is poor.
And step 15, spin-coating a photoresist on the sample processed in the step 14 to be used as a scribing protective film, scribing, soaking the chip by adopting an acetone solution, and removing the protective film.
And step 16, bonding and packaging, and testing.
In the invention, the integrated process manufacturing of the resistive random access memory is realized by combining the radio frequency magnetron sputtering method and the stripping process, the process is simple and compatible with a Complementary Metal Oxide Semiconductor (CMOS) process, the large-area, high-consistency and integrated manufacturing of the resistive random access memory can be realized, more memory units can be formed on a substrate, and the cost of the integrated manufacturing process is obviously reduced.
The invention also provides the resistive random access memory prepared by the method.
Examples
Example 1
The ZnO is prepared according to the following steps:
step 1, oxidizing for the first time, adopting a 4-inch monocrystalline silicon wafer as a substrate, cleaning, and growing first SiO by adopting a thermal growth method2Layer thickness 400 nm.
Step 2, first photoetching is carried out on the first SiO2The upper surface of the electrode is processed by a photoetching process to form a Ti/Pt bottom electrode window.
The model of the bottom photoresist adopted in the photoetching process is LOR10B, and the model of the positive photoresist is AZ 1500.
Step 3, preparing a Ti/Pt bottom electrode by using a magnetron sputtering method, wherein high-purity titanium (purity: 99.995%, diameter: 50.8mm) and high-purity platinum (purity: 99.99%, diameter: 50.8mm) are used as sputtering targets, the power of Ti is 100W, and the time is 5 min; the vacuum degree is 1.0Pa, the sputtering gas is Ar, and the flow rate is 47 sccm; the power of Pt is 100W, and the time is 10 min; the degree of vacuum was 1.0Pa, the sputtering gas was Ar, and the flow rate was 47 sccm.
The obtained Ti layer is an adhesion layer with the thickness of 30nm and the Pt layer with the thickness of 100 nm.
And 4, peeling for the first time, namely, soaking the 4-inch wafer in a degumming solution (model: AZ400T) to form a bottom electrode pattern, sequentially washing the bottom electrode pattern with absolute ethyl alcohol and deionized water, and performing spin-drying treatment.
Step 5, oxidizing for the second time, namely performing chemical vapor deposition on the first SiO2Growing a second SiO on the layer2Layer with a thickness of 300 nm.
Step 6, second photoetching is carried out, and second SiO is etched through the photoetching process2And forming a resistance change layer window and a bottom electrode pressure welding point window on the bottom electrode, and removing photoresist.
And 7, carrying out third photoetching, and forming a resistance change layer pattern on the 4-inch wafer through a third photoetching process.
Step 8, preparing a resistance change layer on the photoetching pattern by utilizing a radio frequency magnetron sputtering method, and carrying out oxygen (O)2Purity: 99.999%) and argon (Ar, purity: 99.999%) is adopted, and a ZnO target material is doped with 5% of Li under the mixed gas environment, wherein sputtering gas O2The flow ratio of Ar to Ar is 15sccm:47sccm, the sputtering gas pressure is 1.0Pa, and the sputtering background vacuum is 1X 10-4Pa, sputtering temperature 200 ℃.
And 9, peeling for the second time, soaking a 4-inch wafer sample in a degumming solution (model: AZ400T), forming a resistance change layer through a peeling process, sequentially cleaning with absolute ethyl alcohol and deionized water, and drying.
Step 10, fourth photoetching, forming a top electrode pattern on a 4-inch wafer through a fourth photoetching process, preparing an Ag layer (the purity of Ag is 99.99%) by utilizing a magnetron sputtering method, wherein the sputtering vacuum degree is superior to 1 multiplied by 10-4Pa, the temperature of the substrate is room temperature, the working pressure is 1.0Pa, the sputtering power is 100W, the flow of the introduced argon is 47sccm, and the time is 10 min.
And 11, stripping for the third time, soaking a 4-inch wafer sample in a degumming solution (model: AZ400T), forming an Ag electrode with the thickness of 100nm through a stripping process, sequentially cleaning with absolute ethyl alcohol and deionized water, and drying.
Step 12, oxidizing for the third time, and growing SiO by adopting a chemical vapor deposition process2As a passivation layer, 150nm thick.
And step 13, carrying out fifth photoetching and photoetching on the passivation layer to form a pressure welding point.
And step 14, cleaning, forming ohmic contact through alloying treatment, wherein the alloying treatment is carried out as follows, and the chip is treated for 30min in a vacuum environment at 300 ℃ to finish the chip process manufacturing.
Step 15, spin-coating photoresist on the four-inch wafer sample to serve as a scribing protective film; and scribing, namely soaking the chip in an acetone solution, and removing the protective adhesive film.
And step 16, bonding, packaging and testing the chip.
Example 2
The preparation method of this example is similar to example 1, except that in step 8, a 3% Li-doped ZnO target was used.
Example 3
The preparation method of this example is similar to that of example 1, except that in step 8, 8% Li is used to dope the ZnO target.
Example 4
The preparation method of this example is similar to example 1, except that in step 8, a 10% Li-doped ZnO target was used.
Example 5
The preparation method of this example is similar to that of example 1 except that the flow ratio of oxygen to argon in step 8 is 0sccm:47 sccm.
Example 6
The preparation method of this example is similar to that of example 1 except that the flow ratio of oxygen to argon in step 8 is 30scm:47 sccm.
Example 7
The manufacturing method of this example is similar to example 1 except that the temperature of the alloying treatment in step 14 is 200 ℃.
Example 8
The manufacturing method of this example is similar to example 1 except that the temperature of the alloying treatment in step 14 is 400 ℃.
Comparative example
Comparative example 1
The preparation method of this comparative example is similar to example 1, except that in step 8, a pure ZnO target was used.
Examples of the experiments
Experimental example 1
The resistive random access memories prepared in examples 1 to 8 and comparative example 1 were subjected to an electrical property test with a Keithley 4200-SCA semiconductor parameter test system, and the ground probe was connected to the Ti/Pt bottom electrode surface and the other probe was connected to the Ag top electrode.
Wherein, the current-voltage test cycle sequence is 1 '→ 2' → 3 '→ 4', the positive direction scanning is firstly carried out, then the 0V is carried out again, then the negative direction scanning is carried out again, and then the 0V is carried out again.
Typical current-voltage characteristic curves of the above resistance change memory are shown in fig. 5 to 8.
FIG. 5 shows current-voltage characteristics of the resistive random access memories prepared in examples 1, 5 and 6 at different oxygen-argon ratios (current-voltage characteristics of each example)All detect multiple curves, select the most representative curve for comparison), as can be seen from FIG. 5, when O2When Ar is 15:47sccm (example 1), the prepared resistive random access memory has better current-voltage characteristics.
Fig. 6 shows current-voltage characteristic curves of the resistive random access memories prepared in examples 1 to 4 and comparative example 1 under different Li doping concentrations, and as can be seen from fig. 6, the resistive random access memory prepared in example 1 (with a Li doping amount of 5%) has a resistive window greater than 106The resistance change window of the resistance change memory (Li doping amount is 3%) prepared in example 2 is greater than 103The resistance change window of the resistance change memory (with the Li doping amount of 8%) prepared in example 3 is larger than 106The resistance change window of the resistance change memory (with a Li doping amount of 10%) prepared in example 4 is greater than 106The resistance change window of the resistance change memory (pure ZnO, undoped Li) prepared in comparative example 1 was greater than 101。
Therefore, it is understood from the above that the switching current ratio of the resistance random access memory is improved as the Li doping concentration increases. When the doping content of Li exceeds 5%, the doping concentration of Li is increased, and the on-off current ratio of the resistive random access memory is not obviously improved.
Fig. 7-1 to 7-3 show a plurality of repeatedly measured current-voltage curves (different symbols in the figure represent a plurality of repeated test curves under the same test conditions) of the resistive random access memories prepared at different alloying treatment temperatures described in examples 1, 7, 8, and it can be seen from fig. 7-1 to 7-3 that the current-voltage characteristic curves of the devices have better reproducibility when the annealing temperature is 300 ℃ (example 1).
Fig. 8 shows a plurality of repeatedly detected current-voltage curves of the resistance change memory prepared in example 1 (different symbols in the figure represent a plurality of repeated test curves under the same test conditions).
The resistance random access memory prepared in example 1 was subjected to a retention test, and the test result is shown in fig. 9, and the device can be retained in a high resistance state and a low resistance state for more than 1000 seconds, and has a long data retention capacity.
The resistance change device of example 1 was subjected to the durability test, and the test results are shown in fig. 10, and the test was performed under the pulse condition(the pulse conditions were set at a set voltage of 1V, a reset voltage of-1V, and a rise time of 9X 10-4s, pulse width 1X 10-5s, delay time 2X 10-4s) durability.
As can be seen from fig. 10, the resistive random access memory based on the 5% Li-doped ZnO thin film can achieve 1000 cycles between the high resistance state and the low resistance state under the pulse voltage, and thus it can be illustrated that the device exhibits good cycle durability and is suitable for use as a nonvolatile memory for multiple erasing and writing of data.
In the description of the present invention, it should be noted that the terms "upper", "lower", "inner", "outer", "front", "rear", and the like indicate orientations or positional relationships based on operational states of the present invention, and are only used for convenience of description and simplification of description, but do not indicate or imply that the referred device or element must have a specific orientation, be constructed in a specific orientation, and be operated, and thus should not be construed as limiting the present invention.
The present invention has been described above in connection with preferred embodiments, but these embodiments are merely exemplary and merely illustrative. On the basis of the above, the invention can be subjected to various substitutions and modifications, and the substitutions and the modifications are all within the protection scope of the invention.

Claims (1)

1. An integrated manufacturing process method of a resistive random access memory is characterized in that the resistive random access memory comprises a substrate (1) and a single or a plurality of resistive random access units arranged on the substrate, wherein,
the resistance change unit comprises a bottom electrode (2), a resistance change layer (3) and a top electrode (4) which are sequentially arranged, wherein the resistance change layer (3) is a Li-doped ZnO thin film, the doping concentration of Li is 5%, and the doping concentration of Li is the mass fraction of Li in ZnO;
the thickness of the resistance change layer (3) is 120 nm-160 nm;
the substrate (1) is a monocrystalline silicon substrate, the upper surface of the substrate is provided with a first silicon dioxide layer (5), and the thickness of the first silicon dioxide layer is 400 nm;
the plurality of resistance change units are arranged in a crisscross array,
the integrated manufacturing process method of the resistive random access memory comprises the following steps of: first oxidation, using 4 inch monocrystalline silicon wafer as substrate, cleaning, and growing first SiO by thermal growth method2A layer having a thickness of 400 nm;
first photoetching on the first SiO2Forming a Ti/Pt bottom electrode window on the upper surface of the substrate by a photoetching process, wherein the model of a bottom photoresist adopted in the photoetching process is LOR10B, and the model of a positive photoresist is AZ 1500;
preparing a Ti/Pt bottom electrode by a magnetron sputtering method, wherein high-purity titanium (purity: 99.995%, diameter: 50.8mm) and high-purity platinum (purity: 99.99%, diameter: 50.8mm) are used as sputtering targets, the power of Ti is 100W, and the time is 5 min; the vacuum degree is 1.0Pa, the sputtering gas is Ar, and the flow rate is 47 sccm; the power of Pt is 100W, and the time is 10 min; the vacuum degree is 1.0Pa, the sputtering gas is Ar, and the flow rate is 47 sccm; the obtained Ti layer is an adhesion layer, the thickness is 30nm, and the thickness of the Pt layer is 100 nm;
peeling for the first time, soaking a 4-inch wafer in a degumming solution (model: AZ400T) to form a bottom electrode pattern, sequentially washing with absolute ethyl alcohol and deionized water, and performing spin-drying treatment;
second oxidation by chemical vapor deposition on the first SiO2Growing a second SiO on the layer2A layer having a thickness of 300 nm;
second photoetching, etching the second SiO by photoetching process2Forming a resistance change layer window and a bottom electrode pressure welding point window on the bottom electrode, and removing photoresist;
carrying out third photoetching, namely forming a resistance change layer pattern on the 4-inch wafer through a third photoetching process;
preparing a resistance change layer on the photoetching pattern by utilizing a radio frequency magnetron sputtering method, and carrying out chemical vapor deposition on oxygen (O)2Purity: 99.999%) and argon (Ar, purity: 99.999%) is adopted, and a ZnO target material is doped with 5% of Li under the mixed gas environment, wherein sputtering gas O2The flow ratio of Ar to Ar is 15sccm:47sccm, the sputtering gas pressure is 1.0Pa, and the sputtering background vacuum is 1X 10-4Pa, the sputtering temperature is 200 ℃;
carrying out secondary stripping, soaking a 4-inch wafer sample in a degumming solution (model: AZ400T), forming a resistance change layer through a stripping process, sequentially washing with absolute ethyl alcohol and deionized water, and carrying out spin-drying treatment;
fourth photoetching, forming a top electrode pattern on a 4-inch wafer through a fourth photoetching process, preparing an Ag layer (the purity of Ag is 99.99%) by using a magnetron sputtering method, wherein the sputtering vacuum degree is superior to 1 multiplied by 10-4Pa, the temperature of the substrate is room temperature, the working pressure is 1.0Pa, the sputtering power is 100W, the flow of introduced argon is 47sccm, and the time is 10 min;
stripping for the third time, soaking a 4-inch wafer sample in a degumming solution (type: AZ400T), forming an Ag electrode with the thickness of 100nm by a stripping process, sequentially cleaning the Ag electrode with absolute ethyl alcohol and deionized water, and drying the Ag electrode;
third oxidation, growing SiO by chemical vapor deposition2As a passivation layer, with a thickness of 150 nm;
photoetching the passivation layer by fifth time to form a pressure welding point;
cleaning, forming ohmic contact through alloying treatment, wherein the alloying treatment is carried out in the following way, and the treatment is carried out for 30min in a vacuum environment at 300 ℃ to finish the chip process manufacturing;
spin-coating photoresist on a four-inch wafer sample to serve as a scribing protective film; scribing, soaking the chip in acetone solution, and removing the protective adhesive film;
and (5) bonding, packaging and testing the chip.
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