CN111651948B - Parameterized circuit unit delay estimation model, modeling method and system thereof - Google Patents
Parameterized circuit unit delay estimation model, modeling method and system thereof Download PDFInfo
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- CN111651948B CN111651948B CN202010515420.9A CN202010515420A CN111651948B CN 111651948 B CN111651948 B CN 111651948B CN 202010515420 A CN202010515420 A CN 202010515420A CN 111651948 B CN111651948 B CN 111651948B
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- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/32—Circuit design at the digital level
- G06F30/33—Design verification, e.g. functional simulation or model checking
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- G06F30/3312—Timing analysis
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- G06F30/20—Design optimisation, verification or simulation
- G06F30/27—Design optimisation, verification or simulation using machine learning, e.g. artificial intelligence, neural networks, support vector machines [SVM] or training a model
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Abstract
A parameterized circuit element delay estimation model, modeling method and system thereof, the circuit element delay estimation model comprising input parameters including at least one of: device size parameters; device model parameters related to process fluctuation; operating voltage parameters; a circuit temperature parameter; and circuit aging state parameters. The invention improves the delay characterization precision of the circuit unit through the parameterization of the delay model, and reduces the dimension of the input parameter of the delay estimation model according to the sensitivity of the parameter so as to simplify the parameterized delay estimation model; the parameterized delay estimation model is built by adopting machine learning, so that a high-precision delay model can be built for any circuit unit in a self-adaptive manner; the invention adopts various analysis techniques to reduce Monte Carlo utilization space and thereby reduce circuit simulation to accelerate modeling.
Description
Technical Field
The invention belongs to the field of integrated circuits, and particularly relates to a parameterized circuit unit delay estimation model, a modeling method and a system thereof.
Background
With the progress of integrated circuit technology, the feature size is continuously reduced, the working voltage is continuously reduced, and particularly, the working voltage is lower than the threshold voltage of a device under extremely low power consumption working, the change of the device performance along with the fluctuation of the technology (P), the fluctuation of the working voltage (V) and the fluctuation of the temperature (T) is more obvious, and the delay distribution of circuit units is flattened trend and non-Gaussian distribution. For a circuit working at a wide variable voltage, the aging accumulation of a device is obvious under a higher voltage, and for a super-threshold voltage working, the aging accumulation has no obvious effect on the delay of a circuit unit, but when the circuit works at a sub-threshold value, the aging accumulation has very obvious effect on the delay of the circuit unit, so that the delay distribution of the circuit unit is flattened and non-Gaussian, the aging states of internal devices of the same circuit unit in different applications and different paths are greatly different, and the delay difference shown by the circuit unit is also great.
The circuit unit delay characterization in the prior art is suitable for the condition that the circuit unit delay is in concentrated Gaussian distribution, and is inaccurate in characterization of the delay when the circuit unit delay is applied to an advanced process integrated circuit, particularly when the circuit unit subthreshold works. Furthermore, prior art delay characterization of circuit cells does not take into account device aging (a) within the circuit cells, and in particular does not take into account different aging states, such delay data being used for timing analysis can cause significant errors or even errors.
Disclosure of Invention
It is therefore one of the primary objectives of the present invention to provide a parameterized circuit cell delay estimation model, a modeling method and a system thereof, so as to at least partially solve at least one of the above problems.
In order to achieve the above object, as one aspect of the present invention, there is provided a digitized circuit cell delay estimation model and a modeling method thereof, including input parameters including at least one of the following parameters:
Device size parameters;
device model parameters related to process fluctuation;
operating voltage parameters;
A circuit temperature parameter; and
Circuit aging state parameters.
As another aspect of the present invention, there is also provided a parameterized circuit cell delay estimation system comprising a circuit cell delay estimation model as described above.
As still another aspect of the present invention, there is also provided a modeling method of a parameterized circuit cell delay estimation model, including:
(1) Generating input parameter-circuit delay data through Monte Carlo circuit simulation;
(2) And analyzing the input parameter-circuit delay data by a machine learning method to establish a parameterized delay estimation model.
Based on the above technical solution, the parameterized circuit unit delay estimation model, the modeling method and the system thereof have at least the following advantages compared with the prior art:
1. The invention improves the delay characterization precision of the circuit unit through the parameterization of the delay model, and reduces the dimension of the input parameter of the delay estimation model according to the sensitivity of the parameter so as to simplify the parameterized delay estimation model;
2. The parameterized delay estimation model is built by adopting machine learning, so that a high-precision delay model can be built for any circuit unit in a self-adaptive manner;
3. the invention adopts various analysis techniques to reduce Monte Carlo utilization space and thereby reduce circuit simulation to accelerate modeling.
Drawings
FIG. 1 is a graph showing the mean value of the delay distribution of a 16nm circuit unit according to the aging state;
FIG. 2 is a graph showing the change of the 3 sigma point delay value of the 16nm circuit unit delay profile with the aging state;
FIG. 3 is a flow chart of a method for modeling a parameterized circuit cell delay estimation model in accordance with one embodiment of the present invention;
FIG. 4 is a flow chart of a method for modeling a parameterized circuit element delay estimation model in accordance with another embodiment of the present invention;
FIG. 5 is a flow chart of a method for modeling a parameterized circuit element delay estimation model in accordance with another embodiment of the present invention.
Detailed Description
The present invention will be further described in detail below with reference to specific embodiments and with reference to the accompanying drawings, in order to make the objects, technical solutions and advantages of the present invention more apparent.
The invention discloses a parameterized circuit unit delay estimation model, which comprises input parameters, wherein the input parameters comprise at least one of the following parameters:
Device size parameters;
device model parameters related to process fluctuation;
operating voltage parameters;
A circuit temperature parameter; and
Circuit aging state parameters.
In some embodiments of the invention, the device dimension parameter comprises a dimension parameter of each device within the circuit cell.
In some embodiments of the invention, the process variation-related device model parameters include model parameters characterizing process variations for individual devices within the circuit cell.
In some embodiments of the invention, the operating voltage parameter comprises an operating voltage parameter of each of a plurality of power supplies of the circuit unit.
In some embodiments of the invention, the circuit temperature parameter comprises an independent temperature parameter for each device or a temperature parameter common to multiple devices;
in some embodiments of the invention, the circuit burn-in status parameter comprises a burn-in status parameter of one or more devices within the circuit cell.
The invention also discloses a parameterized circuit unit delay estimation system which comprises the circuit unit delay estimation model.
The invention also discloses a modeling method of the parameterized circuit unit delay estimation model, which comprises the following steps:
(1) Generating input parameter-circuit delay data through Monte Carlo circuit simulation;
(2) And analyzing the input parameter-circuit delay data by a machine learning method to establish a parameterized delay estimation model.
In some embodiments of the invention, the modeling method further comprises automatically validating the parameterized delay estimation model after step (2) is completed.
In some embodiments of the present invention, the modeling method further includes accelerating the monte carlo circuit simulation in step (1), and the accelerating method includes at least one of the following methods:
1) Reducing the circuit simulation times by utilizing the correlation of adjacent points in the parameter space;
2) Constructing an intermediate model by utilizing machine learning to reduce the circuit simulation times;
3) The hit probability of the tail area of the process fluctuation parameter sampling of the device in the circuit unit is improved by using a scaling deviation method so as to reduce the circuit simulation times;
4) Filtering the input parameters only preserves the sensitive parameters of the sensitive devices to reduce the dimension of the input parameter space so as to reduce the circuit simulation times.
In some embodiments of the present invention, the input parameters of the parameterized delay estimation model are determined before step (1) begins, and include at least one of device size parameters, process fluctuation-related device model parameters, operating voltage parameters, circuit temperature parameters, and circuit aging state parameters.
The technical scheme of the invention is further described below by means of specific embodiments and with reference to the accompanying drawings. It should be noted that the following specific examples are given by way of illustration only and the scope of the present invention is not limited thereto.
The embodiment provides a parameterized delay estimation model capable of accurately representing PVT-A sensitive circuit unit delay and a method for establishing the parameterized delay estimation model of the circuit unit. The parameterized circuit unit delay estimation model at least comprises any one of the following input parameters:
1) Device size parameters;
2) Device model parameters related to process fluctuation;
3) Operating voltage parameters;
4) A circuit temperature parameter;
5) Circuit aging state parameters.
Wherein the device size parameters include size parameters of devices within the circuit unit. Further, the relevant dimension parameters of the devices, which are not input parameters of the delay estimation model, can be ignored for the reason that the change of the dimension parameters has little influence on the delay of the circuit unit.
Wherein the process fluctuation-related device model parameters comprise model parameters characterizing process fluctuation of each device in the circuit unit. Further, for device model parameters whose process fluctuation-related changes have little effect on circuit unit delay, the device model parameters related to the devices can be ignored, and the device model parameters related to the devices are not used as input parameters of the delay estimation model.
The operating voltage parameters comprise the operating voltage parameters of each of the plurality of power supplies of the circuit unit. That is, if the voltage change of some power supply terminals has little influence on the delay performance of the circuit unit, the power supply voltages of the power supply terminals can be ignored, and the working voltages of the power supply terminals are not used as the input parameters of the delay estimation model.
The circuit temperature parameter can be independent of each device, and a plurality of devices can share one temperature parameter. If the temperature change of some devices has little influence on the delay performance of the circuit unit, the temperature of the devices can be ignored, and the temperature of the devices is not used as an input parameter of the delay estimation model.
Wherein the circuit burn-in status parameter comprises a burn-in status parameter of one or more devices within the circuit cell. That is, if the aging of some devices has little effect on the delay performance of the circuit unit, the aging state of some devices can be ignored, and the aging state of the devices is not used as the input parameter of the delay estimation model.
Fig. 1 shows the change of the normalized delay distribution mean value of the 16nm circuit unit along with the aging state, and it can be seen that the change of the normalized delay distribution mean value of the circuit unit under different working voltages is significantly different under different aging states (threshold voltage drift) of the device. Under the same working voltage, the larger the threshold voltage drift caused by the aging of the device is, the larger the influence on the circuit delay distribution mean value is; the lower the operating voltage, the more pronounced the impact on the circuit delay profile mean is on the same device aging state (same device threshold voltage drift). Under the variable voltage operation, the device aging effect caused by the high voltage operation has more obvious influence on the normalized delay distribution mean value of the circuit in the low voltage operation. Note that, the abscissa is the device aging state of the circuit unit, that is, the device threshold voltage drift Vtshift; the ordinate is the normalized delay distribution mean value of the circuit unit.
Fig. 2 shows the change of the normalized delay distribution 3σ point delay value of the 16nm circuit unit along with the aging state, and it can be seen that the normalized delay distribution 3σ point delay value change of the circuit unit under different working voltages is significantly different under different aging states (threshold voltage drift) of the device. Under the same working voltage, the larger the threshold voltage drift caused by the aging of the device is, the larger the influence on the circuit normalized delay distribution 3 sigma point delay is; the lower the operating voltage, the more pronounced the effect on the circuit normalized delay profile 3σ point delay is on the same device aging state (same device threshold voltage drift). Under the variable voltage operation, the device aging effect caused by the high voltage operation has more remarkable influence on the normalized delay distribution 3 sigma point delay when the circuit works at low voltage. Note that, the abscissa is the device aging state of the circuit unit, that is, the device threshold voltage drift Vtshift; the ordinate is the circuit unit normalized delay distribution 3σ point delay.
As shown in fig. 3, in an embodiment, there is further provided a modeling method of a parameterized circuit cell delay estimation model, including:
1) Generating input parameter-circuit delay data through Monte Carlo circuit (MC circuit simulation) simulation;
2) And analyzing the input parameter-circuit delay data by a machine learning method to establish a parameterized delay estimation model.
In another embodiment, as shown in fig. 4, the modeling method further comprises, after establishing the parameterized delay estimation model, performing:
1) Automatically verifying a parameterized delay estimation model;
2) Machine learning is enhanced based on input parameter-delay data that automatically verifies detected large error points (points greater than a preset relative error) to build a more accurate parametric delay estimation model.
In yet another embodiment, as shown in fig. 5, the monte carlo circuit simulation in the modeling method accelerates the monte carlo circuit simulation using at least any one of the following methods:
1) Reducing the circuit simulation times by utilizing the correlation of adjacent points in the parameter space;
2) Constructing an intermediate model by utilizing machine learning to reduce the circuit simulation times;
3) The hit probability of the tail area of the process fluctuation parameter sampling of the device in the circuit unit is improved by utilizing a scaling deviation technology so as to reduce the circuit simulation times;
4) Filtering the input parameters only preserves the sensitive parameters of the sensitive devices to reduce the dimension of the input parameter space so as to reduce the circuit simulation times.
Wherein, sensitive device refers to a device whose device process fluctuation parameter changes affect circuit performance beyond a preset value.
The sensitive parameter refers to a parameter that the influence of the process fluctuation parameter change of a device in the sensitive device on the circuit performance exceeds a preset value.
In other embodiments, the modeling method further comprises determining input parameters of the parameterized delay estimation model, comprising at least any of the following steps:
1) The device size parameter is determined and,
2) Determining device model parameters related to process fluctuations,
3) The operating voltage parameter is determined and the operating voltage,
4) A temperature parameter of the circuit is determined and,
5) A circuit aging state parameter is determined.
Wherein determining the parametric delay estimation model further comprises at least any one of the following steps:
1) Devices with little influence on the delay performance of a circuit unit by the aging of the devices are detected in advance through circuit imitation analysis, and the aging states of the devices are excluded from the input parameters of the parameterized delay estimation model. That is, if the aging of some devices has little effect on the delay performance of the circuit unit, the aging state of some devices can be ignored, and the aging state of the devices is not used as the input parameter of the delay estimation model.
2) The circuit simulation analysis is used for detecting power supply terminals with extremely small influence on the delay performance of the circuit unit by voltage changes of certain power supply terminals in advance, and the working voltages of the power supply terminals are excluded from the input parameters of the parameterized delay estimation model. That is, if the voltage change of some power supply terminals has little influence on the delay performance of the circuit unit, the power supply voltages of the power supply terminals can be ignored, and the working voltages of the power supply terminals are not used as the input parameters of the delay estimation model.
3) Devices with extremely small influence of temperature change on the delay performance of a circuit unit are detected in advance through circuit simulation analysis, and the temperatures of the devices are excluded from the input parameters of the parameterized delay estimation model. That is, if the temperature variation of some devices has little effect on the delay performance of the circuit unit, the temperature of the devices can be ignored, and the temperature of the devices is not used as the input parameter of the delay estimation model.
4) The device with extremely small influence on the circuit unit delay caused by the device model parameter change related to the process fluctuation is detected in advance through circuit imitation analysis, and the device model parameters related to the process fluctuation of the devices are excluded from the input parameters of the parameterized delay estimation model. That is, the relevant device model parameters of the devices, which are not input parameters of the delay estimation model, can be ignored for the device model parameter variations associated with the process fluctuations, which have little influence on the delay of the circuit unit.
5) Devices with extremely small influence of the change of the size parameters on the delay of the circuit unit are detected in advance through circuit imitation analysis, and the size parameters of the devices are excluded from the input parameters of the parameterized delay estimation model. That is, the relevant dimensional parameters of these devices, which are not input parameters to the delay estimation model, may be ignored for those dimensional parameter variations that have little effect on the circuit cell delay.
The foregoing description of the embodiments has been provided for the purpose of illustrating the general principles of the invention, and is not meant to limit the invention thereto, but to limit the invention thereto, and any modifications, equivalents, improvements and equivalents thereof may be made without departing from the spirit and principles of the invention.
Claims (6)
1. A method of modeling a parameterized circuit element delay estimation model, comprising:
(1) Generating input parameter-circuit delay data through Monte Carlo circuit simulation;
(2) Analyzing input parameter-circuit delay data through a machine learning method to establish a parameterized delay estimation model;
the modeling method further includes: determining the input parameters of the parameterized delay estimation model before starting the step (1);
Accelerating the Monte Carlo circuit simulation in the step (1);
Automatically verifying the parameterized delay estimation model after the step (2) is finished;
wherein the input parameters include at least one of the following:
Device size parameters;
device model parameters related to process fluctuation;
operating voltage parameters;
A circuit temperature parameter; and
Circuit aging state parameters.
2. A modeling method as claimed in claim 1, wherein,
The device size parameters include size parameters of devices within the circuit unit.
3. A modeling method as claimed in claim 1, wherein,
The process fluctuation related device model parameters comprise model parameters representing process fluctuation of each device in the circuit unit.
4. A modeling method as claimed in claim 1, wherein,
The operating voltage parameter includes operating voltage parameters of each of a plurality of power supplies of the circuit unit.
5. A modeling method as claimed in claim 1, wherein,
The circuit temperature parameters comprise independent temperature parameters of each device or temperature parameters which are shared by a plurality of devices;
the circuit burn-in state parameters include burn-in state parameters of one or more devices within the circuit cell.
6. Modeling method in accordance with claim 1, characterized in that the acceleration method comprises at least one of the following methods:
1) Reducing the circuit simulation times by utilizing the correlation of adjacent points in the parameter space;
2) Constructing an intermediate model by utilizing machine learning to reduce the circuit simulation times;
3) The hit probability of the tail area of the process fluctuation parameter sampling of the device in the circuit unit is improved by using a scaling deviation method so as to reduce the circuit simulation times;
4) Filtering the input parameters only preserves the sensitive parameters of the sensitive devices to reduce the dimension of the input parameter space so as to reduce the circuit simulation times.
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| CN106066919A (en) * | 2016-06-13 | 2016-11-02 | 中国科学院微电子研究所 | It is applied to the SSTA method of near/subthreshold value digital circuit |
| CN109255159A (en) * | 2018-08-17 | 2019-01-22 | 东南大学 | A kind of circuit paths delay volatility forecast method based on machine learning |
| CN110245432A (en) * | 2019-06-18 | 2019-09-17 | 中国科学院微电子研究所 | Circuit unit characterization method, data storage, access method and processing system |
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