CN114330193A - Wide voltage circuit delay estimation method based on parameter selection - Google Patents
Wide voltage circuit delay estimation method based on parameter selection Download PDFInfo
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Abstract
The invention discloses and protects a wide voltage circuit delay estimation method based on parameter selection, which is based on a low-order tensor approximation model, because the model has two undetermined parameters of rank and polynomial degree, the optimization of the selection of the two parameters can bring obvious improvement of speed and precision to the low-order tensor approximation model, reduce the Monte Carlo simulation times, realize an accurate and effective time sequence analysis method and provide guidance for circuit design. Firstly, extracting a key path of a circuit, efficiently sampling a process parameter space by using a Latin hypercube, obtaining corresponding key information through SPICE (simulation program with integrated Circuit emphasis), constructing an initial training set, and finding out parameters optimized under the current application environment to construct a training low-order tensor approximate circuit delay model according to a parameter lookup table provided by the invention.
Description
Technical Field
The invention belongs to the field of integrated circuit design automation (EDA), and particularly relates to a wide voltage circuit delay estimation method based on parameter selection.
Background
The data processing amount and the standby time of the chip become the main requirements of the modern internet of things and mobile terminal equipment, so the key problems of chip design are to reduce the data processing power consumption of the chip and improve the energy efficiency. Because the power consumption is reduced in square with the voltage, the traditional low power consumption technology achieves the purpose of reducing the power consumption by reducing the power supply voltage. The idea of the sub-threshold circuit design is to reduce the power consumption of the circuit greatly by reducing the power supply voltage below the threshold voltage. The method has good application prospect in wireless sensors and other devices which have low requirements on performance and need extremely low power consumption. However, subthreshold circuit designs have some disadvantages: on one hand, since the performance of the chip around the subthreshold voltage is exponentially reduced compared with the conventional voltage, the subthreshold circuit is poor in performance when facing some applications with higher requirements on the calculation speed; on the other hand, under the extremely low voltage, the leakage power consumption is greatly increased and becomes a main power consumption source under the sub-threshold voltage, so that the power consumption advantage of the circuit under the sub-threshold voltage is weakened. How to reduce power consumption to the maximum extent on the basis of ensuring a certain performance becomes a new challenge in integrated circuit design.
At low voltages, delay fluctuations due to process variations are exacerbated, and designers must leave sufficient timing margins for the design to ensure that the final manufactured chips will operate properly. This requires timing analysis to accurately evaluate the delay statistics of the circuit under process variation. If the delay obtained by the timing analysis is longer than the actual delay of the chip, unnecessary performance waste may be caused, and if the delay obtained by the timing analysis is shorter than the actual delay of the chip, the chip may not work normally. The process deviation refers to the phenomenon that the process parameters such as transistor length, gate oxide thickness, doping concentration and the like deviate from their nominal values due to factors such as equipment precision or process limitation in the manufacturing process of the integrated circuit. Due to the existence of process variations, the characteristics of the circuit, such as current, delay, etc., may fluctuate with fluctuations in the process parameters.
For time delay analysis under the influence of process deviation, On-Chip Variation (OCV) and Advanced On-Chip Variation (AOCV) analysis methods are adopted in conventional time sequence analysis. They characterize the worst case delay that a path may experience under process variation by multiplying the delay of each stage of the path in the circuit by a coefficient and perform timing violation checking in the worst case. With the reduction of the power supply voltage, the delay fluctuation under the process deviation is increased, the traditional time sequence analysis method can cause serious performance loss, and the method is not suitable for the time sequence analysis of the wide voltage circuit under the process deviation any more.
Disclosure of Invention
The invention aims to provide a parameter selection-based wide voltage circuit delay estimation method to realize accurate and effective time sequence analysis under wide voltage.
The method comprises the following steps:
s1, acquiring a pre-sampling training set;
s2, establishing a low-order tensor approximation model RP parameter lookup table, wherein R is the rank of the low-order tensor approximation model, and P is the polynomial degree of the low-order tensor approximation model;
s3, obtaining optimized parameters R and P under the current simulation environment through the RP parameter lookup table established in the step 2;
s4, constructing a model for solving the path delay data of the wide voltage circuit;
s5, training the constructed model by using a pre-sampling training set;
and S6, inputting the process parameters of the circuit to be tested into the trained model, and outputting the delay data, the mean value, the variance and the yield of the delay data.
Preferably, the method for obtaining the pre-sampling training set in step S1 includes extracting a critical path of the circuit through a timing analysis tool, obtaining a process parameter, regarding fluctuation of the process parameter as a random variable conforming to gaussian distribution, and performing latin hypercube sampling on the gaussian distribution obeyed by the obtained process parameter; and generating delay data through simulation of the SPICE circuit, wherein the pre-sampling training set comprises process parameters obtained by sampling and delay data obtained by simulation.
Preferably, the method for establishing the RP parameter lookup table in step S2 includes:
obtaining an optimal rank parameter R: the method comprises the steps that observation points are set according to a certain step length in a certain voltage range for different dimensionality groups of circuits in a TAU15 reference circuit, the influence of the different rank parameters on circuit precision is researched, and a precision optimal solution is selected as an optimal rank parameter R in a lookup table;
obtaining an optimal polynomial degree parameter P: by setting observation points according to a certain step length for a plurality of groups of circuits with different dimensionalities in a TAU15 reference circuit within a certain voltage range, respectively researching the influence of a plurality of groups of different polynomial degree values on the circuit precision, and selecting a precision optimal solution as an optimal polynomial degree parameter P in a lookup table;
let the voltage under simulation environment be ViD is dimension of circuit process parameter, RP parameter table is established, and corresponding RP parameter pair is (R)i,d,Pi,d)；
And finally, selecting an optimal rank parameter R and an optimal polynomial degree parameter P according to the voltage in the simulation environment.
Preferably, the determination method of the lookup table in S2 is not limited to the TAU15 reference circuit.
Preferably, the voltage range is 0.6-1.1V, and the step size is 0.1V.
Preferably, in step S4, the method for constructing the model for solving the wide voltage circuit path delay data includes using a low-order tensor approximation model as the model for solving, using the process parameters obtained by sampling as input variables of the low-order tensor approximation model, where the process parameters satisfy gaussian distribution, and using the delay data obtained by simulation as output variables of the low-order tensor approximation model.
Has the advantages that: compared with the prior art, the technical scheme of the invention has the following beneficial technical effects:
(1) the compatibility of the application under the nominal voltage environment is not lost while the problem of near-threshold voltage simulation is considered.
(2) Aiming at the fact that the original low-order tensor approximate model does not pay attention to RP parameter selection, the optimal RP parameter is selected to construct the model in consideration of different voltage environments, and the efficiency and the precision of the model are effectively improved.
(3) The low-order tensor approximate model is used for establishing a meta-model from process parameters to output delay, particularly when the low-order tensor approximate model is established, an RP parameter selection method based on a lookup table is used, optimal parameters are designed aiming at different voltage environments, and the overall efficiency and accuracy of the model are improved.
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FIG. 1 is a flow chart of a method for estimating delay of a wide voltage circuit according to the present invention.
FIG. 2 is a detailed flowchart of the method for estimating the delay of the wide voltage circuit according to the present invention.
Detailed Description
The principles and features of this invention are described below in conjunction with the following drawings, which are set forth by way of illustration only and are not intended to limit the scope of the invention. The invention is described in more detail in the following paragraphs by way of example with reference to the accompanying drawings. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.
The invention discloses a wide voltage circuit delay estimation method based on parameter selection, which comprises the following steps as shown in figures 1-2:
s1, sampling an initial training set as an initial training set of the model;
firstly, sampling process parameters, firstly, extracting a key path of a near-threshold circuit by using a time sequence analysis tool to obtain the process parameters, regarding the fluctuation of the process parameters as random variables conforming to Gaussian distribution, and sampling the process parameters by using a Latin hypercube sampling method; and generating delay data through simulation of the SPICE circuit, wherein the pre-sampling training set comprises process parameters obtained by sampling and delay data obtained by simulation.
S2, establishing a low-order tensor approximation model RP parameter lookup table, wherein R is the rank of the low-order tensor approximation model, and P is the polynomial degree of the low-order tensor approximation model;
the rank is one of the main parameters of the low-order tensor approximation model, and determines the number of rank-one functions in the low-order tensor approximation model in step S4. For the rank parameter of the low-order tensor approximation model, different dimensionality groups of circuits in a TAU15 reference circuit are researched, observation points are set according to step length 0.1V in a voltage range of (0.6V-1.1V), influences of different sets of rank values on circuit precision are respectively researched, and the optimal solution of speed and time is selected as the optimal rank parameter in a lookup table; according to experimental results, the rank is optimal when the rank is 1 under different voltage environments, and the model has a certain precision loss along with the increase of the rank, so that the parameter R is 1 by default.
The polynomial degree P determines the number of terms of the polynomial basis of the model rank one function in S3. Intuitively, it is understood that the accuracy of the model will improve as the polynomial degree P increases. For polynomial degree parameters of a low-order tensor approximation model, a plurality of groups of circuits with different dimensionalities in a TAU15 reference circuit are researched, observation points are set according to step length 0.1V in a voltage range of (0.6V-1.1V), influences of a plurality of groups of different polynomial degree values on circuit precision are respectively researched, and an optimal solution of speed and time is selected as an optimal polynomial degree parameter in a lookup table; any representative circuit may be used for circuit experiments to determine the RP parameter.
However, according to the experimental results, it is found that the model accuracy in the same voltage environment fluctuates significantly although the overall increase of the polynomial degree is observed. According to the present conclusion, the sensitivity of the model to the polynomial degree is low under the condition of the nominal voltage, and the polynomial degree brings very limited improvement to the precision of the model.
Therefore, the RP parameter lookup table provided by the invention is obtained, and a subsequent low-order tensor approximation model is constructed according to the RP parameter lookup table. The lookup table used in S1 is selected according to the voltage under the simulation environment, and the voltage under the simulation environment is set as ViThe dimension of the circuit process parameter is d, and the corresponding RP parameter pair is (R)i,d,Pi,d). This pair of parameters will be used as the parameters in S3 to construct the low-order tensor approximation model.
And S3, obtaining the optimized parameters under the current simulation environment through an RP parameter lookup table, wherein the RP parameters are respectively the rank and polynomial degree of the low-order tensor approximation model.
S4, constructing a model for solving the path delay data of the wide voltage circuit for the circuit critical path;
the method comprises the steps of solving circuit delay data by using a low-order tensor approximation model, taking process parameters of a circuit key path as input variables of the low-order tensor approximation model, enabling the process parameters to meet Gaussian distribution, taking circuit delay as output variables of the low-order tensor approximation model, and enabling the process parameters to comprise transistor threshold voltage and channel length.
S5, training the low-order tensor approximation model;
and S7, inputting the process parameters of the circuit to be tested into the trained delay model, and outputting delay data, the mean value, the variance and the yield of the delay data.
Although the present invention has been described in detail with reference to the foregoing embodiments, it will be apparent to those skilled in the art that various changes in the embodiments and/or modifications of the invention can be made, and equivalents and modifications of some features of the invention can be made without departing from the spirit and scope of the invention.
Claims (6)
1. A wide voltage circuit delay estimation method based on parameter selection is characterized by comprising the following steps:
s1, acquiring a pre-sampling training set;
s2, establishing a low-order tensor approximation model RP parameter lookup table, wherein R is the rank of the low-order tensor approximation model, and P is the polynomial degree of the low-order tensor approximation model;
s3, obtaining optimized parameters R and P under the current simulation environment through the RP parameter lookup table established in the step 2;
s4, constructing a model for solving the path delay data of the wide voltage circuit;
s5, training the constructed model by using a pre-sampling training set;
and S6, inputting the process parameters of the circuit to be tested into the trained model, and outputting the delay data, the mean value, the variance and the yield of the delay data.
2. The parameter selection-based wide voltage circuit delay estimation method according to claim 1, wherein the method for obtaining the pre-sampling training set in step S1 includes extracting a critical path of the circuit through a timing analysis tool, obtaining process parameters, regarding fluctuation of the process parameters as random variables conforming to gaussian distribution, and performing latin hypercube sampling on the gaussian distribution obeyed by the obtained process parameters; and generating delay data through simulation of the SPICE circuit, wherein the pre-sampling training set comprises process parameters obtained by sampling and delay data obtained by simulation.
3. The method for estimating delay of wide voltage circuit based on parameter selection according to claim 1, wherein the RP parameter lookup table established in step S2 includes:
obtaining an optimal rank parameter R: the method comprises the steps that observation points are set according to a certain step length in a certain voltage range for different dimensionality groups of circuits in a TAU15 reference circuit, the influence of the different rank parameters on circuit precision is researched, and a precision optimal solution is selected as an optimal rank parameter R in a lookup table;
obtaining an optimal polynomial degree parameter P: by setting observation points according to a certain step length for a plurality of groups of circuits with different dimensionalities in a TAU15 reference circuit within a certain voltage range, respectively researching the influence of a plurality of groups of different polynomial degree values on the circuit precision, and selecting a precision optimal solution as an optimal polynomial degree parameter P in a lookup table;
let the voltage under simulation environment be ViD is dimension of circuit process parameter, RP parameter table is established, and corresponding RP parameter pair is (R)i,d,Pi,d)；
And finally, selecting an optimal rank parameter R and an optimal polynomial degree parameter P according to the voltage in the simulation environment.
4. The method of claim 3, wherein the method of determining the lookup table in S2 is not limited to the TAU15 reference circuit.
5. The method of claim 3, wherein the voltage range is 0.6-1.1V, and the step size is 0.1V.
6. The parameter selection-based wide voltage circuit delay estimation method according to claim 1, wherein in step S4, the method for constructing the model for solving the wide voltage circuit path delay data includes using a low-order tensor approximation model as a solving model, using sampled process parameters as input variables of the low-order tensor approximation model, where the process parameters satisfy gaussian distribution, and using delay data obtained through simulation as output variables of the low-order tensor approximation model.
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