CN111651354A - Real-time simulation uncertainty quantification acceleration method - Google Patents
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Abstract
The invention relates to an uncertainty quantification acceleration method for real-time simulation, which is realized by a real-time simulation platform based on an FPGA (field programmable gate array), has small simulation step length and high speed, and solves the problems of time consumption and low efficiency of Monte Carlo analysis for parameter uncertainty quantification on the traditional computing platform; due to the real-time performance of the platform, the synchronism of the measurement of the response quantity of a prototype system and the measurement of the response quantity of a model simulation system are ensured, and the accuracy of the uncertainty of the quantitative model form of the improved surface integral quantity verification method is improved.
Description
Technical Field
The invention belongs to the technical field of uncertainty quantification, and particularly relates to an uncertainty quantification acceleration method for real-time simulation.
Background
Modeling and simulation become an important research method in the engineering field, and play an important role in the process of system design, debugging and fault diagnosis. However, in all model-based research methods, the simulation results of the model often deviate from the actual system. The deviation of the simulation from the actual system depends to a large extent on the fineness of the model used and the uncertainty introduced by the simulation calculation process, two sources of uncertainty existing in the modeling and simulation-parameter uncertainty and model form uncertainty. At present, the model uncertainty quantification method with more practical operability is as follows: the method comprises the steps of quantifying the parameter uncertainty of the model by adopting a Monte Carlo analysis method, quantifying the model form uncertainty by adopting an improved area measurement verification method, and quantifying the total uncertainty of the model by adopting a probability box method.
The use of the monte carlo analysis method means that a large number of simulations of the model are required to obtain statistically significant analysis results. However, in the field of power electronics, as semiconductor technology advances, switching frequencies are becoming higher and higher, resulting in a smaller size and lower weight of the converter. The disadvantage is that the efficiency of the simulation is greatly reduced due to the increase of the switching frequency, and the simulation step size is usually at least 20 times smaller than the switching frequency. Thus in simulating a converter with a switching frequency in the order of 100kHz the step size should be at least less than 1us, and if further considerations are made to the accuracy of the simulation, the step size will achieve about 2MHz less than 20 times the switching frequency. On the traditional simulation platform, the computing power is already high, the simulation speed is low, Monte Carlo analysis is time-consuming and low in efficiency, and the parameter uncertainty is difficult to quantify. If the complexity of the system model is high, it is desired to increase the simulation speed, and a general method is to increase the hardware configuration of the simulation platform, for example, if a multi-core simulation platform is adopted, the cost is greatly increased.
In addition, when the model form uncertainty is quantified using the modified area metric verification method, the target System Response Quantity (SRQs) of the model is measured from the simulation output data. As shown in fig. 1, the simulation step size 1< step size 2< step size 3, and if the SRQs is selected as the overshoot and the adjustment time, the overshoot and the adjustment time measured by the simulation results in the three step sizes are different, and the result in the simulation step size 1 can most represent the characteristics of the real system. If the traditional simulation platform is adopted for simulation, when the simulation step length is not small enough, the SRQs measured by simulation may be inaccurate or even wrong.
Disclosure of Invention
Technical problem to be solved
In order to solve the problem that Monte Carlo analysis for parameter uncertainty quantification on a traditional computing platform consumes time and is low in efficiency, the invention provides an uncertainty quantification acceleration method for real-time simulation.
Technical scheme
A real-time simulation uncertainty quantification acceleration method is characterized by comprising the following steps:
step 1: obtaining a parameter value related to the expected characteristic of the system, wherein the parameter related comprises two parts: the model parameters of the system model reaching the expected characteristics and the tolerance of each parameter of the model;
step 2: establishing a discretization model of the system by using the related parameters obtained in the step 1;
and step 3: selecting target system response quantity;
and 4, step 4: the discretization model obtained in the step (2) and the solving process of the target system response quantity in the step (3) are realized on a software development platform of the FPGA, the software design of the whole model on the FPGA is completed, an output port is added for the target response quantity selected in the step (3), and a simulation engineering file of the model is established;
and 5: behavioral simulation of model software
Performing behavior simulation on the simulation engineering file of the model to determine whether the function of the system model meets the expectation; if the model function is in accordance with expectation and the behavior simulation is passed, carrying out the next step; if the behavior simulation does not pass the expectation, the software implementation of the model has problems, and the next step is carried out again after the problems are searched and solved in the step 4;
step 6: determining whether to reconstruct the model according to the resource requirements of the model simulation
Synthesizing a model engineering file on an adopted FPGA software development platform, and selecting an FPGA model which just meets or is larger than the calculation resources required by the model for the model simulation according to a resource use condition analysis report generated by the software development platform;
when resources of the FPGA model selected by a user can not support the simulation of placing the whole system model on one FPGA chip, splitting the system model and simultaneously expanding the number of FPGA board cards can be split according to different functions of an actual system or according to different functions of each calculation module in the software implementation;
and 7: bit stream file for generative model
Operating in a software development platform according to a platform flow, adding a pin constraint file in a model engineering file, determining I/O for data acquisition output by a later model, and finally obtaining a bit stream file of the model;
and 8: an experimental plan was made, following 4 criteria:
1. before formal experiments, the experimental system is ensured to have normal characteristics or no defects so as to contain all uncertainty sources and prevent underestimation or overestimation of uncertainty;
2. determining model input and SRQs measurement by the same expert, determining input parameters, initial and boundary conditions, and estimating uncertainty of the parameters;
3. the more the number of the prototype/real system is, the better the model/real system is, the parameter determination of each prototype/real system needs to be repeatedly measured for many times and then an average value is taken, so that the influence of the measurement error on the model form uncertainty quantification is reduced;
4. repeated experimental measurement is carried out on the SRQs so as to reduce the influence of measurement errors on model form uncertainty quantification;
and step 9: establishing an FPGA simulation experiment platform and carrying out experiments
Downloading the model bit stream file obtained in the step 7 into an FPGA chip, building an experiment platform, and then carrying out an experiment according to the experiment plan formulated in the step 8; the experimental platform is built under two conditions:
1. when no relevant parameters and experimental data of a real system exist, the control signal controls Monte Carlo analysis in the FPGA simulation platform and the parameters of an experimental prototype to be substituted into the simulation process, and the control signal controls the working condition change corresponding to SRQs formulated in the experimental plans of starting, loading/unloading and the like of the prototype; monte Carlo analysis data output by the FPGA simulation platform, simulation data obtained by substituting experimental prototype parameters into the simulation data and experimental data of N prototypes are collected by an experimental data collection system, and then are sent to an extraction function module of target system response quantity to extract SRQs, and then the cumulative probability distribution function CDF of each SRQs of the Monte Carlo analysis, the prototype parameter simulation and the actually measured prototype data is obtained through calculation;
2. relevant parameters of a real system and historical experimental data required by SRQ extraction exist, Monte Carlo analysis data output by an FPGA simulation platform and experimental prototype parameters are substituted into simulated data and are collected by an experimental data collection system, the simulated data and the experimental data are sent to an extraction function module of target system response quantity together to extract SRQs, and then the SRQs and the SRQs are respectively calculated to obtain an accumulative probability distribution function CDF of the SRQs of the Monte Carlo analysis, the prototype parameter simulation and the actually measured data;
step 10: model uncertainty quantification
And (3) carrying out uncertainty quantification on the 3 CDFs obtained in the step (9) according to the following method:
[1] the Monte Carlo analysis obtains a cumulative probability distribution function CDF (F (x)), which is a quantitative result of parameter uncertainty;
[2] quantizing model form uncertainty of a real system parameter simulation CDF and actual measurement data CDF according to an improved surface product measurement verification method;
the improved type area measurement verification method is also characterized in that the area between the system response quantity cumulative distribution function obtained by comparing simulation and the system response quantity cumulative distribution function obtained by experiment is defined as d + 'and the area with the experiment result smaller than the simulation result is defined as d-';
thus, the range over which model format uncertainty can be found is:
[F(x)-Fsd-,F(x)+Fsd+]
in the formula, FsIs a safety factor;
[3] obtaining the total uncertainty of the model by using a probability box method, drawing the uncertainty of the model parameters obtained by the Monte Carlo analysis obtained in the step (1) in the probability box in a CDF manner, and drawing the uncertainty of the model form obtained in the step (2) in the probability box in an interval manner; in order to quantify the total uncertainty, a confidence level is specified so that the parameter uncertainty is also represented in the form of an interval in a probability box, and an upper limit and a lower limit of the uncertainty of the model are obtained, and the total uncertainty of the model is obtained by subtracting the lower limit from the upper limit.
The discretization method in the step 2 comprises a Euler method, a Runge-Kutta method and a linear multi-step method.
And 5, adding/creating a simulation source file on the used FPGA software development platform to perform simulation test on the model.
Advantageous effects
Compared with a DSP and a CPU, the FPGA has the following advantages: the units can run in parallel, the calculation speed is high, and high real-time performance and high control precision can be realized; secondly, editing the device by using a hardware description language, and realizing different hardware structures by modifying codes so as to realize different functions; with the development of devices, internal resources provided by the FPGA are more and more, and a plurality of IP hard cores and soft cores are integrated in a chip, so that the device is convenient to use. Therefore, the FPGA is adopted to realize the calculation of the model, and the method has wide application prospect.
The maximum advantage of the FPGA is the parallel operation characteristic, the modeling is carried out in a proper mode, and a parallel calculation method is adopted, so that the step length of real-time simulation can be reduced to a nanosecond level, and great benefits are brought to the solution of two problems in uncertainty quantification.
The invention provides an uncertainty quantification acceleration method for real-time simulation, which solves the following 2 problems:
1. monte Carlo analysis adopted for parameter uncertainty quantification in system model uncertainty quantification is time-consuming, low in efficiency and high in requirement on simulation platform resources;
2. in the method for improving the uncertainty of the model form of the surface product measurement verification method, the problem of inaccurate measurement of the model SRQs and inaccurate quantification of the model form are caused due to insufficient simulation.
The uncertainty quantification acceleration method for real-time simulation is realized by a real-time simulation platform based on an FPGA (field programmable gate array), has small simulation step length and high speed, and solves the problem of low efficiency of Monte Carlo analysis for parameter uncertainty quantification on the traditional computing platform; due to the real-time performance of the platform, the synchronism of the measurement of the response quantity of a prototype system and the measurement of the response quantity of a model simulation system are ensured, and the accuracy of the uncertainty of the quantitative model form of the improved surface integral quantity verification method is improved.
Drawings
FIG. 1 traditional simulation platform
FIG. 2 interleaved parallel converter System model software overview framework
Simulation experiment platform architecture diagram under figure 3 and 1
Simulation experiment platform architecture diagram under figure 4 and figure 2
FIG. 5 is a schematic view of an improved method for verifying the amount of a profile product
FIG. 6 probability box schematic
FIG. 7 is a flow chart of the present invention
Detailed Description
The invention will now be further described with reference to the following examples and drawings:
as shown in fig. 1, the steps are specifically implemented as follows:
1. obtaining parameter values associated with a system to achieve a desired characteristic
The relevant parameters include two parts:
【1】 Model parameters for achieving expected characteristics of the system model and also as parameter ratings for Monte Carlo analysis
The calculation of the model parameters can be obtained by knowledge of theoretical calculation equations, empirical formulas and the like in related fields, or by taking an average value through multiple measurements of a real system.
【2】 Tolerance of each parameter of the model, parameter tolerance of Monte Carlo analysis
The tolerance of the model parameters can be determined according to actual conditions. For example, a power electronic component data manual generally gives a tolerance range of the component parameters, and can be combined with the working temperature of a system and the temperature drift of elements to make proper estimation; manufacturing tolerances of the mechanical structure; if the parameters are measured experimentally, the tolerance can be determined based on the measurement error.
2. Establishing a discretized model of a system
And (3) establishing a discretization model of the system by using the related parameters obtained in the step (1).
In the invention, the model is put on a simulation computing platform based on FPGA to run, thereby having great advantages in simulation speed. Before the model is put on an FPGA platform to operate, the model is discretized, the discretization method is various, such as an Euler method, a Runge-Kutta method, a linear multi-step method and the like, and a user can reasonably select the model according to the iteration times, the truncation error size, the solving precision and other factors of various discretization methods.
Example (c): taking an interleaved boost converter with the switching frequency of 200kHz as an example, a binary model which fully embodies the switching characteristics of the MOSFET is adopted to replace a non-linearized switching element in a circuit, a state space modeling method is used for obtaining a converter network equation of a continuous domain, and in order to perform simulation calculation on the FPGA, time domain simulation is performed after discretization. The fixed-step solver for the discretization of the state space equation has to be capable of processing the rigidity problem, high in numerical precision, stable in numerical value and suitable for processing the working condition of frequent switching of the switches of the power converter. The second-order implicit backward euler method meets the above requirements, and although the implicit formula cannot be directly solved, the implicit euler method can obtain higher precision. The state space equation is solved by adopting a pre-calculation inverse matrix method, so that the model is simulated in real time under the condition that the time step is only 30ns, and the Monte Carlo analysis speed is greatly improved.
3. Selecting target system response quantity
The selection principle of the target system response quantity is as follows:
1. in the system output, the object of interest is emphasized;
2. can embody the characteristics of the system.
Example (c): for an interleaved parallel converter, 2 steady state responses and 2 dynamic responses can be selected: the output voltage, the output voltage ripple, the output voltage overshoot when 50% of the load is unloaded and the regulation time are taken as the system response quantity.
4. Software implementation of system discretization model
And (3) realizing the solving process of the discretized model obtained in the step (2) and the system response quantity selected in the step (2) on a software development platform of the FPGA, completing the software design of the whole model on the FPGA for simulation, adding an output port for the target response quantity selected in the step (3), and establishing a simulation engineering file of the model.
Common implementations are:
【1】 Compiling simulation program codes by using Verilog/VHDL language, wherein common software development platforms comprise Vivado, Quartus II and the like;
【2】 An FPGA development kit Vivado and System Generator provided by Xilinx company realizes a model-based design method;
【3】 The ImpulsC compiler implements the conversion of C code into a hardware description language.
The user can flexibly adopt other software development platforms and methods to realize the software development according to actual conditions.
Example (c): the overall framework of the interleaved parallel converter system model software is shown in fig. 2 below.
5. Behavioral simulation of model software
And (4) after the step 4 is finished, performing behavior simulation on the model engineering file to determine whether the function of the system model is in accordance with expectation. Simulation testing can be performed on the model by adding/creating simulation source files in an FPGA software development platform.
If the model function is in accordance with expectation and the behavior simulation is passed, carrying out the next step; if the behavior simulation does not pass the expectation, the software implementation of the model has problems, and the step 5 is carried out again after the step 4 is returned to search and solve the problems.
6. Determining whether to reconstruct the model according to the resource requirements of the model simulation
And 5, after the step 5 is finished, synthesizing the model engineering file on the adopted FPGA software development platform, and selecting a proper FPGA model for the model simulation according to a resource use condition analysis report generated by the software development platform.
When the resources of the FPGA model selected by the user can not support the simulation of placing the whole system model on one FPGA chip, the detachable system model can simultaneously expand the number of FPGA board cards, and can be detached according to different functions of an actual system or different functions of each calculation module during software implementation.
7. Bit stream file for generative model
And 7, operating according to a platform flow in a software development platform, adding a pin constraint file in a model engineering file, determining I/O (input/output) for data acquisition output by a later model, and finally obtaining a bit stream file of the model.
8. Making an experimental plan
The following 4 criteria should be followed when making a specific experimental plan:
1) before formal experiments, the characteristics of the experimental system are ensured to be free of defects so as to contain all uncertainty sources and prevent underestimation or overestimation of uncertainty;
2) determining model input and SRQs measurement by the same expert, determining input parameters, initial and boundary conditions, and estimating uncertainty of the parameters;
3) the more the number of the prototype/real system is, the better the model/real system is, the parameter determination of each prototype/real system needs to be repeatedly measured for many times and then an average value is taken, so that the influence of the measurement error on the model form uncertainty quantification is reduced;
4) repeated experimental measurements are made on the SRQs to reduce the effect of measurement errors on model form uncertainty quantification.
The following test plans are made by way of example:
[1] 20 interleaved parallel converter prototypes are adopted, the working performance of the prototypes is ensured to be good before formal experiments, and the working environment temperature and the power supply quality are determined to be good;
[2] selecting 2 steady-state response quantities and 2 dynamic response quantities: the output voltage, the output voltage ripple, the output voltage overshoot when unloading 50% and the regulation time are used as SRQs;
[3] repeatedly measuring each parameter of 20 prototype machines for 10 times, taking an average value as a real system parameter, substituting the actual system parameter into the model for simulation, wherein the system response quantity of the open-loop static characteristic is as follows: the average value of the output voltage and the ripple peak-to-peak value of the output voltage; the system response of the closed loop dynamics is: overshoot of the output voltage when 50% of the load is suddenly unloaded and the regulation time with 5% as the error limit.
[4] In the open loop static characteristic and closed loop dynamic characteristic experiments, the following processes are adopted: and after the interleaved parallel boost converter works stably for 5 minutes, measuring the system response, and testing and recording the SRQs once every minute for 30 times.
9. Establishing an FPGA simulation experiment platform and carrying out experiments
When the uncertainty of the model form is quantified by using an improved surface integral measurement verification method, relevant parameters and experimental data of a real system need to be acquired. And (4) downloading the model bit stream file obtained in the step (7) into an FPGA chip, building an experiment platform, and then carrying out an experiment according to the specific experiment plan specified in the step (8). According to the actual situation, the construction of the experimental platform is divided into two situations:
【1】 The experimental platform architecture is shown in fig. 3 without any relevant parameters and experimental data of the real system. The control signal controls the Monte Carlo analysis in the FPGA simulation platform and the simulation process of substituting the parameters of the experimental prototype, and the control signal controls the working condition change corresponding to the SRQs formulated in the experimental plans of starting, loading/unloading and the like of the prototype. Monte Carlo analysis data output by the FPGA simulation platform, simulated data obtained by substituting experimental prototype parameters and experimental data of N prototypes are collected by the experimental data collection system, and then sent to the extraction function module of target system response quantity to extract SRQs, and then the cumulative probability distribution functions of the SRQs of the Monte Carlo analysis, the prototype parameter simulation and the actually measured prototype data are obtained through calculation respectively.
【2】 There are enough relevant parameters of a real system and historical experimental data required by the extraction of the SRQ, and the architecture of an experimental platform is shown in FIG. 4. Monte Carlo analysis data output by the FPGA simulation platform and simulation data obtained by substituting experimental prototype parameters into the simulation are collected by the experimental data collection system, and then are sent to the extraction function module of the target system response quantity together with the experimental data to extract SRQs, and then the cumulative probability distribution functions of the SRQs of the Monte Carlo analysis, the prototype parameter simulation and the measured data are obtained through calculation respectively.
10. Model uncertainty quantification
And (3) quantifying the uncertainty of the 3 CDFs obtained in the step (9) according to the following method.
[1] The Monte Carlo analysis obtains a cumulative probability distribution function (CDF) -F (x), which is a quantitative result of the parameter uncertainty as shown by the black line in FIG. 6.
[2] And quantizing the uncertainty of the model form by the real system parameter simulation CDF and the actually measured data CDF according to an improved surface product measurement verification method.
The improved profile product metric verification method is also implemented by comparing area regions obtained by integration between the CDF obtained by simulation and the CDF obtained by experiment, defining a region where the experimental result is greater than the simulation result as "d +", and defining a region where the experimental result is less than the simulation result as "d-", as shown in fig. 5.
Therefore, the range of the interval for quantitatively obtaining the model form uncertainty is as follows:
in the formula, FsIs a safety factor, the measured safety factor can be calculated using the following formula:
in the formula, F1＝1.25，F04. The above formula shows that the number of repeated measurements affects the value of the safety factor, and in the verification experiment, the safety factor should be reduced and the accuracy of the improved surface integral measurement verification method should be improved by adopting a method of measuring the SRQs as many times as possible.
[3] The method using the probability box yields the total uncertainty of the model.
In the probability box method, the uncertainty of the model parameters obtained by the Monte Carlo analysis obtained in [1] is plotted in CDF in the probability box as represented by the black curve in FIG. 6, and the uncertainty of the model form obtained in [2] is plotted in interval form in the probability box as represented by the red line in FIG. 6. In order to quantify the total uncertainty, a confidence level is specified so that the parameter uncertainty is also represented in the form of an interval in a probability box, and an upper limit and a lower limit of the uncertainty of the model are obtained, and the total uncertainty of the model is obtained by subtracting the lower limit from the upper limit. The example specifies a confidence level of 90% and the final probability box is shown in figure 6.
Claims (3)
1. A real-time simulation uncertainty quantification acceleration method is characterized by comprising the following steps:
step 1: obtaining a parameter value related to the expected characteristic of the system, wherein the parameter related comprises two parts: the model parameters of the system model reaching the expected characteristics and the tolerance of each parameter of the model;
step 2: establishing a discretization model of the system by using the related parameters obtained in the step 1;
and step 3: selecting target system response quantity;
and 4, step 4: the discretization model obtained in the step (2) and the solving process of the target system response quantity in the step (3) are realized on a software development platform of the FPGA, the software design of the whole model on the FPGA is completed, an output port is added for the target response quantity selected in the step (3), and a simulation engineering file of the model is established;
and 5: behavioral simulation of model software
Performing behavior simulation on the simulation engineering file of the model to determine whether the function of the system model meets the expectation; if the model function is in accordance with expectation and the behavior simulation is passed, carrying out the next step; if the behavior simulation does not pass the expectation, the software implementation of the model has problems, and the next step is carried out again after the problems are searched and solved in the step 4;
step 6: determining whether to reconstruct the model according to the resource requirements of the model simulation
Synthesizing a model engineering file on an adopted FPGA software development platform, and selecting an FPGA model which just meets or is larger than the calculation resources required by the model for the model simulation according to a resource use condition analysis report generated by the software development platform;
when resources of the FPGA model selected by a user can not support the simulation of placing the whole system model on one FPGA chip, splitting the system model and simultaneously expanding the number of FPGA board cards can be split according to different functions of an actual system or according to different functions of each calculation module in the software implementation;
and 7: bit stream file for generative model
Operating in a software development platform according to a platform flow, adding a pin constraint file in a model engineering file, determining I/O for data acquisition output by a later model, and finally obtaining a bit stream file of the model;
and 8: an experimental plan was made, following 4 criteria:
1. before formal experiments, the experimental system is ensured to have normal characteristics or no defects so as to contain all uncertainty sources and prevent underestimation or overestimation of uncertainty;
2. determining model input and SRQs measurement by the same expert, determining input parameters, initial and boundary conditions, and estimating uncertainty of the parameters;
3. the more the number of the prototype/real system is, the better the model/real system is, the parameter determination of each prototype/real system needs to be repeatedly measured for many times and then an average value is taken, so that the influence of the measurement error on the model form uncertainty quantification is reduced;
4. repeated experimental measurement is carried out on the SRQs so as to reduce the influence of measurement errors on model form uncertainty quantification;
and step 9: establishing an FPGA simulation experiment platform and carrying out experiments
Downloading the model bit stream file obtained in the step 7 into an FPGA chip, building an experiment platform, and then carrying out an experiment according to the experiment plan formulated in the step 8; the experimental platform is built under two conditions:
1. when no relevant parameters and experimental data of a real system exist, the control signal controls Monte Carlo analysis in the FPGA simulation platform and the parameters of an experimental prototype to be substituted into the simulation process, and the control signal controls the working condition change corresponding to SRQs formulated in the experimental plans of starting, loading/unloading and the like of the prototype; monte Carlo analysis data output by the FPGA simulation platform, simulation data obtained by substituting experimental prototype parameters into the simulation data and experimental data of N prototypes are collected by an experimental data collection system, and then are sent to an extraction function module of target system response quantity to extract SRQs, and then the cumulative probability distribution function CDF of each SRQs of the Monte Carlo analysis, the prototype parameter simulation and the actually measured prototype data is obtained through calculation;
2. relevant parameters of a real system and historical experimental data required by SRQ extraction exist, Monte Carlo analysis data output by an FPGA simulation platform and experimental prototype parameters are substituted into simulated data and are collected by an experimental data collection system, the simulated data and the experimental data are sent to an extraction function module of target system response quantity together to extract SRQs, and then the SRQs and the SRQs are respectively calculated to obtain an accumulative probability distribution function CDF of the SRQs of the Monte Carlo analysis, the prototype parameter simulation and the actually measured data;
step 10: model uncertainty quantification
And (3) carrying out uncertainty quantification on the 3 CDFs obtained in the step (9) according to the following method:
[1] the Monte Carlo analysis obtains a cumulative probability distribution function CDF (F (x)), which is a quantitative result of parameter uncertainty;
[2] quantizing model form uncertainty of a real system parameter simulation CDF and actual measurement data CDF according to an improved surface product measurement verification method;
the improved type area measurement verification method is also characterized in that the area between the system response quantity cumulative distribution function obtained by comparing simulation and the system response quantity cumulative distribution function obtained by experiment is defined as d + 'and the area with the experiment result smaller than the simulation result is defined as d-';
thus, the range over which model format uncertainty can be found is:
[F(x)-Fsd-,F(x)+Fsd+]
in the formula, FsIs a safety factor;
[3] obtaining the total uncertainty of the model by using a probability box method, drawing the uncertainty of the model parameters obtained by the Monte Carlo analysis obtained in the step (1) in the probability box in a CDF manner, and drawing the uncertainty of the model form obtained in the step (2) in the probability box in an interval manner; in order to quantify the total uncertainty, a confidence level is specified so that the parameter uncertainty is also represented in the form of an interval in a probability box, and an upper limit and a lower limit of the uncertainty of the model are obtained, and the total uncertainty of the model is obtained by subtracting the lower limit from the upper limit.
2. The uncertainty quantization acceleration method for real-time simulation of claim 1, wherein the discretization method in step 2 comprises Euler method, Runge-Kutta method, and linear multi-step method.
3. The uncertainty quantization acceleration method for real-time simulation of claim 1, characterized in that in step 5, simulation test is performed on the model by adding/creating simulation source files on the utilized FPGA software development platform.
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