CN111651354B - Uncertainty quantization acceleration method for real-time simulation - Google Patents
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Abstract
The invention relates to an uncertainty quantization acceleration method for real-time simulation, which is realized by a real-time simulation platform based on an FPGA, has small simulation step length and high speed, and solves the problem of time consumption and inefficiency of Monte Carlo analysis for carrying out parameter uncertainty quantization on a traditional computing platform; due to the real-time performance of the platform, the synchronism of measurement of the prototype system response and the model simulation system response is ensured, and the accuracy of the uncertainty of the model form of the improved area measurement verification method is improved.
Description
Technical Field
The invention belongs to the technical field of uncertainty quantization, and particularly relates to a real-time simulation uncertainty quantization acceleration method.
Background
Modeling and simulation have become an important research method in the engineering field, playing an important role in the system design, debugging and fault diagnosis process. However, in all model-based research methods, the simulation results of the model often deviate from the actual system. The deviation of the simulation from the actual system depends largely on the fineness of the model used and the uncertainty introduced by the simulation calculation process, and two sources of uncertainty exist in modeling and simulation-parameter uncertainty and model form uncertainty. At present, the model uncertainty quantization method with more practical operability comprises the following steps: and quantifying the uncertainty of the model parameters by adopting a Monte Carlo analysis method, quantifying the uncertainty of the model form by adopting an improved area measurement verification method, and quantifying the total uncertainty of the model by adopting a probability box method.
The Monte Carlo analysis method means that a large number of simulations are required for the model to obtain an analysis result with statistical significance. However, as the semiconductor technology advances, the switching frequency is also increasing, which reduces the size and weight of the converter. The disadvantage is that the efficiency of the simulation is greatly reduced by the increase of the switching frequency, and the simulation step size should generally be at least 20 times smaller than the switching frequency. Thus, when emulating a converter with a switching frequency of the order of 100kHz, the step size should be at least less than 1us, which step size would be about 2MHz less than 20 times the switching frequency if the accuracy of the emulation was further considered. On the traditional simulation platform, the computing power is already caught in the elbow, the simulation speed is low, so that Monte Carlo analysis is very time-consuming and low in efficiency, and difficulty is brought to quantification of parameter uncertainty. If the complexity of the system model is high, it is desired to increase the simulation speed, and it is common practice to increase the hardware configuration of the simulation platform, for example, to use a multi-core simulation platform, which greatly increases the cost.
In addition, the target system response (system response quantities, SRQs) of the model is measured from the simulated output data when model form uncertainty is quantified using a modified area metric verification method. As shown in fig. 1, if the step size 1 is smaller than the step size 2 and smaller than the step size 3, if the SRQs is selected as the overshoot and the adjustment time, the overshoot and the adjustment time measured by the simulation results under the three step sizes are different, and the results under the simulation step size 1 can best represent the real system characteristics. If the traditional simulation platform is adopted for simulation, when the simulation step length is not enough, the simulated and measured SRQs may be inaccurate or even wrong.
Disclosure of Invention
Technical problem to be solved
In order to solve the problem that the Monte Carlo analysis for quantifying the uncertainty of parameters on a traditional computing platform is time-consuming and low-efficient, the invention provides a real-time simulation uncertainty quantification acceleration method.
Technical proposal
The uncertainty quantization acceleration method for real-time simulation is characterized by comprising the following steps of:
step 1: obtaining a value of a correlation parameter of a desired characteristic of the system, wherein the correlation parameter comprises two parts: the system model achieves the tolerance of the model parameters of the expected characteristics and the parameters of the model;
step 2: establishing a discretization model of the system by using the related parameters obtained in the step 1;
step 3: selecting a target system response;
step 4: implementing the discretization model obtained in the step 2 and the solution process of the target system response in the step 3 on a software development platform of the FPGA, completing the software design of the whole model simulated on the FPGA, adding an output port for the target response selected in the step 3, and establishing a simulation engineering file of the model;
step 5: behavior simulation of model software
Performing behavior simulation on the simulation engineering file of the model to determine whether the system model function accords with the expectation; if the model function accords with the expectation, the behavior simulation passes, and the next step is carried out; if the behavior simulation does not accord with the expectation, the software implementation of the model has problems, and after the problems are searched and solved in the step 4, the next step is carried out again;
step 6: determining whether to reconstruct the model according to the model simulation resource requirement
Integrating the model engineering files on an adopted FPGA software development platform, analyzing and reporting the model simulation to select the FPGA model which just meets or is larger than the calculation resources required by the model according to the resource use condition generated by the software development platform;
when the resources of the FPGA model selected by the user cannot support the simulation by placing the whole system model on one FPGA chip, the system model is split, the number of the FPGA boards is expanded at the same time, and the FPGA boards can be split according to different functions of an actual system or different functions of each calculation module when the FPGA boards are implemented by software;
step 7: generating a bitstream file of a model
Operating in a software development platform according to a platform flow, adding a pin constraint file into a model engineering file, determining I/O for data acquisition output by a later model, and finally obtaining a bit stream file of the model;
step 8: an experimental plan was formulated, following 4 criteria:
1) Ensuring that the experimental system is normal or defect free prior to a formal experiment so as to contain all sources of uncertainty and prevent underestimation or overestimation of uncertainty;
2) Determining model input and SRQs measurement by the same expert, and determining input parameters, initial and boundary conditions and uncertainty problems of estimated parameters;
3) The more the number of the prototype/real system is, the better the number of the prototype/real system is, the average value is obtained after repeated measurement is needed for parameter measurement of each prototype/real system, so that the influence of measurement errors on model form uncertainty quantification is reduced;
4) Repeated experimental measurement is carried out on the SRQs so as to reduce the influence of measurement errors on model form uncertainty quantification;
step 9: constructing an FPGA simulation experiment platform and performing experiments
Downloading the model bit stream file obtained in the step 7 into an FPGA chip, building an experimental platform, and then performing experiments according to the experimental plan formulated in the step 8; the establishment of the experimental platform is divided into two cases:
1) When relevant parameters and experimental data of any real system are not available, the control signals control Monte Carlo analysis and experimental prototype parameters in the FPGA simulation platform to be substituted into the simulation process, and the control signals control the working condition changes corresponding to SRQs formulated in experimental plans such as starting, loading/unloading and the like of the prototype; the Monte Carlo analysis data and experimental prototype parameters output by the FPGA simulation platform are substituted into simulation data and experimental data of N prototypes, the simulation data and experimental data are acquired by an experimental data acquisition system and then are sent to an extraction functional module of target system response to extract SRQs, and then cumulative probability distribution functions CDF of the SRQs of the Monte Carlo analysis, prototype parameter simulation and actual measurement prototype data are calculated respectively;
2) The relevant parameters of the existing real system and the SRQ extract the required historical experimental data, monte Carlo analysis data and experimental prototype parameters output by the FPGA simulation platform are substituted into the simulated data and are collected by the experimental data collection system, then the data are sent to the extraction functional module of the target system response volume together with the experimental data to extract SRQs, and then the cumulative probability distribution function CDF of each SRQs of Monte Carlo analysis, prototype parameter simulation and measured data is obtained through calculation;
step 10: model uncertainty quantization
The uncertainty quantization is performed on the 3 CDFs obtained in the step 9 as follows:
[1] the Monte Carlo analysis obtains a cumulative probability distribution function CDF-F (x) which is a quantized result of parameter uncertainty;
[2] quantifying model form uncertainty by using a real system parameter simulation CDF and measured data CDF according to an improved area measurement verification method;
improved area metric verification is also achieved byComparing the area between the system response cumulative distribution function obtained by simulation and the system response cumulative distribution function obtained by experiment, and defining the area with the experimental result larger than the simulation result as'd' + "the region where the experimental result is smaller than the simulation result is defined as" d - ”；
Thus, the range in which the uncertainty of the model form can be found is:
wherein F is s Is a safety factor;
[3] obtaining the total uncertainty of the model by using a probability box method, drawing the model parameter uncertainty obtained by Monte Carlo analysis obtained in the step (1) in the probability box in a CDF mode, and drawing the model form uncertainty obtained in the step (2) in the probability box in a section mode; to quantify the total uncertainty, a confidence level is specified to convert the parameter uncertainty into a range form and to represent the range form in a probability box, to obtain an upper limit and a lower limit of the model uncertainty, and to obtain the total uncertainty of the model by subtracting the lower limit from the upper limit.
The discretization method in the step 2 comprises an Euler method, a Runge-Kutta method and a linear multi-step method. In step 5, simulation test is performed on the model by adding/creating a simulation source file on the used FPGA software development platform.
Advantageous effects
Compared with the DSP and the CPU, the FPGA has the following advantages: (1) all units can run in parallel, the calculation speed is high, and high real-time performance and high control precision can be achieved; (2) different hardware structures can be realized by modifying codes by using a hardware description language editing device, so that different functions are realized; (3) with the development of devices, the internal resources provided by the FPGA are more and more, and a plurality of IP hard cores and soft cores are integrated in a chip, so that the use is convenient. Therefore, the method for realizing the calculation of the model by adopting the FPGA has wide application prospect.
The biggest advantage of the FPGA is that the parallel operation characteristic is modeled in a proper mode, and the step size of real-time simulation can be reduced to nanosecond level by adopting a parallel resolving method, so that the method brings great benefits to the resolution of two problems in uncertainty quantization.
The invention provides a real-time simulation uncertainty quantization acceleration method, which solves the following 2 problems:
1. the Monte Carlo analysis adopted in the parameter uncertainty quantization in the uncertainty quantization of the system model is time-consuming, low in efficiency and high in resource requirement on the simulation platform;
2. in the uncertainty of the model form quantized by the improved area measurement verification method, the problem of inaccurate quantization of the model form is caused by inaccurate measurement of the model SRQs due to insufficient simulation.
The uncertainty quantization acceleration method for real-time simulation is realized on the basis of a real-time simulation platform of the FPGA, has small simulation step length and high speed, and solves the problem of time consumption and inefficiency of Monte Carlo analysis for carrying out parameter uncertainty quantization on a traditional computing platform; due to the real-time performance of the platform, the synchronism of measurement of the prototype system response and the model simulation system response is ensured, and the accuracy of the uncertainty of the model form of the improved area measurement verification method is improved.
Drawings
FIG. 1 conventional simulation platform
FIG. 2A-C converter system model software overview framework
FIG. 3 simulation experiment platform frame composition under case 1
FIG. 4 is a schematic diagram of a simulation experiment platform under condition 2
FIG. 5 is a schematic diagram of an improved area metric verification method
FIG. 6 schematic of probability box
FIG. 7 is a flow chart of the present invention
Detailed Description
The invention will now be further described with reference to examples, figures:
as shown in fig. 1, the steps are specifically implemented as follows:
1. acquiring values of parameters related to expected characteristics of system
The relevant parameters include two parts:
【1】 The system model achieves model parameters of expected characteristics and is also used as parameter rating value of Monte Carlo analysis
The calculation of the model parameters can be obtained by knowledge such as theoretical calculation equations, empirical formulas and the like in the related field, or by taking average values through multiple measurements of a real system.
【2】 The tolerance of each parameter of the model is the parameter tolerance of Monte Carlo analysis
The tolerance of the model parameters can be determined according to practical situations. If the power electronic component data manual generally gives the tolerance range of the component parameters, the working temperature and the component temperature drift of the system can be combined to make proper estimation; manufacturing tolerances for the mechanical structure; if the parameters are obtained by experimental measurement, the tolerance can be determined according to the measurement error.
2. Establishing a discretization model of a system
And (3) establishing a discretization model of the system by using the related parameters obtained in the step (1).
In the invention, the model is operated on a simulation computing platform based on the FPGA, and has great advantages in simulation speed. However, before the model is put on the FPGA platform to run, the model is discretized, the discretization method is various, such as an Euler method, a Runge-Kutta method, a linear multi-step method and the like, and a user can reasonably select according to the factors of iteration times, truncation error, solving precision and the like of various discretization methods.
Examples: taking an interleaved parallel boost converter with a switching frequency of 200kHz as an example, a binary model fully representing the switching characteristics of a MOSFET is adopted to replace a non-linearisable switching element in a circuit, a continuous-domain converter network equation is obtained by a state space modeling method, and in order to perform simulation calculation on an FPGA, discretization is required to be performed for time domain simulation. The fixed-step solver for state space equation dispersion must be capable of handling stiffness problems, have high numerical accuracy, have numerical stability, and be suitable for handling the working conditions of frequent switching of the switches of the power converter. The second-order implicit backward euler method meets the above requirements, and although the implicit formula cannot be directly solved, the implicit euler method can obtain higher precision. The state space equation is solved by adopting a pre-calculation inverse matrix method, so that the model is simulated in real time under the condition that the time step is only 30ns, and the Monte Carlo analysis speed is greatly improved.
3. Selecting target system response
The selection principle of the target system response quantity:
1. in the system output, the object of major interest;
2. can embody the characteristics of the system.
Examples: for an interleaved parallel converter, 2 steady state response amounts and 2 dynamic response amounts can be selected: output voltage, output voltage ripple, output voltage overshoot at 50% off load, and regulation time are used as system response.
4. Software implementation of a discretized model of a system
And (3) realizing the discretization model obtained in the step (2) and the solving process of the system response selected in the step (2) on a software development platform of the FPGA, completing the software design of the whole model simulated on the FPGA, adding an output port for the target response selected in the step (3), and establishing a simulation engineering file of the model.
The common implementation modes are as follows:
【1】 The simulation program codes are written by using Verilog/VHDL language, and common software development platforms include Vivado, quartz II and the like;
【2】 The FPGA development kit Vivado and System Generator provided by Xilinx company realizes a model-based design method;
【3】 The ImpulsC compiler implements the conversion of C code into hardware description language.
The user can flexibly adopt other software development platforms and methods to realize according to actual conditions.
Examples: the overall framework of the interleaved parallel converter system model software is shown in fig. 2 below.
5. Behavior simulation of model software
And 4, after the step 4 is completed, carrying out behavior simulation on the model engineering file to determine whether the system model function accords with the expectation. Simulation source files can be added/created to simulate the model by using the FPGA software development platform.
If the model function accords with the expectation, the behavior simulation passes, and the next step is carried out; if the behavior simulation does not pass, the software implementation of the model has problems, and after the step 4 is returned to find and solve the problems, the step 5 is carried out again.
6. Determining whether to reconstruct the model according to the model simulation resource requirement
And 5, after the step is completed, integrating the model engineering files on the adopted FPGA software development platform, and selecting a proper FPGA model for the model simulation according to the resource use condition analysis report generated by the software development platform.
When the resources of the FPGA model selected by the user cannot support the whole system model to be placed on one FPGA chip for simulation, the system model can be split to expand the number of the FPGA boards at the same time, and can be split according to different functions of an actual system or different functions of each calculation module when the system model is implemented by software.
7. Generating a bitstream file of a model
Through the steps 6, the model number and model architecture of the used FPGA are determined, the model software realizes the expected function, the step 7 is to operate according to the platform flow in a software development platform, add pin constraint files in model engineering files, determine I/O for data acquisition output by a later model, and finally obtain the bit stream file of the model.
8. Making an experiment plan
The following 4 criteria should be followed when making a specific experimental plan:
1) Before a formal experiment, ensuring that the experimental system characteristics are defect-free so as to contain all uncertainty sources and prevent underestimation or overestimation of uncertainty;
2) Determining model input and SRQs measurement by the same expert, and determining input parameters, initial and boundary conditions and uncertainty problems of estimated parameters;
3) The more the number of the prototype/real system is, the better the number is, the average value is obtained after repeated measurement is needed for parameter measurement of each prototype/real system, so that the influence of measurement errors on model form uncertainty quantification is reduced;
4) Repeated experimental measurements of SRQs are performed to reduce the effect of measurement errors on model form uncertainty quantization.
The following test plans were formulated by way of example:
[1] 20 staggered parallel converter prototypes are adopted, the working performance of the prototypes is ensured to be good before formal experiments, and the working environment temperature and the power supply quality of a power supply are determined to be good;
[2] 2 steady state response amounts and 2 dynamic response amounts are selected: output voltage, output voltage ripple, output voltage overshoot at 50% unloading and regulation time are taken as SRQs;
[3] repeatedly measuring each parameter of 20 prototypes for 10 times, taking an average value as a real system parameter, substituting the real system parameter into a model for simulation, wherein the system response of open loop static characteristics is as follows: the average value of the output voltage and the peak value of the output voltage ripple peak; the system response of the closed loop dynamic characteristic is: overshoot of the output voltage when 50% of the load is suddenly unloaded and regulation time with 5% as the error limit.
[4] In the open loop static characteristic and closed loop dynamic characteristic experiments, the following procedures are adopted: after the interleaved parallel boost converter was stable for 5 minutes, the system response was measured, SRQs were tested and recorded once per minute for a total of 30 tests.
9. Constructing an FPGA simulation experiment platform and performing experiments
In quantifying model form uncertainty using improved area metric verification, it is necessary to obtain relevant parameters and experimental data for a real system. And (3) downloading the model bit stream file obtained in the step (7) into an FPGA chip, building an experimental platform, and then performing experiments according to the specific experimental plan appointed in the step (8). According to actual conditions, the construction of the experimental platform is divided into two conditions:
【1】 The experimental platform architecture is shown in fig. 3 without any relevant parameters and experimental data of the real system. And controlling the Monte Carlo analysis and parameter substitution simulation process of the experimental prototype in the FPGA simulation platform by the control signal, and controlling the working condition change corresponding to SRQs formulated in experimental plans such as starting, loading/unloading and the like of the prototype by the control signal. And after the Monte Carlo analysis data and experimental prototype parameters output by the FPGA simulation platform are substituted into the simulated data and the experimental data of the N prototypes are acquired by the experimental data acquisition system, the acquired data are sent to the extraction functional module of the target system response to extract SRQs, and then the cumulative probability distribution function of each SRQs of the Monte Carlo analysis, prototype parameter simulation and actual measurement prototype data is respectively calculated.
【2】 There are enough relevant parameters of a real system and the needed historical experimental data for SRQ extraction, and the experimental platform architecture is shown in fig. 4. And after the Monte Carlo analysis data and experimental prototype parameters output by the FPGA simulation platform are substituted into the simulated data, the simulated data are collected by the experimental data collection system, the simulated data and the experimental data are transmitted to the extraction function module of the response of the target system together for extracting SRQs, and then the cumulative probability distribution function of each SRQs of the Monte Carlo analysis, prototype parameter simulation and actual measurement data is obtained through calculation.
10. Model uncertainty quantization
The 3 CDFs obtained in step 9 were subjected to uncertainty quantization as follows.
[1] Monte Carlo analysis yields a cumulative probability distribution function (cumulative distribution function, CDF) -F (x), which is a quantification of parameter uncertainty, as shown by the black line in FIG. 6.
[2] And quantifying model form uncertainty by using a real system parameter simulation CDF and measured data CDF according to an improved area measurement verification method.
The improved area measurement verification method is also to compare the area obtained by integration between the CDF obtained by simulation and the CDF obtained by experiment, and define the area with the experimental result larger than the simulation result as'd' + "the region where the experimental result is smaller than the simulation result is defined as" d - ", as shown in fig. 5.
Thus, the range of intervals in which model form uncertainty is quantified is:
wherein F is s Is a safety factor, the measured safety factor can be calculated using the following formula:
wherein F is 1 ＝1.25，F 0 =4. From the above formula, the number of repeated measurement can affect the value of the safety factor, and in the verification experiment, the safety factor should be reduced and the accuracy of the improved area measurement verification method should be improved by adopting a mode of measuring SRQs as many times as possible.
[3] The method using the probability box yields the total uncertainty of the model.
In the probability box method, model parameter uncertainty obtained by Monte Carlo analysis obtained in the step (1) is drawn in the probability box in a CDF mode, as represented by black curves in fig. 6, and model form uncertainty obtained in the step (2) is drawn in the probability box in a section mode, as represented by red lines in fig. 6. To quantify the total uncertainty, a confidence level is specified to convert the parameter uncertainty into a range form and to represent the range form in a probability box, to obtain an upper limit and a lower limit of the model uncertainty, and to obtain the total uncertainty of the model by subtracting the lower limit from the upper limit. The example specifies a confidence level of 90% and the final probability box is shown in fig. 6.
Claims (3)
1. The uncertainty quantization acceleration method for real-time simulation is characterized by comprising the following steps of:
step 1: obtaining a value of a correlation parameter of a desired characteristic of the system, wherein the correlation parameter comprises two parts: the system model achieves the tolerance of the model parameters of the expected characteristics and the parameters of the model;
step 2: establishing a discretization model of the system by using the related parameters obtained in the step 1;
step 3: selecting a target system response;
step 4: implementing the discretization model obtained in the step 2 and the solution process of the target system response in the step 3 on a software development platform of the FPGA, completing the software design of the whole model simulated on the FPGA, adding an output port for the target response selected in the step 3, and establishing a simulation engineering file of the model;
step 5: behavior simulation of model software
Performing behavior simulation on the simulation engineering file of the model to determine whether the system model function accords with the expectation; if the model function accords with the expectation, the behavior simulation passes, and the next step is carried out; if the behavior simulation does not accord with the expectation, the software implementation of the model has problems, and after the problems are searched and solved in the step 4, the next step is carried out again;
step 6: determining whether to reconstruct the model according to the model simulation resource requirement
Integrating the model engineering files on an adopted FPGA software development platform, analyzing and reporting the model simulation to select the FPGA model which just meets or is larger than the calculation resources required by the model according to the resource use condition generated by the software development platform;
when the resources of the FPGA model selected by the user cannot support the simulation by placing the whole system model on one FPGA chip, the system model is split, the number of the FPGA boards is expanded at the same time, and the FPGA boards can be split according to different functions of an actual system or different functions of each calculation module when the FPGA boards are implemented by software;
step 7: generating a bitstream file of a model
Operating in a software development platform according to a platform flow, adding a pin constraint file into a model engineering file, determining I/O for data acquisition output by a later model, and finally obtaining a bit stream file of the model;
step 8: an experimental plan was formulated, following 4 criteria:
8a, ensuring that the experimental system is normal or defect free before a formal experiment so as to contain all uncertainty sources and prevent underestimation or overestimation of uncertainty;
8b, determining model input and SRQs measurement by the same expert, and simultaneously determining input parameters, initial and boundary conditions and estimating uncertainty problems of the parameters;
8c, taking an average value after repeated measurement is needed for parameter measurement of each prototype/real system so as to reduce the influence of measurement errors on model form uncertainty quantification;
8d, carrying out repeated experimental measurement on the SRQs so as to reduce the influence of measurement errors on model form uncertainty quantification;
step 9: constructing an FPGA simulation experiment platform and performing experiments
Downloading the model bit stream file obtained in the step 7 into an FPGA chip, building an experimental platform, and then performing experiments according to the experimental plan formulated in the step 8; the establishment of the experimental platform is divided into two cases:
in the first case, when relevant parameters and experimental data of any real system are not available, a control signal is used for controlling Monte Carlo analysis in an FPGA simulation platform and substituting experimental prototype parameters into a simulation process, and a control signal is used for controlling the working condition changes corresponding to SRQs formulated in experimental plans such as starting, loading/unloading and the like of the prototype; the Monte Carlo analysis data and experimental prototype parameters output by the FPGA simulation platform are substituted into simulation data and experimental data of N prototypes, the simulation data and experimental data are acquired by an experimental data acquisition system and then are sent to an extraction functional module of target system response to extract SRQs, and then cumulative probability distribution functions CDF of the SRQs of the Monte Carlo analysis, prototype parameter simulation and actual measurement prototype data are calculated respectively;
in the second case, relevant parameters of the existing real system and SRQ extraction required historical experimental data, monte Carlo analysis data and experimental prototype parameters output by the FPGA simulation platform are substituted into simulated data and are collected by the experimental data collection system, the simulated data and the experimental data are sent to the extraction functional module of the target system response to extract SRQs, and then cumulative probability distribution functions CDF of the Monte Carlo analysis, prototype parameter simulation and actual measurement data SRQs are respectively calculated;
step 10: model uncertainty quantization
The uncertainty quantization is performed on the 3 CDFs obtained in the step 9 as follows:
[1] the Monte Carlo analysis obtains a cumulative probability distribution function CDF-F (x) which is a quantized result of parameter uncertainty;
[2] quantifying model form uncertainty by using a real system parameter simulation CDF and measured data CDF according to an improved area measurement verification method;
the improved area measurement verification method is also to compare the area between the simulated system response volume cumulative distribution function and the experimentally obtained system response volume cumulative distribution function, and define the area with the experimental result larger than the simulation result as'd' + "the region where the experimental result is smaller than the simulation result is defined as" d - ”；
Thus, the range in which the uncertainty of the model form can be found is:
[F(x)-F s d - ,F(x)+F s d + ]
wherein F is s Is a safety factor;
[3] obtaining the total uncertainty of the model by using a probability box method, drawing the model parameter uncertainty obtained by Monte Carlo analysis obtained in the step (1) in the probability box in a CDF mode, and drawing the model form uncertainty obtained in the step (2) in the probability box in a section mode; to quantify the total uncertainty, a confidence level is specified to convert the parameter uncertainty into a range form and to represent the range form in a probability box, to obtain an upper limit and a lower limit of the model uncertainty, and to obtain the total uncertainty of the model by subtracting the lower limit from the upper limit.
2. The method for accelerating the uncertainty quantization of real-time simulation according to claim 1, wherein the discretizing method in the step 2 comprises an Euler method, a ringe-Kutta method and a linear multi-step method.
3. The method for accelerating the uncertainty quantization of real-time simulation according to claim 1, wherein in the step 5, simulation test is performed on the model by adding/creating a simulation source file on the used FPGA software development platform.
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| Application Number | Priority Date | Filing Date | Title |
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| WO2016197552A1 (en) * | 2015-06-08 | 2016-12-15 | 广东工业大学 | High-speed platform movement parameter self-tuning method based on model identification and equivalent simplification |
| CN109583117A (en) * | 2018-12-07 | 2019-04-05 | 广东电网有限责任公司 | The determination method, apparatus and electronic equipment of power supply reliability |
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| CN104252550A (en) * | 2013-06-27 | 2014-12-31 | 中国矿业大学 | High-performance real-time simulation method based on FPGA (field programmable gate array) |
| WO2016197552A1 (en) * | 2015-06-08 | 2016-12-15 | 广东工业大学 | High-speed platform movement parameter self-tuning method based on model identification and equivalent simplification |
| CN109583117A (en) * | 2018-12-07 | 2019-04-05 | 广东电网有限责任公司 | The determination method, apparatus and electronic equipment of power supply reliability |
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