CN111650610B - Rowland C comprehensive signal generating equipment - Google Patents
Rowland C comprehensive signal generating equipment Download PDFInfo
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- CN111650610B CN111650610B CN202010481903.1A CN202010481903A CN111650610B CN 111650610 B CN111650610 B CN 111650610B CN 202010481903 A CN202010481903 A CN 202010481903A CN 111650610 B CN111650610 B CN 111650610B
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
- G01S19/00—Satellite radio beacon positioning systems; Determining position, velocity or attitude using signals transmitted by such systems
- G01S19/01—Satellite radio beacon positioning systems transmitting time-stamped messages, e.g. GPS [Global Positioning System], GLONASS [Global Orbiting Navigation Satellite System] or GALILEO
- G01S19/13—Receivers
- G01S19/23—Testing, monitoring, correcting or calibrating of receiver elements
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P90/00—Enabling technologies with a potential contribution to greenhouse gas [GHG] emissions mitigation
- Y02P90/02—Total factory control, e.g. smart factories, flexible manufacturing systems [FMS] or integrated manufacturing systems [IMS]
Abstract
The invention discloses a Rowland C comprehensive signal generating device which comprises a linear power supply module, a GPD/BD tame clock module, a signal generator core processing board, a high-precision signal attenuator group and a high-order band-pass filter module, wherein the signal generator is divided into the whole modules clearly, and the functions and interfaces of the modules are designed reasonably; the single SOC chip completes all signal processing algorithm designs, the signal processing framework is reasonably designed, 3 station chains and 9 station Rowland signals can be generated by the single chip simultaneously, 6 stations of the Rowland signals can be coded at the same time, and the single equipment can complete all tests of indexes such as Rowland C receiving equipment positioning, time service, interference resistance and the like; the design of the high-precision attenuator group can accurately control the intensity of an output signal, ensure the accuracy and the integrity of the Rowland C waveform, and the signal generating equipment can be used for time delay test and calibration of a Rowland C receiver and detection and calibration of the working state and the performance index of the receiver, and has wide application prospect.
Description
Technical Field
The invention relates to the technical field of signal and information processing, in particular to a Rowland C comprehensive signal generating device.
Background
The Rowland C is called remote navigation, is a remote hyperbolic radio navigation system designed in the last 60 th century, has the working distance of 2000 km and the working frequency of 100KHz, and is a land-based navigation positioning system commonly used in land, sea and air. Subsequently, due to the improvement of the technology, the Roland C system is modernized and improved, an Eurofi x coding technology is added, and the Roland C system has a time service function and is an international universal long-wave high-precision time service means.
The Rowland C receiver technology also advances, from analog hard-clipping sampling Rowland C receiver, to digital signal processing Rowland C receiver, from single-chain reception, to double-chain, multi-chain receiver, to the latest development of the present digitalized long-wavelength time service receiver, in addition to testing the actual signals received over the day, a rowland C signal generator is required, generating various steady continuous rowland C excitation signals, such as large and small signals, ECD envelope variation signals, signals under different signal-to-noise ratios, sky wave superimposed signals, continuous wave superimposed signals, cross interference signals, coded time service telegraph text signals and the like, the limit indexes of the receiving equipment are tested and verified, the limit performance of the equipment is improved, various internal parameters of the receiver can be calibrated, and the method is an indispensable instrument in the research process of the Roland C navigation time service receiver. In addition, in the production, inspection and delivery processes of the loran C receiving devices, the signal generator is also required to inspect and detect the receiving devices. The Rowland C comprehensive signal generating equipment is an instrument essential in the development, production and delivery processes of a Rowland C receiver.
The research and development manufacturers of the domestic Roland C equipment currently use the Roland C simulator imported from abroad in the last 90 th century, the A-8 and LSG-5 Roland C simulators are stopped in production by foreign manufacturers, the simulators are used for many years, the performance of the equipment is aged, the simulators are incomplete in function, the research and development requirements of latest receiving equipment cannot be completely met, and the main defects are as follows:
1. the single-chain signal design cannot meet the requirements of receiving capability test of more than two chains and multi-channel equipment;
2. there is no way to superimpose sky wave signals, and the influence of sky wave interference on equipment under different intensities and delay conditions cannot be detected;
3. there is no way to superimpose the continuous wave signals, and the influence of the continuous wave interference on the equipment under different conditions cannot be detected;
4. the method has the advantages that the method does not have a 'Eurofix' data modulation coding function, cannot detect the decoding function of equipment, cannot calibrate the internal delay of a receiver, and cannot detect the number of decoding channels of the receiver;
5. the time synchronization function with the guard guide equipment is not available, and the time service precision of the equipment cannot be detected in real time;
6. the simulator parameter setting resolution is not enough, and the requirement of fine testing cannot be met.
Related organizations develop simulator development work in China, products are not formed, and 1 model can not contain all functions.
Disclosure of Invention
The invention aims to solve the defects in the prior art and provides a Roland C comprehensive signal generating device. The Rowland C comprehensive signal generating equipment can be used as a signal source to provide an analog excitation signal for a Rowland-C receiver, and can simulate the station chain number, the station number, the noise, the field intensity, the signal peripherial difference change, the superposed sky wave continuous wave interference signal, the analog time difference positioning function, the modulation time service message analog station time service function and the like of a Rowland C signal.
In order to achieve the purpose, the invention adopts the following technical scheme:
a Rowland C comprehensive signal generation device comprises a linear power supply module, a GPD/BD tame clock module, a signal generator core processing board, a high-precision signal attenuator group and a high-order band-pass filter module.
The linear power supply module is used for rectifying and filtering the commercial power to obtain clean and stable direct-current voltage. The power supply is used for the GPD/BD taming clock module and the signal generator core processing board;
the GPD/BD discipline clock module is used for carrying out GPS/BD dual-mode time service and specifically comprises a GPS/BD data receiving module, a discipline clock circuit and a high-stability constant-temperature crystal oscillator. The tame clock circuit frequency calibrates the local frequency reference with the 1PPS generated by the satellite timing receiver. The advantage of good long-term stability of the satellite timing receiver is combined with the characteristic of good short-term stability of the local frequency standard; the module circuit adopts an FPGA as a core algorithm processor, a second-order tracking loop compares satellite 1PPS and local 1PPS in real time, a local clock difference is measured, a clock difference result adopts filtering to reduce jitter, and finally a high-stability constant-temperature crystal oscillator is adjusted through a DAC circuit, so that stable 10MHz pulse is obtained.
Signal generator core processing board: and the circuit is used for converting the digital signal after time service into an analog signal and generating and outputting a Rowland C signal.
The hardware part of the signal generator core processing board comprises a digital part and an analog part, and preferably, the digital part and the analog part are designed in an isolation mode, so that the influence of a digital circuit on the analog circuit is reduced.
The digital part comprises an SOC platform used for processing digital signals; the analog part comprises a power supply chip, a DA conversion chip, a low-pass filter, a signal amplifier and a signal combiner circuit and is used for processing analog signals. The electric signals are processed through the SOC platform, then analog signals are formed through the DA conversion chip, and the analog signals are subjected to low-pass filtering and 2-level signal amplification to form target analog signals.
The SOC platform software design can be divided into a frame design and a software algorithm design, wherein the frame design is realized in ZYNQ 7020 PL, and the software algorithm design is realized in ZYNQ 7020 PS.
High-precision signal attenuator group: the signal attenuator accurately controls the attenuation of the signal, and the integrity of the output Rowland C pulse waveform is maintained.
A high-order band-pass filter module: and the filter is used for processing the signal, so that the influence of out-of-band noise on the signal quality is reduced.
The SOC platform is in the frame design part, in order to realize that signal generator simulates the signal of 3 platform chains, 9 platforms, and the parameter that needs to set up includes: the amplitude, the peripherical difference, the sending time and the phase code of the Roland signal, the amplitude and the time delay parameter of the sky wave interference signal, the modulation (Eurofix modulation) of the time service coding message, the amplitude of the noise channel noise, the amplitude of the continuous wave interference and the like. According to analysis of characteristics of Rowland C signals, 3 signals, namely 1 main signal and 2 auxiliary signals, of the same station chain are sequentially arranged on a time AXIs, according to the characteristic that periodic parameters of the station chain are repeatedly sent, FPGA (ZYNQ 7020 PL) hardware resources are distributed according to the station chain on the framework design, according to the design idea of parallel processing of the station chain, and each module carries out data exchange and control processing through an AXI high-speed data bus, hardware interrupt and an ARM processor (ZYNQ 7020 PS).
Preferably, the frame portion of the SOC platform includes:
the synchronous module is used for generating synchronous reset signals for all modules;
the clock module is used for carrying out frequency multiplication on an external 10MHz clock, generating an internal required 100MHz clock and distributing the 10MHz clock;
the time measurement module is used for synchronizing the external GPS1PPS, generating local 1PPS, recording GTP pulse generation time of each channel in real time and calculating the day-second information in real time in a recursion manner;
the noise channel is used for storing noise signal data and continuous wave signal data into a BLOCK RAM of the FPGA, sending data parameters to drive a DAC chip according to clock rhythm, and sending the data through a data bus after the data is generated and calculated by the ARM processor;
the three signal channels are used for storing single complete pulse signal waveform data of the Rowland C signal, and the data comprises signal amplitude, peripherical difference, sky wave amplitude and sky wave delay; pulse transmission time sequence data including transmission time, phase encoding and Eurofix encoding information are also stored;
the ARM processor is used for realizing the functions of interface analysis, information transmission, synchronous GPS time, data transmission generation of each module and control of transmission time sequence;
each module carries out data exchange and control processing through an AXI high-speed data bus, hardware and an interrupt ARM processor.
Preferably, the software portion of the SOC platform includes scheduling interrupts and tasks. The tasks comprise a main task and a subtask of the system, wherein the main task is used for operating the embedded operating system and finishing the scheduling of each subtask; the subtasks include a pulse-per-second task and a Eurofix encoding task for three signal channels.
Preferably, the scheduling process of the main task to the subtask includes the following steps:
a1, initializing the embedded operating system;
a2, initializing parameters of Rowland C signals;
a3, calculating Loran C pulse waveform data, calculating time sequence data without Eurofix coding and noise channel data in sequence according to the parameters, and storing all the data in FPGA;
a4, sending a synchronization instruction, and starting the FPGA to operate;
a5: inquiring the serial port state, and judging whether the Rowland C signal parameter changes or not by analyzing serial port information; if the Rowland C signal parameters are changed, entering the step A3; if the Rowland C signal parameters are not changed, the step A6 is proceeded to;
a6, inquiring each interrupt state, and sending task call; inquiring whether the operating system has tasks to be operated; if the operating system has tasks to be performed, switching to each subtask to be performed, and then continuing to enter the step A5; if the operating system does not have a task to perform, step A5 is entered.
Preferably, the second pulse task is used for synchronizing a day-second counter in the FPGA, so that the second time of the ARM processor is consistent with the day-second time of the FPGA; and serial port statements sent by the GPS/BD module are analyzed, time information such as year, month, day, time, minute, second and the like is extracted, and relevant time in the ARM processor is updated in real time.
Preferably, in the Eurofix encoding task, three signal channels in the FPGA generate corresponding interrupts, and send the interrupts to the ARM processor to trigger an interrupt processing function, so as to call the Eurofix encoding task corresponding to each channel.
Preferably, the time for generating the interrupt is that after 48 pulses in the three odd-even cycles of the station in a station chain are transmitted, the interrupt is generated immediately;
when the pulse signal sending time sequence is finished, the Eurofix coding task in the ARM processor calculates the sending time sequence of the next group of pulse signals, and sends the time sequence data to the corresponding channel before the next group of pulse signals are sent, so that the pulse signals are controlled to be sent.
Preferably, the high-precision attenuator group comprises five signal attenuators, wherein three attenuators are connected to the signal channel, and one attenuator is connected to the noise channel; the attenuated signals are synthesized into a path of signal by a signal combining circuit on a signal generator processing board and finally output to a high-order band-pass filter by a total attenuator.
The invention has the beneficial effects that:
(1) the signal generator has clear integral module division and reasonable function and interface design of each module;
(2) the single SOC chip completes all signal processing algorithm designs, a signal processing frame is reasonably designed, data are exchanged in real time through an internal high-speed data bus, interruption requirements are processed in real time, the single chip can simultaneously generate 3 station chains and 9 station Rowland signals, 6 station real-time information can be coded simultaneously, and the single equipment can complete all tests of indexes such as Rowland C receiving equipment positioning, time service, interference resistance and the like;
(3) the design of the high-precision attenuator group can accurately control the strength of an output signal, meet the requirement that the signal is output from a large dynamic range of 25-114 dBuv, and simultaneously avoid low-order output of a DA chip in small signals, thereby ensuring accurate and complete Rowland C waveform.
In conclusion, the signal generator can simulate the station chain number, the station number, the noise, the field intensity and the signal cycle difference change of the Rowland C signal, superpose a sky wave continuous wave interference signal, simulate the time difference positioning function, simulate the station time service function of a modulation time service message simulation station, and the like. Therefore, the device can be used for time delay test and calibration of the Roland-C receiver, and detection and calibration of the working state and performance index of the receiver, and has wide application prospect.
Drawings
FIG. 1 is a schematic diagram showing the connection of the parts of the signal generating apparatus;
FIG. 2 is a block diagram of a linear power supply module of the present signal generating device;
FIG. 3 is a block diagram of the GPS/BD taming clock module of the present signal generating apparatus;
FIG. 4 is a block diagram of a hardware part of a signal generator processing board of the signal generating device;
FIG. 5 is a design diagram of the SOC platform software framework of the present signal generation device;
FIG. 6 is a flow chart of the subtask retrieval of the signal generating apparatus;
FIG. 7 is a flow chart of the second pulse task of the signal generating device;
FIG. 8 is a flow chart of the Eurofix encoding task of the signal generating device.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments.
Referring to fig. 1, the loran C integrated signal generator includes a linear power supply module, a GPD/BD tame clock module, a signal generator core processing board, a high-precision signal attenuator bank, and a high-order band-pass filter module.
Referring to fig. 2, the linear power module is used to rectify and filter the commercial power to obtain a clean and stable dc voltage. The linear power module comprises an EMI filter, a multi-stage capacitor array filter and a CLC filter three-stage filter. Alternating current 220V commercial power passes through level 1 EMI filter, reduces mains supply interference, outputs alternating current 15V through toroidal transformer, through rectifier bridge rectification and multistage capacitor array filtration, outputs direct current 15V voltage, steps down to DC12V through TL431, obtains clean stable direct current voltage through level 3 CLC filter at last.
Referring to fig. 3, the GPS/BD taming clock includes a GPS/BD receiving module, a taming clock circuit, and a highly stable constant temperature crystal oscillator. The GPS/BD receiving module adopts a u-blox special time service module LEA-M8T, and the time service precision can reach 20 ns. The tame clock circuit frequency calibrates the local frequency reference with the 1PPS generated by the satellite timing receiver. The 1PPS generated by the satellite timing receiver has certain jitter, but the long-term stability is better; the local frequency reference has good short-term stability, but has frequency drift, so the advantages of the local frequency reference and the local frequency reference are combined by utilizing 1PPS to correct the local frequency reference, and the method has the advantages of good long-term stability of a satellite timing receiver and good short-term stability of a local frequency standard. In the equipment, the FPGA is used as a core algorithm processor, the second-order tracking loop compares the satellite-guided 1PPS and the local 1PPS in real time, the local clock error is measured, the clock error result adopts filtering to reduce jitter, and finally the DAC circuit is used for adjusting the high-stability constant-temperature crystal oscillator, so that stable 10MHz pulse is obtained.
The signal generator processing board is used for converting the digital signal into an analog signal and generating and outputting a Rowland C signal, and comprises a hardware part and a software part.
Referring to fig. 4, the hardware portion of the signal generator core processing board includes an interface, a digital portion including an SOC platform and a switching power supply, and an analog portion including a power supply chip, a DA conversion chip, a low pass filter, a signal amplifier, and a signal combining circuit. The electric signals are processed through the SOC platform, then analog signals are formed through the DA conversion chip, and the analog signals are subjected to low-pass filtering and 2-level signal amplification to form target analog signals.
The digital part and the analog part of the core processing board of the signal generator are designed in an isolation mode, and the influence of a digital circuit on an analog circuit is reduced.
The analog power supply part adopts the latest LT3049 and LT3045 chips, the two chips adopt the latest model of ultra-low ripple linear voltage-stabilizing power supply chip of ADI company, the power supply ripple output is below 10uv, and the system noise can be ensured not to interfere with the signal output; 2 AD9767 DA conversion chips of 14-bit 125MSPS are adopted to form high-precision 4-channel signal output; the DA converted signal can output a +/-5V signal through low-pass filtering and 2-stage signal amplification.
The digital part adopts a ZYNQ 7020 platform, the ZYNQ 7020 is a complete SOC platform of 1 FPGA + ARM of Xilinx company, the integration level is high, the configuration is convenient and flexible, and a development space is provided for algorithm design.
The SOC platform software design can be divided into a framework design part and a software algorithm design part, wherein the framework design is realized in ZYNQ 7020 PL, and the software algorithm design is realized in ZYNQ 7020 PS.
In the frame design part, in order to realize that the signal generator simulates the signals of 3 station chains and 9 stations, the parameters required to be set include: the amplitude, the peripherical difference, the sending time and the phase code of the Roland signal, the amplitude and the time delay parameter of the sky wave interference signal, the modulation (Eurofix modulation) of the time service coding message, the amplitude of the noise channel noise, the amplitude of the continuous wave interference and the like. According to analysis of characteristics of Rowland C signals, 3 signals, namely 1 main signal and 2 auxiliary signals, of the same station chain are sequentially arranged on a time AXIs, according to the characteristic that periodic parameters of the station chain are repeatedly sent, FPGA (ZYNQ 7020 PL) hardware resources are distributed according to the station chain on the framework design, according to the design idea of parallel processing of the station chain, and each module carries out data exchange and control processing through an AXI high-speed data bus, hardware interrupt and an ARM processor (ZYNQ 7020 PS).
Referring to fig. 5, the present SOC platform framework includes:
the synchronous module is used for generating synchronous reset signals for all modules;
the clock module is used for carrying out frequency multiplication on an external 10MHz clock, generating an internal required 100MHz clock and distributing the 10MHz clock;
the time measurement module is used for synchronizing the external GPS1PPS, generating local 1PPS, recording GTP pulse generation time of each channel in real time and calculating the day-second information in real time in a recursion manner;
because the envelope characteristic of the Rowland C signal needs to be perfectly reproduced, the working frequency of the DAC chip is set at 10MHz and is far higher than the carrier frequency of the Rowland C signal by 100 KHz;
the noise channel is used for storing noise signal data and continuous wave signal data into a BLOCK RAM of the FPGA, sending data parameters to drive a DAC chip according to clock rhythm, and sending the data through a data bus after calculation and generation by the ARM processor;
the signal channel is used for storing single complete pulse signal waveform data of the Rowland C signal, and the data comprises signal amplitude, peripherical difference, sky wave amplitude, sky wave delay and the like; pulse transmission timing data including transmission time, phase encoding, Eurofix encoding, and the like are also stored. The pulse signal waveform data is generated once in the ARM and is sent to the BLOCK RAM to be stored, the data size is large, the parameters are not changed, the pulse signal data does not need to be sent repeatedly, and the bus occupation time is reduced.
After each group of odd-even periodic pulses are sent, the pulse sending time sequence data generate interruption to the ARM, the GTP pulse of the ARM reading time measurement module reaches the time, the time is calculated in real time, and the time sequence data are sent to the BLOCK RAM for temporary storage until the group of data are sent completely; under the clock driving, the signal channel sequentially reads pulse signal waveform data and sending time sequence data according to a 10MHz clock beat, and drives a DAC chip at the rear end;
and the ARM processor is used for realizing functions of interface analysis, information sending, synchronous GPS time, data sending generation of each module, control of sending time sequence and the like. Detailed description is given in the software algorithm.
The above framework design is implemented in the FPGA part of ZYNQ 7020 by using a VHDL hardware programming language.
In the software algorithm design part, in order to meet the requirements of processing a plurality of interrupts and real-time multitasking, the resources of the ARM processor need to be accurately managed. In the design, an ucos II embedded operating system is adopted to schedule the interruption and the task. Except for the main task of the embedded operating system, each interrupt is processed by adopting a corresponding subtask, and the subtasks comprise: second pulse task, three channel Eurofix encoding task.
Specifically, the main task is used for running the embedded operating system to complete the scheduling of each subtask. Referring to fig. 6, the scheduling flow of the sub-tasks by the main task includes the following steps:
a1, initializing the embedded operating system;
a2, initializing parameters of Rowland C signals;
a3, calculating Loran C pulse waveform data, calculating time sequence data without Eurofix coding and noise channel data in sequence according to the parameters, and storing all the data in FPGA;
a4, sending a synchronization instruction, and starting the FPGA to operate;
a5: inquiring the serial port state, and judging whether the Rowland C signal parameter changes or not by analyzing serial port information; if the Rowland C signal parameters are changed, entering the step A3; if the Rowland C signal parameters have not changed, proceed to step A6;
a6, inquiring each interrupt state, and sending task call; inquiring whether the operating system has tasks to be operated; if the operating system has tasks to be performed, switching to each subtask to be performed, and then continuing to enter the step A5; if the operating system does not have tasks to perform, then step A5 is entered.
In the second pulse task, an interrupt 1 is generated by a local 1PPS second pulse of a clock measurement module in the FPGA and is sent to an ARM processor to trigger the task. The task is mainly used for synchronizing a day-second counter in the FPGA, so that the second time of the ARM processor is consistent with the day-second time of the FPGA. If the system is in a GPS time synchronization state, the task also analyzes serial port statements sent by the GPS/BD module, extracts time information of year, month, day, hour, minute, second and the like, and updates related time in the ARM processor in real time. Referring to fig. 7, the execution of the pulse-per-second task specifically includes the following steps:
b1: initializing a task stack;
b2: judging whether the task is called; if yes, go to step B3; if not, continuing to judge whether the task is called;
b3: reading the day-second time in the PPGA;
b4: judging whether the second time in the FPGA is consistent with the second time in the ARM or not; if yes, go to step B5; if not, the second time in ARM is updated, and the step B4 is entered.
B5: judging whether the GPS synchronization mode exists; if so, go to step B6; if not, go to step B2;
b6: analyzing serial port data sent by the GPS/BD module;
b7: judging whether the information is consistent with the information of the time, the month, the day, the hour, the minute and the second in the ARM; if so, go to step B2; if not, the information of year, month, day, hour, minute and second in ARM is updated, and then the step B2 is entered.
In the Eurofix coding task, signal channels 1, 2 and 3 in the FPGA generate an interrupt 2, an interrupt 3 and an interrupt 4, and the interrupt 2, the interrupt 3 and the interrupt 4 are sent to an ARM processor to trigger an interrupt processing function, and the Eurofix coding task corresponding to each channel is called. The interruption is generated immediately after the transmission of 48 pulses in 3 station odd-even periods of 1 station chain. At the moment, a group of pulse sending time sequence is finished, the sending time sequence of the next group of pulses is calculated by an Eurofix coding task in the ARM processor, and the time sequence data is sent to a corresponding channel before the next group of pulses are sent, so that the pulse sending time is controlled. With reference to fig. 8, the execution of the Eurofix encoding task specifically comprises the following steps:
c1: initializing a task stack;
c2: judging whether the task is called; if so, go to step C3; if not, continuing to judge whether the task is called;
c3: judging whether the transmission of the whole frame of data is finished; if so, go to step C4; if not, go to step C7;
c3: reading the accurate time when the last GTP pulse of each station in the FPGA arrives, wherein the accuracy is 10 ns;
c4: reading the time of year, month, day, hour, minute and second running in the ARM, and calculating the content of the next group of telegraph texts according to the time of arrival of the last GTP pulse;
c5: performing CRC coding and RS coding;
c6: eurofix encoding was performed and the encoded data for each station was divided into 15 groups.
C7: 1 group of data in each station is taken in sequence to form a Rowland C pulse sending time sequence;
c8: and sending the data to the FPGARAM for caching, waiting for the FPGA to call, and then continuing to enter the step C2.
The high-precision attenuator group is used for signal attenuation. In the embodiment, five high-precision 1dB stepping signal attenuators are selected, the attenuation can be maximally 60dB, three attenuators are connected with a signal channel, one attenuator is connected with a noise channel, attenuated signals are combined into a path of signal through a signal combining circuit on a signal generator processing board, and finally the path of signal is output to a high-order band-pass filter through a total attenuator. In this embodiment, the attenuation of each channel signal can be accurately controlled individually by the five high-precision attenuator groups, and the attenuation of the total signal can be accurately controlled by the total attenuator. Meanwhile, the relative relation between the signal intensity of the main station and the signal intensity of the auxiliary station in the same channel can be set through controlling the serial port, so that the low-bit output (the condition of needing small signals) of the DA chip can be avoided as much as possible, the integrity of the output Rowland C pulse waveform can be ensured as much as possible, and the purpose of outputting high-quality signals is achieved.
Higher order bandpass filters are used to reduce the effect of out-of-band noise on signal quality. The higher-order bandpass filter in this embodiment is an active 8 th-order bandpass filter, and the bandwidth of the filter is 70-130Khz, which can further reduce the influence of out-of-band noise on the signal quality.
The Rowland C comprehensive signal generating equipment has high integration level and perfect functions, and a single device can test all the technical indexes of the current latest Rowland C navigation time service receiver and monitoring receiver, which are specifically shown in the following steps:
(1) the Rowland C signals of 3 station chains and 9 stations in total can be generated simultaneously, and the requirement of the receiving capability test of the multi-channel equipment is met;
(2) sky wave signals with 1dB resolution and 0.1us delay resolution can be generated, and the influence of sky waves on equipment under different conditions can be accurately detected;
(3) 2 continuous wave interferences with 1KHz and 1dB resolution can be generated simultaneously, and the influence of the continuous wave interferences on equipment under different conditions can be detected;
(4) the system has a 'Eurofix' data modulation coding function, can simultaneously code signals of 6 stations, can synchronously guide in real time, accurately trace the source UTC time, can detect the decoding function of equipment, can calibrate the internal delay of a receiver, can detect the number of decoding channels of the receiver, and can determine the time service precision of receiving equipment;
(5) the simulator has high parameter setting resolution and can meet the requirement of fine test.
The above description is only for the preferred embodiment of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art should be considered to be within the technical scope of the present invention, and the technical solutions and the inventive concepts thereof according to the present invention should be equivalent or changed within the scope of the present invention.
Claims (7)
1. A loran C synthesis signal generating apparatus, comprising:
a linear power supply module: rectifying and filtering the mains supply to obtain clean and stable direct-current voltage for supplying power to a GPD/BD tame clock module and a signal generator core processing board;
GPD/BD tame clock module: the system is used for carrying out GPS/BD dual-mode time service; the device comprises a GPS/BD data receiving module, a taming clock circuit and a high-stability constant-temperature crystal oscillator;
signal generator core processing board: the system is used for converting the digital signal into an analog signal and generating and outputting a Rowland C signal; the hardware part of the signal generator core processing board comprises a digital part and an analog part, and the digital part and the analog part are designed in an isolated mode;
the digital part comprises an SOC platform used for processing digital signals; the software part of the SOC platform comprises the steps of scheduling interrupts and tasks; the tasks comprise a main task and a subtask of the system, wherein the main task is used for operating the embedded operating system and finishing the scheduling of each subtask; the subtasks comprise a pulse-per-second task and a Eurofix encoding task of three signal channels;
the analog part comprises a power supply chip, a DA conversion chip, a low-pass filter, a signal amplifier and a signal combiner circuit and is used for processing analog signals;
high-precision signal attenuator group: accurately controlling the attenuation of the signal through a signal attenuator, and keeping the integrity of the output Rowland C pulse waveform;
a high-order band-pass filter module: the filter is used for processing the signal, so that the influence of out-of-band noise on the signal quality is reduced;
the frame portion of the SOC platform includes:
the synchronous module is used for generating synchronous reset signals for all modules;
the clock module is used for carrying out frequency multiplication on an external 10MHz clock, generating an internal required 100MHz clock and distributing the 10MHz clock;
the time measurement module is used for synchronizing the external GPS1PPS, generating local 1PPS, recording GTP pulse generation time of each channel in real time and calculating the day-second information in real time in a recursion manner;
the noise channel is used for storing noise signal data and continuous wave signal data into a BLOCK RAM of the FPGA, sending data parameters to drive a DAC chip according to clock rhythm, and sending the data through a data bus after calculation and generation by the ARM processor;
the three signal channels are used for storing single complete pulse signal waveform data of the Rowland C signal, and the data comprises signal amplitude, peripherical difference, sky wave amplitude and sky wave delay; pulse transmission time sequence data including transmission time, phase encoding and Eurofix encoding information are also stored;
the ARM processor is used for realizing the functions of interface analysis, information transmission, synchronous GPS time, data transmission generation of each module and control of transmission time sequence;
each module carries out data exchange and control processing through an AXI high-speed data bus, hardware and an interrupt ARM processor.
2. The roland C integrated signal generating device according to claim 1, wherein the linear power supply module performs three-stage filtering processing on the commercial power, and the commercial power sequentially passes through three filters, namely an EMI filter, a multi-stage capacitor array filter and a CLC filter, so as to obtain a clean and stable dc voltage.
3. The Rowland C integrated signal generation device according to claim 2, wherein said main task is configured to schedule the subtasks according to the following steps:
a1, initializing the embedded operating system;
a2, initializing parameters of Rowland C signals;
a3, calculating Loran C pulse waveform data, calculating time sequence data without Eurofix coding and noise channel data in sequence according to the parameters, and storing all the data in FPGA;
a4, sending a synchronization instruction, and starting the FPGA to operate;
a5: inquiring the serial port state, and judging whether the Rowland C signal parameter changes or not by analyzing the serial port information, if the Rowland C signal parameter changes, entering the step A3; if the Rowland C signal parameters have not changed, proceed to step A6;
a6, inquiring the interruption state, sending task call, inquiring whether the operating system has tasks to run, if the operating system has tasks to run, switching to the running of each subtask, and then continuing to enter the step A5; if the operating system does not have tasks to perform, then step A5 is entered.
4. The Rowland C integrated signal generating device of claim 2, wherein the pulse-per-second task is used for synchronizing a day-second counter in the FPGA so that the second of the ARM processor is consistent with the second of the FPGA day; and serial port statements sent by the GPS/BD module are analyzed, time information of year, month, day, hour, minute and second is extracted, and relevant time in the ARM processor is updated in real time.
5. The apparatus of claim 2, wherein in the Eurofix encoding task, corresponding interrupts generated by three signal channels in the FPGA are sent to the ARM processor to trigger an interrupt handling function, and the Eurofix encoding task corresponding to each channel is called.
6. The apparatus of claim 5, wherein the interrupt is generated immediately after 48 pulses of odd-even cycles of three stations in a station chain are transmitted;
when the pulse signal sending time sequence is finished, the Eurofix coding task in the ARM processor calculates the sending time sequence of the next group of pulse signals, and sends the time sequence data to the corresponding channel before the next group of pulse signals are sent, so that the pulse signals are controlled to be sent.
7. The roland C integrated signal generating apparatus according to claim 2 wherein said high precision signal attenuator group comprises five signal attenuators, three of which are connected to the signal path and one of which is connected to the noise path; the attenuated signals are synthesized into a path of signal by a signal combining circuit on a signal generator processing board and finally output to a high-order band-pass filter by a total attenuator.
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