CN111640785A - LIGBT device with multiple grooves - Google Patents
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- CN111640785A CN111640785A CN202010535078.9A CN202010535078A CN111640785A CN 111640785 A CN111640785 A CN 111640785A CN 202010535078 A CN202010535078 A CN 202010535078A CN 111640785 A CN111640785 A CN 111640785A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
- H01L29/0623—Buried supplementary region, e.g. buried guard ring
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
Abstract
The invention relates to a LIGBT device with multiple grooves, and belongs to the technical field of power semiconductors. According to the LIGBT device with the multiple grooves, the appearance of a second conduction type semiconductor heavily-doped diffusion region below an anode is improved through groove etching and high-temperature annealing diffusion, the area of the region is saved, and uniform doping of the region is realized, so that the conductivity modulation effect is enhanced, and lower conduction voltage drop, conduction resistance and forward conduction power consumption are obtained; by forming the second conductivity type polysilicon trench region in the first conductivity type drift region, a better electric field distribution can be achieved, thereby obtaining a better blocking characteristic and area optimization.
Description
Technical Field
The invention belongs to the technical field of power semiconductors, and particularly relates to an LIGBT device with multiple grooves.
Background
With the development of society and the progress of science and technology, the demand of human beings on high-performance power devices is increasing day by day, an Insulated Gate Bipolar Transistor (IGBT) is a composite power device combining a Bipolar transistor and an MOS (metal oxide semiconductor) transistor, the current of the power MOS can be amplified through a BJT under the on-state condition, and the total current of the device can be improved due to the fact that the resistance of a drift region is reduced by the conductance modulation effect of the BJT device under the large-current condition, so that the IGBT has the double characteristics of high input impedance of the MOS Gate device and conductance modulation of the BJT device, well compromises the on-state current and the switching time of the device, and becomes a typical representative of a novel power device.
Compared with a longitudinal structure, the LIGBT (Lateral IGBT) is easier to integrate on a silicon substrate, and all electrodes of the LIGBT device are positioned on the same surface, so that a back etching process is not needed, the production difficulty and the cost are reduced, the LIGBT device becomes one of core power devices for promoting the development of a single-chip integrated power system chip, and the LIGBT (Lateral IGBT) is widely applied to the fields of frequency conversion household appliances, industrial production, power systems and the like. However, as shown in fig. 1, the conventional LIGBT device has a contradiction between high breakdown voltage and small area, and the improvement of the breakdown voltage is restricted.
Disclosure of Invention
The invention aims to solve the technical problem in the prior art and provides a LIGBT device with multiple grooves.
In order to solve the above technical problem, an embodiment of the present invention provides a LIGBT device with multiple trenches, including a second conductive type substrate, a first conductive type drift region, a second conductive type body region, a second conductive type heavily doped region, a first conductive type heavily doped region, a second conductive type heavily doped diffusion region, a second conductive type polysilicon heavily doped trench region, a second conductive type polysilicon trench region, an isolation dielectric layer, a cathode electrode, a planar gate structure and an anode electrode;
the first conductive type drift region is located on the second conductive type substrate; the second conductive type body region is located in the first conductive type drift region and on the second conductive type substrate; the second conductive type heavily doped region and the side surface of the first conductive type heavily doped region are in mutual contact and are positioned on one side of the top layer of the second conductive type body region;
the second conductive type heavily doped diffusion region is positioned on one side, far away from the second conductive type body region, of the top layer of the first conductive type drift region, the second conductive type polysilicon heavily doped diffusion regions are positioned on the top layer of the second conductive type heavily doped diffusion region at intervals, and the second conductive type heavily doped diffusion region is formed by the diffusion of the second conductive type polysilicon heavily doped diffusion region;
the second conductive type polycrystalline silicon groove regions are arranged on the top layer of the first conductive type drift region at intervals and are arranged between the second conductive type body region and the second conductive type heavily doped diffusion region;
the cathode electrode is positioned on the second conductive type heavily doped region and the first portion of the first conductive type heavily doped region; the planar gate structure is positioned on the second part of the first conductive type heavily doped region, the second conductive type body region and part of the first conductive type drift region; the anode electrode is positioned on the second conductive type polycrystalline silicon heavily doped groove regions;
the isolation dielectric layer is positioned on the first conductive type drift region among the cathode electrode, the planar gate structure and the anode electrode.
On the basis of the technical scheme, the invention can be further improved as follows.
Further, the planar gate structure comprises the gate oxide layer and a polysilicon gate electrode positioned on the gate oxide layer.
Further, the isolation dielectric layer is silicon dioxide.
Furthermore, in the preparation process, the transverse width, the longitudinal length, the spacing and the number of the grooves of the second conductive type polycrystalline silicon groove regions are adjusted by changing the photolithography.
Furthermore, in the preparation process, the transverse width, the longitudinal length, the distance and the number of the grooves of the second conductive type polycrystalline silicon heavily doped groove regions are adjusted by changing a photolithography mask.
Further, the first conductive type is an N type, and the second conductive type is a P type.
Further, the first conductive type is a P type, and the second conductive type is an N type.
The invention has the beneficial effects that: compared with the traditional LIGBT, the LIGBT device with the multiple grooves has the advantages that the doping distribution of the collector region is more uniform, the concentration is adjustable, the distribution of an electric field in a body is optimized, the stronger reverse blocking capability can be realized, the overcurrent capability is improved, meanwhile, the conduction voltage drop is lower, the conduction resistance is smaller, the forward conduction power consumption is lower, and the area of the device can be smaller.
Drawings
FIG. 1 is a schematic diagram of a conventional LIGBT;
fig. 2 is a schematic diagram of a first structure of a LIGBT device with multiple trenches, according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of a second LIGBT device with multiple trenches according to an embodiment of the present invention;
fig. 4 is a schematic diagram of a third structure of a LIGBT device with multiple trenches, according to an embodiment of the present invention.
In the drawings, the components represented by the respective reference numerals are listed below:
201. a second conductive type substrate, 202, a first conductive type drift region, 203, a second conductive type body region, 204, a second conductive type heavily doped region, 205, a first conductive type heavily doped region, 206, a second conductive type heavily doped diffusion region, 207, a gate oxide layer, 208, an isolation dielectric layer, 209, a cathode electrode, 210, a polysilicon gate electrode, 211, an anode electrode, 212, a second conductive type polysilicon trench region, 213 and a second conductive type polysilicon heavily doped trench region, 212-11 to 212-1N is the transverse width of each trench of the plurality of second conductive type polysilicon trench regions, 212-21 to 212-2(N-1) is the distance between adjacent trenches in the plurality of second conductive type polysilicon trench regions, 212-31 to 212-3M is the longitudinal length of each trench of the plurality of second conductive type polysilicon trench regions, 213-11 to 213-1M are the lateral width of each of the plurality of heavily doped trench regions of second conductivity type polysilicon, 213-21 to 213-2(M-1) are the spacing between adjacent trenches in the plurality of heavily doped trench regions of second conductivity type polysilicon, and 213-31 to 213-3M are the longitudinal length of each of the plurality of heavily doped trench regions of second conductivity type polysilicon, where N and M are positive integers.
Detailed Description
The principles and features of this invention are described below in conjunction with the following drawings, which are set forth by way of illustration only and are not intended to limit the scope of the invention.
As shown in fig. 2, a LIGBT device with multiple trenches according to a first embodiment of the present invention includes a second conductive type substrate 201, a first conductive type drift region 202, a second conductive type body region 203, a second conductive type heavily doped region 204, a first conductive type heavily doped region 205, a second conductive type heavily doped diffusion region 206, a second conductive type polysilicon heavily doped trench region 213, a second conductive type polysilicon trench region 212, an isolation dielectric layer 208, a cathode electrode 209, a planar gate structure and an anode electrode 211;
the first conductive-type drift region 202 is located on the second conductive-type substrate 201; the second conductive-type body region 203 is located in the first conductive-type drift region 202 and on the second conductive-type substrate 201; the second conductive type heavily doped region 204 and the first conductive type heavily doped region 205 are positioned on one side of the top layer of the second conductive type body region 203, and the side surfaces of the second conductive type heavily doped region and the first conductive type heavily doped region are mutually contacted;
the heavily doped diffusion region 206 of the second conductivity type is located on one side of the top layer of the drift region 202 of the first conductivity type far away from the body region 203 of the second conductivity type, a plurality of heavily doped trench regions 213 of polysilicon of the second conductivity type are spaced from each other and located on the top layer of the heavily doped diffusion region 206 of the second conductivity type, and the heavily doped diffusion region 206 of the second conductivity type is formed by diffusing the heavily doped trench regions 213 of polysilicon of the second conductivity type;
a plurality of second conductive-type polysilicon trench regions 212 are spaced from each other and located at the top layer of the first conductive-type drift region 202 and between the second conductive-type body region 203 and the second conductive-type heavily doped diffusion region 206;
the cathode electrode 209 is located on the second conductive-type heavily doped region 204 and a first portion of the first conductive-type heavily doped region 205; the planar gate structure is located on a second portion of the heavily doped first-conductivity-type region 205, the second-conductivity-type body region 203, and a portion of the first-conductivity-type drift region 202; the anode electrode 211 is located on the plurality of second conductive type polysilicon heavily doped trench regions 213;
the isolation dielectric layer 208 is positioned on the first conductive-type drift region 202 between the cathode electrode 209, the planar gate structure and the anode electrode 211.
In the above embodiments, the first conductive type may be an N type, and the second conductive type may be a P type. The second conductive type polysilicon trench region 212 is formed by etching a trench, and the trench is filled with second conductive type polysilicon, preferably, the longitudinal lengths of the plurality of second conductive type polysilicon trench regions 212 are the same, and the distances between adjacent trenches in the plurality of second conductive type polysilicon trench regions 212 are the same;
the heavily doped trench region 213 of the second conductivity type polysilicon is formed by etching a trench, and the trench is filled with heavily doped second conductivity type polysilicon, preferably, the longitudinal lengths of the heavily doped trench regions 213 of the second conductivity type polysilicon are consistent, and the distances between adjacent trenches in the heavily doped trench regions 213 of the second conductivity type polysilicon are the same;
the heavily doped diffusion region 206 of the second conductivity type is preferably formed by high temperature anneal diffusion of a heavily doped trench region 213 of polysilicon of the second conductivity type.
Taking an N-type LIGBT as an example, the working principle of the invention is explained as follows:
according to the LIGBT device with the multiple grooves, the P-type polycrystalline silicon heavily-doped groove region 213 is formed in the N-type drift region 202 through etching, the P-type heavily-doped diffusion region 206 is formed through high-temperature annealing diffusion, and the P-type polycrystalline silicon groove region 212 is formed in the N-type drift region 202. When the positive voltage applied to the polysilicon gate electrode 210 exceeds the threshold voltage, the surface of the P-type body region 203 below the polysilicon gate electrode 210 is inverted and forms a channel, electrons in the N-type heavily doped region 205 enter the N-type drift region 202 through the channel, and the NMOS part in the LIGBT is turned on; meanwhile, when a sufficient forward voltage is applied to the anode electrode 211, a PN junction formed by the P-type heavily doped diffusion region 206 and the N-type drift region 202 is turned on, so that a large number of holes are injected into the N-type drift region 202 by the P-type heavily doped diffusion region 206, and the LIGBT structure is turned on.
Because the P-type heavily doped diffusion region 206 is formed by high-temperature annealing diffusion of the P-type polysilicon heavily doped trench region 213, compared with the traditional diffusion process, the P-type heavily doped diffusion region 206 has more uniform doping concentration, so that the conductance modulation effect is stronger when the LIGBT is conducted, the forward conduction voltage drop and the conduction power consumption are reduced, and the area of the device is saved because the formed P-type heavily doped diffusion region 206 has smaller lateral expansion; when the device is forward voltage-resistant, the N-type drift region 202 and the P-type body region 203 are mainly used for resisting voltage, and the electric field in the N-type drift region 202 is in trapezoidal distribution due to the P-type polycrystalline silicon groove region 212 in the N-type drift region 202, so that the breakdown voltage is improved, and the reverse voltage resistance is the same, so that the shorter drift region length realizes higher blocking characteristic, the device area is saved, and the device cost is reduced.
Optionally, as shown in fig. 2, the planar gate structure includes the gate oxide layer 207 and a polysilicon gate electrode 210 thereon.
Optionally, the isolation dielectric layer 208 is silicon dioxide.
Alternatively, as shown in fig. 3 to 4, during the preparation process, the lateral width, the longitudinal length, the pitch, and the number of trenches of the plurality of second conductivity type polysilicon trench regions 212 are adjusted by changing photolithography.
In the above embodiments, a person skilled in the art can adjust the lateral width, the longitudinal length, the pitch, and the number of trenches of the plurality of second conductivity type polysilicon trench regions 212 according to actual needs.
Alternatively, as shown in fig. 3 to 4, during the preparation process, the lateral width, the longitudinal length, the pitch, and the number of trenches of the plurality of heavily doped trench regions 213 of second conductivity type are adjusted by changing photolithography.
In the above embodiments, a person skilled in the art can adjust the lateral width, the longitudinal length, the pitch, and the number of the trenches of the plurality of heavily doped trench regions 213 of second conductivity type polysilicon according to actual needs.
Optionally, the first conductivity type is an N-type, and the second conductivity type is a P-type.
Optionally, the first conductivity type is a P type, and the second conductivity type is an N type.
According to the LIGBT device with the multiple grooves, the appearance of a second conduction type semiconductor heavily doped region below an anode is improved through groove etching and high-temperature annealing diffusion, the area of the region is saved, and uniform doping of the region is realized, so that the conductivity modulation effect is enhanced, and lower conduction voltage drop, conduction resistance and forward conduction power consumption are obtained; by forming the second conductivity type polysilicon trench region in the first conductivity type drift region, a better electric field distribution can be achieved, thereby obtaining a better blocking characteristic and area optimization.
In the description of the present invention, it is to be understood that the terms "central," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," "axial," "radial," "circumferential," and the like are used in the orientations and positional relationships indicated in the drawings for convenience in describing the invention and to simplify the description, and are not intended to indicate or imply that the referenced devices or elements must have a particular orientation, be constructed and operated in a particular orientation, and are therefore not to be considered limiting of the invention.
In the present invention, unless otherwise expressly stated or limited, the first feature "on" or "under" the second feature may be directly contacting the first and second features or indirectly contacting the first and second features through an intermediate. Also, a first feature "on," "over," and "above" a second feature may be directly or diagonally above the second feature, or may simply indicate that the first feature is at a higher level than the second feature. A first feature being "under," "below," and "beneath" a second feature may be directly under or obliquely under the first feature, or may simply mean that the first feature is at a lesser elevation than the second feature.
In the description herein, references to the description of the term "one embodiment," "some embodiments," "an example," "a specific example," or "some examples," etc., mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, the schematic representations of the terms used above are not necessarily intended to refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, various embodiments or examples and features of different embodiments or examples described in this specification can be combined and combined by one skilled in the art without contradiction.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents, improvements and the like that fall within the spirit and principle of the present invention are intended to be included therein.
Claims (7)
1. An LIGBT device with multiple grooves is characterized by comprising a second conduction type substrate (201), a first conduction type drift region (202), a second conduction type body region (203), a second conduction type heavily doped region (204), a first conduction type heavily doped region (205), a second conduction type heavily doped diffusion region (206), a second conduction type polysilicon heavily doped groove region (213), a second conduction type polysilicon groove region (212), an isolation dielectric layer (208), a cathode electrode (209), a planar gate structure and an anode electrode (211);
the first conductivity type drift region (202) is located on the second conductivity type substrate (201); the second conductivity type body region (203) is located in the first conductivity type drift region (202) and on the second conductivity type substrate (201); the side surfaces of the second conductive type heavily doped region (204) and the first conductive type heavily doped region (205) are in mutual contact and are positioned on one side of the top layer of the second conductive type body region (203);
the second conductive type heavily doped diffusion region (206) is positioned on one side, far away from the second conductive type body region (203), of the top layer of the first conductive type drift region (202), a plurality of second conductive type polysilicon heavily doped trench regions (213) are positioned on the top layer of the second conductive type heavily doped diffusion region (206) at intervals, and the second conductive type heavily doped diffusion region (206) is formed by diffusing the second conductive type polysilicon heavily doped trench regions (213);
a plurality of second conductive type polysilicon trench regions (212) are arranged at the top layer of the first conductive type drift region (202) at intervals and between the second conductive type body region (203) and the second conductive type heavily doped diffusion region (206);
the cathode electrode (209) is located on the second-conductivity-type heavily doped region (204) and a first portion of the first-conductivity-type heavily doped region (205); the planar gate structure is located on a second portion of the heavily doped region of first conductivity type (205), the body region of second conductivity type (203) and a portion of the drift region of first conductivity type (202); the anode electrode (211) is positioned on a plurality of second conductive type polycrystalline silicon heavily doped groove regions (213);
the isolation dielectric layer (208) is located on the first conductivity type drift region (202) between the cathode electrode (209), the planar gate structure and the anode electrode (211).
2. The LIGBT device with multiple trenches of claim 1, wherein said planar gate structure comprises said gate oxide layer (207) and a polysilicon gate electrode (210) thereon.
3. The LIGBT device with multiple trenches of claim 1, wherein the isolation dielectric layer (208) is silicon dioxide.
4. The LIGBT device with multiple trenches as claimed in any one of claims 1 to 3, wherein the lateral width, the longitudinal length, the pitch and the number of trenches of the second conductivity type polysilicon trench region (212) are adjusted by changing photolithography during the fabrication process.
5. The LIGBT device with multiple trenches as claimed in any one of claims 1 to 3, wherein the lateral width, longitudinal length, pitch and number of trenches of the heavily doped trench region (213) of the second conductivity type are adjusted by changing photolithography during the fabrication process.
6. The LIGBT device with multiple trenches of any one of claims 1-3, wherein the first conductivity type is N-type and the second conductivity type is P-type.
7. The LIGBT device with multiple trenches of any one of claims 1-3, wherein the first conductivity type is P-type and the second conductivity type is N-type.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN112420824A (en) * | 2020-12-09 | 2021-02-26 | 东南大学 | Reverse conducting type transverse insulated gate bipolar transistor capable of eliminating negative resistance effect |
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| US6445038B1 (en) * | 1998-01-09 | 2002-09-03 | Infineon Technologies Ag | Silicon on insulator high-voltage switch |
| US6326656B1 (en) * | 1998-06-24 | 2001-12-04 | Siemens Aktiengesellschaft | Lateral high-voltage transistor |
| CN104617157A (en) * | 2015-01-23 | 2015-05-13 | 应能微电子（上海）有限公司 | Transient voltage suppressor structure with ultra-deep grooves |
| CN109065627A (en) * | 2018-08-21 | 2018-12-21 | 电子科技大学 | A kind of LDMOS device with polysilicon island |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112420824A (en) * | 2020-12-09 | 2021-02-26 | 东南大学 | Reverse conducting type transverse insulated gate bipolar transistor capable of eliminating negative resistance effect |
| CN112420824B (en) * | 2020-12-09 | 2022-08-19 | 东南大学 | Reverse conducting type transverse insulated gate bipolar transistor capable of eliminating negative resistance effect |
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