CN111638887A - Program curing method for FPGA chip - Google Patents
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- CN111638887A CN111638887A CN202010465374.6A CN202010465374A CN111638887A CN 111638887 A CN111638887 A CN 111638887A CN 202010465374 A CN202010465374 A CN 202010465374A CN 111638887 A CN111638887 A CN 111638887A
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- 230000008023 solidification Effects 0.000 claims abstract description 7
- 238000000034 method Methods 0.000 claims description 19
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- 238000012360 testing method Methods 0.000 claims description 5
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- 238000013461 design Methods 0.000 description 2
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
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- G06F8/00—Arrangements for software engineering
- G06F8/60—Software deployment
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- G—PHYSICS
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- G06F8/00—Arrangements for software engineering
- G06F8/60—Software deployment
- G06F8/65—Updates
- G06F8/654—Updates using techniques specially adapted for alterable solid state memories, e.g. for EEPROM or flash memories
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Abstract
The invention discloses a program curing method for an FPGA chip, which comprises the following steps: s1: dividing QSPI Flash of the FPGA chip into a first area and a second area; s2: the FPGA chip is electrified, and first frame data is sent to an upper computer to request upgrading; s3: the upper computer sends preemption frame data to the FPGA chip, the first area preempts the control right of the memory and sends marking frame data to the upper computer at the same time; s4: the upper computer sends a start frame to the FPGA chip and erases data in the second area; after the update, sending response frame data to an upper computer to request for sending an upgrade program file; s5: and the upper computer sends an upgrading program file to the FPGA chip and writes the upgrading program file into a second area in the QSPI Flash, so that program solidification is completed. The invention executes the upgrading program through the JTAG port before the FPGA chip is sealed, and sets up the upgrading protocol, after the JTAG port is sealed, the FPGA chip is connected with the upper computer through the CAN port, thus finishing the program upgrading without needing a special JTAG port, and the program upgrading is faster.
Description
Technical Field
The invention relates to the technical field of communication, in particular to a program curing method for an FPGA chip.
Background
The sailing release a hardware architecture of an extensible processing platform in 2010, and can meet the requirements of high performance, low power consumption and multi-core processing capability of a complex embedded system; the core essence of the system is that a universal basic dual ARM Cortex _ A9 MPCore processor system is used as a 'main system', and high flexibility, powerful configuration function and high performance are realized by combining with low-power consumption process technologies of 28nm, 14nm and the like. The sailing company classifies the chips into Zynq-7000 series, and the series has the existing chips of Zynq-7010, Zynq-7020, Zynq-7045, Zynq-7100 and the like. The hardware architecture changes the traditional FPGA + ARM/DSP core architecture, provides a novel solution of single CPU, multiple processing cores, FPGA and ARM internal high-speed interconnection, can well complete work by using a single FPGA, and can be flexibly used in various fields.
In the prior art, Zynq-7000 series FPGA chip program curing adopts a plug-in nonvolatile memory QSPI (Quad SPI, four-wire SPI bus) Flash, a curable file suffix finally generated by a program is in a BIN format (BIN file for short), the program curing is to write an application program file into the QSPI Flash, and then the FPGA chip is started from the QSPIflash after each power-on and then executes the application program. Unlike other xlinx 7 series devices, the Zynq-7000 series does not support start-up configuration directly from the PL side, and the Zynq-7000 series start-up configuration is performed in multiple stages, requiring a minimum of two steps for the configuration process, and generally involving three stages, i.e., solid upgrade via a dedicated JTAG port:
stage 0(Stage 0): BootROM for short, controls the initialization process of the whole chip. The part of code is not modifiable, the processor core automatically executes the part of code when being powered on or started in a hot mode, external controllers such as NAND, NOR, SD and the like are initialized, and meanwhile, the processor core is also responsible for loading a starting mirror image (FSBL mirror image) of the stage1 into an OCM (256K RAM on a Zynq-7000 series chip) and then running the FSBL mirror image, wherein the source of the FSBL mirror image is determined by a starting mode selected by MIO (5: 3) pins on a board.
Stage 1(Stage 1): the first stage boot image (FSBL image), which may be controlled by the user's code. The main work completed is: according to user configuration, completing initialization of a PS (packet data service) end, including initialization of a DDR (double data rate) peripheral controller; configuring the PL using a bitstream file; the stage2 code (SSBL) is loaded into memory space (DDR) and run.
Stage 2(Stage 2): this stage can be generally the PS-side design code of the user, or the code of the Second Stage (SSBL), which can be completely controlled by the user. In the design adopting the Linux operating system, SSBL (u-boot.
However, in many applications using the sailing Zynq-7000 series FPGA chip, in some special cases, the FPGA chip needs to be sealed for testing or other purposes, and a special JTAG interface cannot be led out for preventing electromagnetic interference, so that subsequent program solidification or upgrading is affected.
Disclosure of Invention
Aiming at the problem that a program CAN not be solidified when an FPGA chip has no special JTAG interface in the prior art, the invention provides a program solidifying method for the FPGA chip, which realizes the program solidification of the FPG chip through a CAN interface by a data communication interface CAN interface and formulating a relevant protocol so as to upgrade software.
In order to achieve the purpose, the invention provides the following technical scheme:
a program curing method for an FPGA chip specifically comprises the following steps:
s1: dividing a plug-in nonvolatile memory QSPI Flash on an FPGA chip into a first area and a second area; the first area is used for storing BIN files for executing upgrading programs, and the second area is used for storing application programs;
s2: the FPGA chip is powered on, first frame data are sent to the upper computer through the communication interface, and the upper computer judges whether the FPGA chip needs to be upgraded or not according to the received first frame data; if the FPGA chip needs to be upgraded, jumping to S3;
s3: the upper computer sends preemption frame data to the FPGA chip, the first area receives the preemption frame data, then preempts the control right of the memory and runs the BIN file, and simultaneously sends marking frame data to the upper computer;
s4: the upper computer sends a start frame to the FPGA chip, initializes QSPI Flash, and then erases an application program in the second area; after the completion, the FPGA chip sends response frame data to the upper computer and requests the upper computer to send an upgrading program file;
s5: after receiving the response frame data, the upper computer sends an upgrading program file to the FPGA chip through the communication bus;
s6: and the FPGA chip writes the received upgrade program file into a second area in the QSPIFlash so as to finish program solidification.
Preferably, in S2, after the FPGA chip is powered on, the first frame data is sent to the upper computer within time t 1; and if the upper computer does not receive the first frame data after the time t1, the FPGA chip runs the application program of the second area.
Preferably, in S5, the upper computer sends the upgrade program file by frame, and counts frames.
Preferably, the method further comprises step S7:
s7: after the writing is finished, carrying out a read-back test, and comparing whether the written data and the read data are consistent;
A. if the written data and the read data are inconsistent, the FPGA chip sends an error frame to the upper computer, writing of QSPIFlash is stopped, and the upper computer stops sending the upgrading program file;
B. if the written data and the read data are consistent, continuously writing next frame data until a check frame sent by an upper computer is received, wherein the check frame comprises check sum information;
C. comparing the checksum information sent by the upper computer with the checksum obtained by the FPGA chip, if the checksum information is different from the checksum obtained by the FPGA chip, sending an error frame by the FPGA chip, and ending the program curing; if the two are the same, the FPGA sends an end frame mark to be upgraded successfully, and the program is cured.
Preferably, the error frame includes an error in an erasing process of the QSPI Flash and an error in a writing process of the QSPI Flash.
Preferably, after the upper computer receives the error frame, the power is cut off and the FPGA chip is restarted, and the steps S3-S7 are repeated until the upper computer receives the end frame sent by the FPGA chip.
In summary, due to the adoption of the technical scheme, compared with the prior art, the invention at least has the following beneficial effects:
according to the invention, before the FPGA chip is sealed, the upgraded Golden Image is cured and executed through the JTAG port, an upgrade protocol is formulated, after the JTAG port is sealed, the FPGA chip is connected with an upper computer through the CAN port, the program upgrade CAN be completed, and a special JTAG port is not needed any more, so that the program upgrade is quicker.
Description of the drawings:
fig. 1 is a schematic diagram of a program curing system for FPGA chips according to an exemplary embodiment of the present invention.
Fig. 2 is a flowchart illustrating a program curing method for an FPGA chip according to an exemplary embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to examples and embodiments. It should be understood that the scope of the above-described subject matter is not limited to the following examples, and any techniques implemented based on the disclosure of the present invention are within the scope of the present invention.
In the description of the present invention, it is to be understood that the terms "longitudinal", "lateral", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like, indicate orientations or positional relationships based on those shown in the drawings, and are used merely for convenience of description and for simplicity of description, and do not indicate or imply that the referenced devices or elements must have a particular orientation, be constructed in a particular orientation, and be operated, and thus, are not to be construed as limiting the present invention.
As shown in fig. 1, the present invention provides a program solidifying system for an FPGA chip, which includes an FPGA chip and an upper computer, wherein the FPGA chip is connected to the upper computer through a CAN bus. The FPGA chip is provided with a plug-in nonvolatile memory QSPI (Quad SPI, four-wire SPI bus) Flash, a JTAG port and a CAN port. When the FPGA chip is closed, the JTAG port is closed.
In this embodiment, the upper computer stores various upgrade program files (i.e., application programs) for upgrading the FPGA chip.
In this embodiment, the QSPI Flash includes two areas, a first area is used to store a BIN file for executing an upgrade program, and a second area is used to store an application program.
As shown in fig. 2, the present invention further provides a program curing method for an FPGA chip, which specifically includes the following steps:
s1: dividing a plug-in nonvolatile memory QSPIFlash on an FPGA chip into a first area and a second area; the first area is used for storing BIN files for executing the upgrading programs, and the second area is used for storing the application programs.
In this embodiment, a plug-in nonvolatile memory QSPI (Quad SPI, four-wire SPI bus) Flash on an FPGA chip is first divided into a first area and a second area. The first area stores Golden Image (Golden mirror Image), namely BIN file used for communicating with CAN interface and executing upgrading program; the second area stores Updatable Image (i.e., an application program executed in a normal operating state).
S2: the FPGA chip is powered on, a first area sends first frame data to an upper computer through a communication interface (such as a CAN port), the first frame data are communication data (a protocol CAN be self-defined) appointed by the FPGA chip and the upper computer, and the upper computer judges whether the FPGA chip needs to be upgraded or not according to the received first frame data; and if the FPGA chip needs to be upgraded, jumping to S3. And if the FPGA chip does not need to be upgraded, ending the process.
In this embodiment, after the FPGA chip is powered on, the first frame data is sent to the upper computer within a certain time t1 (for example, 3s, which can be arbitrarily set as required); if the specified time t1 is exceeded, the FPGA chip still does not send the first frame data to the upper computer, and the FPGA chip directly runs the application program in the second area, that is, the program is not upgraded.
S3: the upper computer sends preemption frame data to the FPGA chip, and the first area preempts the control right of the memory after receiving the preemption frame data and runs the BIN file to execute program upgrading; and meanwhile, sending the mark frame data to the upper computer to indicate that the BIN file runs successfully, and continuing to execute the upgrading program operation and jumping to S4.
S4: after receiving the mark frame data, the upper computer sends a start frame to the FPGA chip, initializes QSPI Flash, and then immediately erases application program data in the second area; and after the erasing is finished, the FPGA chip sends response frame data to the upper computer so that the upper computer sends an upgrading program file.
S5: and after receiving the response frame data, the upper computer sends an upgrading program file according to frames through the CAN bus, and performs frame counting and checksum.
S6: the FPGA chip writes the received upgrading program file into a second area in the QSPI Flash so as to complete program solidification; after the writing of each frame is finished, a read-back test is carried out, and whether the written data is consistent with the read data or not is compared.
And if the upper computer receives the error frame fed back by the FPGA chip midway, the upper computer stops sending the upgrading program file.
A. And if the written data and the read data are inconsistent, the FPGA chip immediately sends an error frame to the upper computer and stops writing the QSPI Flash, and the upper computer stops sending the upgrade program file.
B. And if the written data and the read data are consistent, performing checksum and continuously writing the next frame of upgrading program file and performing read-back test until a check frame sent by the upper computer is received.
C. Comparing the check sum sent by the upper computer with the check sum calculated by the FPGA chip, if the check sums are different, sending an error frame by the FPGA chip, and finishing the solidification of the upgrading program; if the checksums are the same, the FPGA sends an end frame, the mark is upgraded successfully, and the FPGA chip is restarted after power failure.
In this embodiment, if the upper computer receives the error frame, it indicates that an error occurs in the upgrading process, and there are the following situations: errors occur in the QSPI Flash erasing process; the QSPI Flash write process is in error (including checksum error).
The invention has error recovery capability, and is not limited to upgrade times on software, but only limited to the erase times of the selected QSPI Flash chip. When the errors occur in the upgrading process, the FPGA chip is only required to be powered off and restarted, and then the method flow is executed (i.e. S3 is jumped to) until the upper computer receives an end frame with a successful mark.
It will be understood by those of ordinary skill in the art that the foregoing embodiments are specific examples for carrying out the invention, and that various changes in form and details may be made therein without departing from the spirit and scope of the invention in practice.
Claims (6)
1. A program curing method for an FPGA chip is characterized by comprising the following steps:
s1: dividing a plug-in nonvolatile memory QSPI Flash on an FPGA chip into a first area and a second area; the first area is used for storing BIN files for executing upgrading programs, and the second area is used for storing application programs;
s2: the FPGA chip is powered on, first frame data are sent to the upper computer through the communication interface, and the upper computer judges whether the FPGA chip needs to be upgraded or not according to the received first frame data; if the FPGA chip needs to be upgraded, jumping to S3;
s3: the upper computer sends preemption frame data to the FPGA chip, the first area receives the preemption frame data, then preempts the control right of the memory and runs the BIN file, and simultaneously sends marking frame data to the upper computer;
s4: the upper computer sends a start frame to the FPGA chip, initializes QSPI Flash, and then erases an application program in the second area; after the completion, the FPGA chip sends response frame data to the upper computer and requests the upper computer to send an upgrading program file;
s5: after receiving the response frame data, the upper computer sends an upgrading program file to the FPGA chip through the communication bus;
s6: and the FPGA chip writes the received upgrade program file into a second area in the QSPI Flash, so that the program solidification is completed.
2. The program solidifying method for FPGA chip as claimed in claim 1, wherein in S2, after the FPGA chip is powered on, the first frame data is sent to the upper computer within time t 1; and if the upper computer does not receive the first frame data after the time t1, the FPGA chip runs the application program of the second area.
3. The program curing method for the FPGA chip as recited in claim 1, wherein in S5, the upper computer sends the upgrade program file by frame and performs frame counting.
4. The program curing method for the FPGA chip as recited in claim 1, further comprising the step S7:
s7: after the writing is finished, carrying out a read-back test, and comparing whether the written data and the read data are consistent;
A. if the written data and the read data are inconsistent, the FPGA chip sends an error frame to the upper computer, writing of QSPIFlash is stopped, and the upper computer stops sending the upgrading program file;
B. if the written data and the read data are consistent, continuously writing next frame data until a check frame sent by an upper computer is received, wherein the check frame comprises check sum information;
C. comparing the checksum information sent by the upper computer with the checksum obtained by the FPGA chip, if the checksum information is different from the checksum obtained by the FPGA chip, sending an error frame by the FPGA chip, and ending the program curing; if the two are the same, the FPGA sends an end frame mark to be upgraded successfully, and the program is cured.
5. The program hardening method for the FPGA chip according to claim 4, wherein the error frame includes an erasure process error of the QSPI Flash and a write process error of the QSPI Flash.
6. The program solidifying method for the FPGA chip as recited in claim 4, wherein the FPGA chip is restarted after the upper computer receives the error frame, and the steps S3-S7 are repeated until the upper computer receives an end frame sent by the FPGA chip.
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Cited By (4)
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| CN112269585A (en) * | 2020-11-04 | 2021-01-26 | 配天机器人技术有限公司 | Joint driver firmware online updating method and device and joint driver |
| CN115934139A (en) * | 2023-03-13 | 2023-04-07 | 东方电子股份有限公司 | FPGA (field programmable Gate array) online upgrading method and system |
| CN116301936A (en) * | 2023-03-03 | 2023-06-23 | 西安瑞日电子发展有限公司 | FPGA configuration file acceleration curing system and method |
| WO2024103635A1 (en) * | 2022-11-15 | 2024-05-23 | 中国第一汽车股份有限公司 | Cpld program upgrading method and apparatus for motor controller, motor controller and vehicle |
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Application publication date: 20200908 |