CN111629533A - Warpage improving method of PCB - Google Patents
Warpage improving method of PCB Download PDFInfo
- Publication number
- CN111629533A CN111629533A CN202010616336.6A CN202010616336A CN111629533A CN 111629533 A CN111629533 A CN 111629533A CN 202010616336 A CN202010616336 A CN 202010616336A CN 111629533 A CN111629533 A CN 111629533A
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- pcb
- copper
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/303—Surface mounted components, e.g. affixing before soldering, aligning means, spacing means
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0271—Arrangements for reducing stress or warp in rigid printed circuit boards, e.g. caused by loads, vibrations or differences in thermal expansion
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3431—Leadless components
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09009—Substrate related
- H05K2201/09136—Means for correcting warpage
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Manufacturing Of Printed Wiring (AREA)
Abstract
The invention relates to the technical field of PCBs (printed circuit boards), and discloses a method for improving warpage of a PCB, which comprises the following steps: manufacturing a PCB, so that the PCB is divided into two equal-thickness parts with different copper densities in a designated area along the thickness direction of the PCB, and the direction of the part with the higher copper density pointing to the part with the lower copper density is the same as the warping direction of the carrier plate; or, the middle copper density of the designated area of the PCB is larger than a preset value; the designated area is a vertical projection area of a preset welding area on the surface of the PCB; and (3) mounting the chip on a preset welding area and then welding. According to the invention, the copper density of the upper part and the lower part of the PCB along the thickness direction of the board is asymmetrically designed, so that the PCB can present the same warping direction as the chip after welding and cooling, or the overall shrinkage rate of the PCB is reduced by increasing the middle copper density of the PCB, the warping difference between the PCB and the chip can be reduced, the tightness of the PCB and the chip can be effectively improved, and the product yield can be ensured.
Description
Technical Field
The invention relates to the technical field of Printed Circuit Boards (PCBs), in particular to a method for improving warping of a PCB.
Background
As chip processing capacity of information-enabled electronic products increases, the size of the integrated circuit Die (Die) increases rapidly, and the warpage of the entire chip formed by packaging also increases. As the size of the chip increases, the CTE (coefficient of thermal expansion) of the PCB also increases, eventually resulting in increased deformation and complicated orientation and morphology of the PCB and the soldered chip.
Referring to the PCB20 and the chip 10 shown in fig. 1, the chip 10 is usually attached to the surface of the PCB20, and then the two are connected by high temperature reflow soldering. After the soldering is cooled, the warpage directions of the PCB20 and the chip 10 are opposite, or the warpage degrees differ greatly although the warpage directions are the same, which may cause the contact between the chip 10 and the BGA (Ball Grid Array) pad on the PCB20 to be reduced, which may have a great adverse effect on the yield of the assembly, and may even cause the solder joint to break and the product to be discarded.
Disclosure of Invention
The invention aims to provide a method for improving the warpage of a PCB (printed circuit board), which aims to solve the problem that the bonding degree of a chip and the PCB is easy to reduce due to the warpage problem after a high-temperature reflow soldering process in the prior art.
In order to achieve the purpose, the invention adopts the following technical scheme:
a warpage improving method of a PCB, the chip comprising a die and a carrier board for carrying the die, comprising:
manufacturing a PCB, so that the PCB is divided into two parts with equal thickness and different copper densities in a designated area along the thickness direction of the PCB, and the direction of the part with the higher copper density pointing to the part with the lower copper density is the same as the warping direction of the carrier plate relative to the PCB; or, the middle copper density of the designated area of the PCB is larger than a preset value;
the designated area is a vertical projection area of a preset welding area on the surface of the PCB;
and attaching the chip to a preset welding area on the surface of the PCB, and then welding.
Optionally, the manufacturing the PCB such that the PCB is divided into two equal-thickness portions having different copper densities in a designated area along a thickness direction of the PCB, and a direction in which a portion having a higher copper density points to a portion having a lower copper density is the same as a warping direction of the carrier board relative to the PCB includes:
performing local thick copper plating operation on at least one core plate which forms the part with the larger copper density in a specified area of a single plate surface or two opposite plate surfaces of the core plate;
and applying the core board, and laminating the boards to manufacture the PCB.
Optionally, if the local thick copper plating operation is performed on the designated area of the single board surface of the core board, the increased thickness of copper is less than or equal to the thickness of the adjacent prepreg-the thickness of the glass fiber cloth of the adjacent prepreg.
Optionally, if the local thick copper plating operation is performed on the designated areas of the two opposite plate surfaces of the core plate, the thickness of the copper thickness added on each plate surface is less than or equal to (the thickness of the adjacent prepreg-the thickness of the glass fiber cloth of the adjacent prepreg)/2.
Optionally, the manufacturing the PCB such that the PCB is divided into two equal-thickness portions having different copper densities in a designated area along a thickness direction of the PCB, and a direction in which a portion having a higher copper density points to a portion having a lower copper density is the same as a warping direction of the carrier board relative to the PCB includes:
performing local copper reduction operation on at least one core plate forming the part with low copper density in a specified area of a single plate surface or two opposite plate surfaces of the core plate;
and applying the core board, and laminating the boards to manufacture the PCB.
Optionally, the manufacturing the PCB such that the PCB is divided into two equal-thickness portions having different copper densities in a designated area along a thickness direction of the PCB, and a direction in which a portion having a higher copper density points to a portion having a lower copper density is the same as a warping direction of the carrier board relative to the PCB includes:
sequentially stacking the core boards and the prepregs which form the PCB, and additionally stacking a preset number of copper foils at the inner layer position of the part with higher copper density;
and pressing at high temperature to manufacture the PCB.
Optionally, the manufacturing the PCB such that the middle copper density of the designated area of the PCB is greater than a preset value includes:
aiming at a core board which forms the PCB and is positioned at the innermost layer, local thick copper plating operation is simultaneously carried out on specified areas of two opposite board surfaces of the core board;
and applying the core board, and laminating the boards to manufacture the PCB.
Optionally, the manufacturing the PCB such that the middle copper density of the designated area of the PCB is greater than a preset value includes:
sequentially stacking the core boards and the prepregs which form the PCB, and stacking a middle board at the most middle position; copper layers are reserved in the designated areas of the two opposite plate surfaces of the middle plate, and the copper layers outside the designated areas of the two opposite plate surfaces are etched and removed;
and pressing at high temperature to manufacture the PCB.
Optionally, the manufacturing the PCB such that the middle copper density of the designated area of the PCB is greater than a preset value includes:
sequentially stacking the core boards and the prepregs which form the PCB, and stacking a preset number of copper foils at the middle position;
and pressing at high temperature to manufacture the PCB.
Optionally, the welding conditions are as follows: peak temperature at 260 ℃, 20-30 seconds above 255 ℃, and 150 seconds above 217 ℃.
Compared with the prior art, the invention has the beneficial effects that:
according to the embodiment of the invention, the copper density of the upper and lower equal-thickness parts of the PCB along the plate thickness direction is asymmetrically designed, so that the PCB can present the same warping direction as the chip after welding and cooling, or the overall shrinkage rate of the PCB is reduced by increasing the middle copper density of the PCB, the warping difference between the PCB and the chip can be reduced, the tightness of the PCB and the chip can be effectively improved, and the product yield can be ensured.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
Fig. 1 is a schematic structural diagram of a chip and a PCB before soldering.
Fig. 2 is a flowchart of a method for improving warpage of a PCB according to an embodiment of the present invention.
Fig. 3 is a schematic structural diagram of a PCB after local copper thickness is achieved through addition according to an embodiment of the present invention.
Fig. 4 is a schematic structural diagram of a PCB after local copper thickness is achieved by subtraction according to an embodiment of the present invention.
Fig. 5 is a flowchart of another method for improving warpage of a PCB according to an embodiment of the present invention.
Fig. 6 is a schematic diagram of a PCB structure with increased intermediate copper density according to an embodiment of the present invention.
Description of the figure numbers: chip 10, PCB20, bare chip 11, carrier board 12, intermediate board 21.
Detailed Description
In order to make the objects, features and advantages of the present invention more obvious and understandable, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the embodiments described below are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
In order to solve the problem that after the chip 10 and the PCB20 are welded and cooled, the PCB20 and the carrier plate 12 of the chip 10 are easy to generate different warping directions, so that the tightness of the PCB20 and the carrier plate 12 is poor, and even a welding point is broken, the invention provides a PCB warping improvement scheme, wherein the PCB20 can present the same warping direction as the chip 10 after being cooled by carrying out asymmetric design on the copper density of the upper part and the lower part of the PCB20 along the plate thickness direction; or the intermediate copper density of the PCB20 is increased, so that the overall shrinkage rate of the PCB20 is reduced, the warpage difference between the PCB20 and the chip 10 is reduced, and the tightness between the two is improved.
Example one
Referring to fig. 2, the method for improving warpage of the PCB20 provided in the present embodiment specifically includes the steps of:
In this embodiment, the warping direction of the carrier 12 relative to the PCB20 refers to a moving direction of the edge portion of the carrier 12 relative to the center portion when the carrier 12 is deformed in a relative position state with the PCB20 during soldering. Taking fig. 3 as an example, since the peripheral portion of the carrier plate 12 moves upward relative to the central portion when the deformation occurs (as shown by the arrow in fig. 3), the warpage direction of the carrier plate 12 is referred to as an upward direction in this embodiment, and the carrier plate 12 after the deformation has a concave structure as a whole; on the contrary, if the peripheral portion of the carrier 12 moves downward relative to the central portion when the deformation occurs, the warpage direction of the carrier 12 is referred to as a downward direction in this embodiment, and the carrier 12 takes on a convex structure after the deformation.
Wherein the designated area is a vertical projection area of a preset soldering area on the surface of the PCB 20.
Typically, a BGA pad is disposed on the surface of the PCB20 in a predetermined bonding area for bonding with the bonding surface of the carrier 12 of the chip 10.
Specifically, the method further comprises the following steps: the method comprises the steps of firstly carrying out silk-screen printing or dispensing on solder paste on a BGA bonding pad on the outer layer of a PCB20, then adopting a chip mounter to mount a carrier plate 12 supporting an integrated circuit bare chip 11 on the BGA bonding pad, and then passing through a reflow oven to carry out soldering under reflow soldering conditions (peak temperature at 260 ℃, 20-30 seconds above 255 ℃, and 120-150 seconds above 217 ℃).
Since the shrinkage rate decreases as the copper density increases and the shrinkage rates of the object are different on opposite sides thereof, a warp direction from the side having a small shrinkage rate toward the side having a large shrinkage rate occurs. Therefore, the PCB20 is divided into two equal-thickness portions along the board thickness direction at a theoretical angle, and the copper density of the two portions is differentially designed according to the warping direction of the chip 10 relative to the PCB20, so that the PCB20 can have the same warping direction as the chip 10 after soldering cooling. Because the warping directions of the two are the same, the welding point between the BGA pad of the PCB20 and the chip 10 is not broken by stress, thereby ensuring that the two are always kept in high tightness.
Illustratively, the specific implementation method of step 101 includes the following three types:
first, an additive solution concept for local copper thickness includes: for at least one core board with a large copper density, performing local thick copper plating operation on a single board surface or specified areas of two opposite board surfaces of the core board, as shown in fig. 3; then, the core board stack is pressed to form the PCB 20.
Taking fig. 3 as an example, there is an upward warping direction of the carrier 12 of the chip 10, and the bottom surface of the PCB20 away from the chip 10 is partially increased in copper thickness, so that the copper density of the bottom portion of the PCB20 is higher than that of the top portion, and after soldering and cooling, the PCB20 will generate an upward warping direction, which is consistent with the warping direction of the carrier 12.
Further, the operation of locally plating thick copper may include: pasting a film on the core board, exposing and developing to remove the dry film in the designated area (namely the vertical projection area of the preset welding area) on one or two surfaces, and reserving the dry films at other positions; copper plating is carried out on the core plate, so that the copper thickness of the dry film windowing area is increased; and stripping to form the local thick copper core plate.
The core plates for local thick copper plating operation are only required to belong to the part with higher copper density, the number of the core plates is not limited, and the number of the core plates can be controlled according to the warping degree required in practice.
Preferably, if local thick copper plating operation is carried out on the specified area of the single board surface of the core board, the thickness of the added copper is less than or equal to the thickness of the adjacent prepreg-the thickness of the glass fiber cloth of the adjacent prepreg; if the local thick copper plating operation is carried out on the specified areas of the two opposite plate surfaces of the core plate, the thickness of the copper thickness increased by each plate surface is less than or equal to (the thickness of the adjacent prepreg-the thickness of the glass fiber cloth of the adjacent prepreg)/2. Wherein adjacent prepreg refers to prepreg adjacent to the core board.
Second, a solution for local copper thickness subtraction comprises: for at least one core board forming a part with a small copper density, performing a local copper reduction operation on a single board surface or a designated area of two opposite board surfaces of the core board, as shown in fig. 4; the PCB20 is manufactured by laminating the core boards.
The third, directly increase the solution thinking of copper foil, include: sequentially stacking the core boards and the prepregs which form the PCB20, and additionally stacking a preset number of copper foils at the inner layer position of the part with higher copper density; and (4) pressing at high temperature to manufacture the PCB 20.
In fact, the first and second solutions are: in the PCB20, the two portions having the same thickness are theoretically divided in the plate thickness direction, and the copper density of one portion is increased or decreased on the premise that the copper density of the other portion is not changed, so that the copper density of one portion is smaller or larger than that of the other portion. The third solution is to add copper foil directly to the part where the copper density needs to be increased. In practical applications, the three schemes can be applied independently or in various combination modes, and the invention is not limited.
Example two
Referring to fig. 5, the method for improving warpage of the PCB20 provided in the present embodiment includes the following steps:
The designated area is a vertical projection area of a preset soldering area on the surface of the PCB 20.
The intermediate copper density refers to the copper density of the intermediate layer of the PCB 20. The intermediate layer may be one or a plurality of successive layers in the order of lamination at the most intermediate lamination position.
Specifically, the method further comprises the following steps: the method comprises the steps of firstly carrying out silk-screen printing or dispensing on solder paste on a BGA bonding pad on the outer layer of a PCB20, then adopting a chip mounter to mount a carrier plate 12 supporting an integrated circuit bare chip 11 on the BGA bonding pad, and then passing through a reflow oven to carry out soldering under reflow soldering conditions (peak temperature at 260 ℃, 20-30 seconds above 255 ℃, and 120-150 seconds above 217 ℃).
Illustratively, the specific implementation method of step 201 includes the following two methods:
first, a solution idea of adding a middle plate 21 having a special structure at a middle position includes: the core boards and prepregs constituting the PCB20 are sequentially stacked, and the intermediate board 21 is stacked at the most intermediate position, as shown in fig. 6; copper layers are reserved in the designated areas of the two opposite plate surfaces of the middle plate 21, and the copper layers outside the designated areas of the two opposite plate surfaces are etched and removed; and (4) pressing at high temperature to manufacture the PCB 20.
The manufacturing process of the intermediate plate 21 comprises the following steps: pasting a film on the core plate, exposing and developing to reserve dry films in designated areas (namely vertical projection areas of preset welding areas) on two sides of the core plate and remove the dry films at other positions; etching to remove the exposed copper layer at other positions; the intermediate plate 21 is removed from the film to form a copper layer only in a predetermined region on both surfaces.
The second solution of stacking copper foils in the middle includes: sequentially stacking the core boards and the prepregs which form the PCB20, and stacking a preset number of copper foils at the middle position; and (4) pressing at high temperature to manufacture the PCB 20.
In the embodiment, the copper thickness is increased at the middle position of the PCB20 in the plate thickness direction, so that the middle copper density of the PCB20 is increased, and the warping degree of the whole PCB20 is reduced. Therefore, no matter whether the warping directions of the PCB20 and the chip 10 are the same or not, the warping degree of the whole PCB20 can be reduced to a certain degree in the embodiment, so that the warping difference between the PCB20 and the chip 10 is reduced, the tightness between the PCB20 and the chip 10 is increased, the risk of breakage of the welding points of the BGA pads on the chip 10 and the PCB20 is reduced, and the product yield is improved.
The above-mentioned embodiments are only used for illustrating the technical solutions of the present invention, and not for limiting the same; although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions of the embodiments of the present invention.
Claims (10)
1. A warpage improving method of a PCB, wherein the chip comprises a bare chip and a carrier board for carrying the bare chip, the warpage improving method is characterized by comprising the following steps:
manufacturing a PCB, so that the PCB is divided into two parts with equal thickness and different copper densities in a designated area along the thickness direction of the PCB, and the direction of the part with the higher copper density pointing to the part with the lower copper density is the same as the warping direction of the carrier plate relative to the PCB; or, the middle copper density of the designated area of the PCB is larger than a preset value;
the designated area is a vertical projection area of a preset welding area on the surface of the PCB;
and attaching the chip to a preset welding area on the surface of the PCB, and then welding.
2. The method of claim 1, wherein the fabricating the PCB such that the PCB is divided into two equal-thickness portions having different copper densities in a designated area along a board thickness direction, and a direction in which a portion having a greater copper density is directed to a portion having a lesser copper density is the same as a warpage direction of the carrier board with respect to the PCB comprises:
performing local thick copper plating operation on at least one core plate which forms the part with the larger copper density in a specified area of a single plate surface or two opposite plate surfaces of the core plate;
and applying the core board, and laminating the boards to manufacture the PCB.
3. The method of claim 2, wherein if the copper plating operation is performed locally on a designated area of a single board surface of the core board, the copper thickness is increased to be not more than the thickness of an adjacent prepreg-the thickness of a glass cloth of the adjacent prepreg.
4. The method of claim 2, wherein if the copper plating operation is performed locally on the designated areas of the opposite two board surfaces of the core board, the thickness of the copper thickness added to each board surface is less than or equal to (thickness of adjacent prepreg-thickness of glass fiber cloth of adjacent prepreg)/2.
5. The method of claim 1, wherein the fabricating the PCB such that the PCB is divided into two equal-thickness portions having different copper densities in a designated area along a board thickness direction, and a direction in which a portion having a greater copper density is directed to a portion having a lesser copper density is the same as a warpage direction of the carrier board with respect to the PCB comprises:
performing local copper reduction operation on at least one core plate forming the part with low copper density in a specified area of a single plate surface or two opposite plate surfaces of the core plate;
and applying the core board, and laminating the boards to manufacture the PCB.
6. The method of claim 1, wherein the fabricating the PCB such that the PCB is divided into two equal-thickness portions having different copper densities in a designated area along a board thickness direction, and a direction in which a portion having a greater copper density is directed to a portion having a lesser copper density is the same as a warpage direction of the carrier board with respect to the PCB comprises:
sequentially stacking the core boards and the prepregs which form the PCB, and additionally stacking a preset number of copper foils at the inner layer position of the part with higher copper density;
and pressing at high temperature to manufacture the PCB.
7. The PCB warpage improving method of claim 1, wherein the fabricating the PCB such that the copper density in the middle of the designated area of the PCB is greater than a preset value comprises:
aiming at a core board which forms the PCB and is positioned at the innermost layer, local thick copper plating operation is simultaneously carried out on specified areas of two opposite board surfaces of the core board;
and applying the core board, and laminating the boards to manufacture the PCB.
8. The PCB warpage improving method of claim 1, wherein the fabricating the PCB such that the copper density in the middle of the designated area of the PCB is greater than a preset value comprises:
sequentially stacking the core boards and the prepregs which form the PCB, and stacking a middle board at the most middle position; copper layers are reserved in the designated areas of the two opposite plate surfaces of the middle plate, and the copper layers outside the designated areas of the two opposite plate surfaces are etched and removed;
and pressing at high temperature to manufacture the PCB.
9. The PCB warpage improving method of claim 1, wherein the fabricating the PCB such that the copper density in the middle of the designated area of the PCB is greater than a preset value comprises:
sequentially stacking the core boards and the prepregs which form the PCB, and stacking a preset number of copper foils at the middle position;
and pressing at high temperature to manufacture the PCB.
10. The warpage-improving method of PCB according to claim 1, wherein the soldering conditions are: peak temperature at 260 ℃, 20-30 seconds above 255 ℃, and 150 seconds above 217 ℃.
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Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN114286513A (en) * | 2021-11-30 | 2022-04-05 | 通元科技(惠州)有限公司 | Asymmetric prestress relieving type LED backboard and manufacturing method thereof |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0982844A (en) * | 1995-09-20 | 1997-03-28 | Mitsubishi Electric Corp | Semiconductor module board and manufacture thereof |
US20120320509A1 (en) * | 2010-03-04 | 2012-12-20 | Tovis Co., Ltd. | Curved-surface display panel fabrication method, curved-surface display panel using same, and multi-image display device using same |
JP2018006377A (en) * | 2016-06-27 | 2018-01-11 | 京セラ株式会社 | Composite substrate, electronic device, and electronic module |
CN209545978U (en) * | 2018-09-18 | 2019-10-25 | 深圳市信维通信股份有限公司 | A kind of flexible circuitry plate structure |
-
2020
- 2020-06-30 CN CN202010616336.6A patent/CN111629533B/en active Active
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0982844A (en) * | 1995-09-20 | 1997-03-28 | Mitsubishi Electric Corp | Semiconductor module board and manufacture thereof |
US20120320509A1 (en) * | 2010-03-04 | 2012-12-20 | Tovis Co., Ltd. | Curved-surface display panel fabrication method, curved-surface display panel using same, and multi-image display device using same |
JP2018006377A (en) * | 2016-06-27 | 2018-01-11 | 京セラ株式会社 | Composite substrate, electronic device, and electronic module |
CN209545978U (en) * | 2018-09-18 | 2019-10-25 | 深圳市信维通信股份有限公司 | A kind of flexible circuitry plate structure |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN114286513A (en) * | 2021-11-30 | 2022-04-05 | 通元科技(惠州)有限公司 | Asymmetric prestress relieving type LED backboard and manufacturing method thereof |
CN114286513B (en) * | 2021-11-30 | 2024-02-06 | 通元科技(惠州)有限公司 | Asymmetric prestress eliminating type LED backboard and manufacturing method thereof |
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