CN111627987A - Fin channel structure SiC field effect transistor device - Google Patents

Fin channel structure SiC field effect transistor device Download PDF

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Publication number
CN111627987A
CN111627987A CN202010472711.4A CN202010472711A CN111627987A CN 111627987 A CN111627987 A CN 111627987A CN 202010472711 A CN202010472711 A CN 202010472711A CN 111627987 A CN111627987 A CN 111627987A
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Prior art keywords
fin
region
channel
field effect
effect transistor
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CN202010472711.4A
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Inventor
倪炜江
徐妙玲
李明山
李百泉
李天运
孙安信
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Beijing Century Goldray Semiconductor Co ltd
Dongguan South Semiconductor Technology Co ltd
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Beijing Century Goldray Semiconductor Co ltd
Dongguan South Semiconductor Technology Co ltd
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Priority to CN202010472711.4A priority Critical patent/CN111627987A/en
Publication of CN111627987A publication Critical patent/CN111627987A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7827—Vertical transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H01L29/1037—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure and non-planar channel
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

The invention provides a Fin channel structure SiC field effect transistor device which sequentially comprises an n + SiC substrate, an n-drift layer, a p well region, a p + region, an n + region, a gate medium, a grid electrode, a source electrode and a drain electrode at the bottom on the surface of the device from bottom to top, wherein the channel part of the device is provided with periodically arranged mesas to form a Fin mesa structure; in addition, MOS channels are arranged on the table top, under the table top and on two side walls of the table top. According to the invention, the Fin mesa structure is arranged, so that the channel density of the SiC field effect transistor is obviously increased, namely, the channel width of a unit chip area is obviously increased on the premise of keeping the cell size and the cell density unchanged, and the channel resistance of a device is effectively reduced. The on-resistance of the whole device can be greatly reduced.

Description

Fin channel structure SiC field effect transistor device
Technical Field
The invention relates to the field of semiconductors, in particular to a Fin channel structure SiC field effect transistor device.
Background
Through years of research in the industry, a commercial product has been introduced to the SiC MOSFET, and the SiC MOSFET starts to be widely applied to the fields of a switching power supply, a photovoltaic inverter, a UPS, a new energy automobile and the like, and has the advantages of high frequency, high efficiency and the like. However, due to the great technical difficulty of SiC gate dielectric, the gate channel mobility of the current products is generally low, about 10-30cm2the/Vs, much lower than the bulk material mobility, about 1/20 of the bulk material mobility, is much lower than the channel mobility of Si MOS. In order to obtain low on-resistance, the shorter the channel of the SiC field effect transistor (MOSFET, IGBT) is, the better, but the too short channel will cause punch-through and tunneling phenomena, so in order to further reduce the very high channel resistance in the SiC MOSFET, on the one hand, it is necessary to improve the gate growth technology, and on the other hand, it is necessary to reduce the cell size and increase the cell density, i.e. to increase the channel width per chip area. However, as the cell size decreases, the resistance of the JFET region increases, and when the cell size is small enough, the JFET resistance increases dramatically, even forming pinch-offs. There is therefore a limit to the method of cell size reduction in general.
The information disclosed in this background section is only for enhancement of understanding of the general background of the invention and should not be taken as an acknowledgement or any form of suggestion that this information forms the prior art already known to a person skilled in the art.
Disclosure of Invention
The invention aims to provide a Fin channel structure SiC field effect transistor device to solve the technical problems in the prior art.
In order to achieve the purpose, the invention adopts the following technical scheme:
the invention provides a Fin channel structure SiC field effect transistor device which sequentially comprises an n + SiC substrate, an n-drift layer, a p well region, a p + region, an n + region, a gate medium, a grid electrode, a source electrode and a drain electrode at the bottom on the surface of the device from bottom to top, wherein the channel part of the device is provided with periodically arranged mesas to form a Fin mesa structure; in addition, MOS channels are arranged on the table top, under the table top and on two side walls of the table top.
As a further technical scheme, the Fin mesa structure is only arranged in the source and channel regions of the device.
As a further technical scheme, the Fin mesa structure is arranged in the whole primitive cell of a source region, a channel region and a JFET region of a device.
As a further technical scheme, the Fin mesa structure is formed by plasma etching.
As a further technical solution, the depth of the Fin mesa structure is smaller than the depths of the n + region and the p + region.
As a further technical scheme, the doping concentration of the p-well region from top to the bottom position of the Fin channel structure is 1e15-5e17cm-3In the meantime.
As a further technical scheme, the doping concentration of the bottom of the p-well region is more than 1e18cm-3。
As a further technical solution, the depth of the p + region is greater than or equal to the depth of the n + region.
By adopting the technical scheme, the invention has the following beneficial effects:
according to the invention, the Fin mesa structure is arranged, so that the channel density of the SiC field effect transistor is obviously increased, namely, the channel width of a unit chip area is obviously increased on the premise of keeping the cell size and the cell density unchanged, and the channel resistance of a device is effectively reduced. The on-resistance of the whole device can be greatly reduced.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and other drawings can be obtained by those skilled in the art without creative efforts.
FIG. 1a is a schematic cross-sectional view of a SiC MOSFET cell of the prior art (the dashed arrows indicate the electron conduction channels after turn-on);
FIG. 1b is a schematic diagram of a three-dimensional structure of a SiC MOSFET cell in the prior art;
fig. 2 is a schematic three-dimensional structure diagram of a stripe-shaped primitive cell structure of a Fin mesa structure in source and channel regions according to an embodiment of the present disclosure;
FIG. 3 is a schematic cross-sectional structure of AA ', BB' in FIG. 2;
fig. 4 is a schematic three-dimensional structure diagram of a Fin mesa structure in a stripe-shaped cell structure of a whole cell according to an embodiment of the present disclosure;
FIG. 5 is a schematic cross-sectional structure of AA ', BB' in FIG. 4;
icon: the device comprises a 1-n + SiC substrate, a 2-n-drift layer, a 3-p well region, a 4-p + region, a 5-n + region, a 6-gate dielectric, a 7-gate, an 8-source, a 9-drain, a 10-gate-source isolation dielectric, an 11-channel region, a 12-JFET region and a 13-MOS channel.
Detailed Description
The technical solutions of the present invention will be described clearly and completely with reference to the accompanying drawings, and it should be understood that the described embodiments are some, but not all embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
In the description of the present invention, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only for convenience of description and simplicity of description, but do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, should not be construed as limiting the present invention. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
In the description of the present invention, it should be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meanings of the above terms in the present invention can be understood by those skilled in the art according to specific situations.
The following detailed description of embodiments of the invention refers to the accompanying drawings. It should be understood that the detailed description and specific examples, while indicating the present invention, are given by way of illustration and explanation only, not limitation.
As shown in fig. 1a and 1b, the conventional SiC MOSFET cell includes an n + SiC substrate 1, an n-drift layer 2, a p-well region 3, a p + region 4, an n + region 5, and a gate dielectric 6 on the surface of the device, a gate 7, a source 8, a bottom drain 9, a gate-source isolation dielectric 10, a channel region 11, and a JFET region 12; according to the method, the channel structure of the SiC MOSFET device is improved, and the channel arrangement of the Fin mesa structure is adopted, so that the SiC MOSFET device with high channel density is formed, and the channel resistance of the device is reduced. The mesa arranged regularly is etched on the surface of the SiC, MOS channels are formed on the upper part and the lower part of the mesa (namely the bottom of the groove), and simultaneously MOS channels are formed on two side walls of the mesa, so that the channel density can be increased by 1 time or even more. The mesa may be vertical or may be sloped. Meanwhile, the added channel at the side wall is on other crystal faces, and the mobility of the SiC channel is greatly related to the crystal faces, and the mobility of the channel on the other crystal faces is more than several times higher than that of the channel on the conventional Si face, so that the mobility of the channel at the added side wall is very high by properly selecting the direction of the original cell and the inclination angle of the table top.
Taking the MOSFET with stripe cell structure as an example, the other cell structures are similar. Fig. 1b shows a schematic three-dimensional structure for a generic device. The total channel width in the cells is 2L, and the total channel width of the device is the sum of the channel widths of the cells. The channel density, i.e., the gate density, is the total channel width to total area, i.e., 2/W in the cell, W being the cell width.
Example one
As shown in fig. 2 and fig. 3, the present embodiment provides a Fin channel structure SiC field effect transistor device, which includes, from bottom to top, an n + SiC substrate 1, an n-drift layer 2, a p well region 3, a p + region 4, an n + region 5, and a gate dielectric 6, a gate electrode 7, a source electrode 8, a drain electrode 9, a gate-source isolation dielectric 10 and a channel region 11 on a surface of the device, where a channel portion of the device is provided with periodically arranged mesas to form a Fin mesa structure; in addition, MOS channels 13 are provided on the mesa, under the mesa and on both sidewalls of the mesa. If the depth of the mesa is h, the width is d, and the interval is s, the channel density is (2L/W × L) × (2h + d + s)/(d + s), and if d is h, the channel density is 2 times that of the normal structure. If 2h > (d + s), the channel density is greater than 2 times. The height h of the mesa is limited by the depth of the p-well region 3.
In this embodiment, as a further technical solution, the Fin mesa structure is only disposed in the source and channel regions of the device.
In this embodiment, as a further technical solution, the Fin mesa structure is formed by plasma etching. After the p-well region 3, the p + region 4 and the n + region 5 are formed by ion implantation, ICP or RIE etching is carried out by using a medium or glue as a mask, and the depth of the Fin mesa structure is smaller than that of the n + region 5 and the p + region 4.
In this embodiment, as a further technical solution, the doping concentration of the p-well region 3 from the top (near the surface) to the bottom (or a part slightly deeper than the trench) of the Fin channel structure is 1e15-5e17cm-3And the uniformity is determined according to the threshold voltage. Therefore, after etching, the doping concentrations of the p-wells on the upper surface, the lower surface and the side wall of the mesa are relatively uniform, and the channels at all positions are kept consistent.
In this embodiment, as a further technical solution, the doping concentration of the bottom of the p-well region 3 is greater than 1e18cm-3Punch-through of the p-well in the blocking state can be prevented while forming a very low resistance avalanche current conduction region.
In this embodiment, as a further technical solution, the depth of the p + region is greater than or equal to the depth of the n + region.
The device comprises an active area, an electrode pressing block, a junction terminal and a scribing groove, wherein the active area is formed by connecting a plurality of cells in parallel, a source electrode and a grid electrode of each cell are respectively and electrically connected with the corresponding electrode pressing block in a metal mode, and the grid electrode and the source electrode are electrically isolated through an isolation dielectric layer. The junction termination of the device may be field limiting ring, JTE, or a combination of both.
Example two
As shown in fig. 4 and 5, the present embodiment is different from the first embodiment in that the Fin mesa structure is disposed in the whole cell of the source, channel and JFET regions of the device.
The structure of the present invention can be applied to various SiC field effect transistors such as MOSFET, IGBT, etc., and hereinafter, SiCMOSFET will be described as an example.
Because SiO is arranged at the interface of the gate dielectric in the SiC MOSFET2the/SiC interface state density is very high, 1-2 orders of magnitude higher than that of silicon devices, and therefore the channel mobility is very low, especially on the silicon surface for common devices, the channel mobility of the current market SiCMOSFET products is between 10-30, about 1/20 of bulk material, and therefore although the channel length is usually only submicron, the channel resistance still accounts for a large proportion of the whole device. In devices of 1200V and below, the channel resistance may be a major component because of the low drift region resistance. Therefore, reducing the channel resistance is very important in medium and low voltage SiC MOSFET devices. The Fin mesa structure is arranged, so that the channel density of the SiC field effect transistor is obviously increased, namely the channel width of the unit chip area is obviously increased on the premise of keeping the original cell size and the original cell density unchanged, and the channel resistance of the device is effectively reduced. The on-resistance of the whole device can be obtainedA large reduction.
Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; while the invention has been described in detail and with reference to the foregoing embodiments, it will be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present invention.

Claims (8)

1. A Fin channel structure SiC field effect transistor device comprises an n + SiC substrate, an n-drift layer, a p well region, a p + region, an n + region, a gate dielectric, a grid electrode, a source electrode and a drain electrode at the bottom on the surface of the device from bottom to top in sequence, and is characterized in that periodically arranged mesas are arranged on a channel part of the device to form a Fin mesa structure; in addition, MOS channels are arranged on the table top, under the table top and on two side walls of the table top.
2. A Fin channel structure SiC field effect transistor device according to claim 1, wherein the Fin mesa structures are provided only in the source and channel regions of the device.
3. The Fin channel structure SiC field effect transistor device of claim 1, wherein the Fin mesa structure is disposed within an entire cell of source, channel and JFET regions of the device.
4. The Fin channel structure SiC field effect transistor device of claim 1, wherein the Fin mesa structure is formed by plasma etching.
5. The Fin channel structure SiC field effect transistor device of claim 1, wherein a depth of the Fin mesa structure is less than a depth of the n + region and the p + region.
6. The Fin channel structure SiC field effect transistor device of claim 1, wherein the doping concentration of the p-well region from top to the bottom position of the Fin channel structure is 1e15-5e17cm-3In the meantime.
7. The Fin channel structure SiC field effect transistor device of claim 1, wherein the doping concentration at the bottom of the p-well region is greater than 1e18cm-3。
8. The Fin channel structure SiC field effect transistor device of claim 1, wherein the depth of the p + region is greater than or equal to the depth of the n + region.
CN202010472711.4A 2020-05-29 2020-05-29 Fin channel structure SiC field effect transistor device Pending CN111627987A (en)

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Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1883051A (en) * 2003-11-17 2006-12-20 Abb技术有限公司 IGBT cathode design with improved safe operating area capability
CN1977386A (en) * 2004-06-22 2007-06-06 克里公司 Silicon carbide devices and methods of fabricating the same
CN102770960A (en) * 2010-11-01 2012-11-07 住友电气工业株式会社 Semiconductor device and manufacturing method therefor
CN103681843A (en) * 2012-09-18 2014-03-26 无锡华润华晶微电子有限公司 Planar VDMOS (Vertical Double-Diffusion Metal-Oxide-Semiconductor) transistor and preparation method thereof
CN103779414A (en) * 2012-10-18 2014-05-07 富士电机株式会社 Semiconductor device and method for manufacturing the same
WO2014207793A1 (en) * 2013-06-24 2014-12-31 株式会社日立製作所 Semiconductor device, and method for manufacturing same
CN104282574A (en) * 2013-07-02 2015-01-14 通用电气公司 Semiconductor device and method for manufacturing same
US20150155355A1 (en) * 2013-12-04 2015-06-04 General Electric Company Systems and methods for semiconductor devices
WO2015177914A1 (en) * 2014-05-23 2015-11-26 株式会社日立製作所 Semiconductor device, semiconductor device manufacturing method, power conversion device, three-phase motor system, automobile, and train car

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1883051A (en) * 2003-11-17 2006-12-20 Abb技术有限公司 IGBT cathode design with improved safe operating area capability
CN1977386A (en) * 2004-06-22 2007-06-06 克里公司 Silicon carbide devices and methods of fabricating the same
CN102770960A (en) * 2010-11-01 2012-11-07 住友电气工业株式会社 Semiconductor device and manufacturing method therefor
CN103681843A (en) * 2012-09-18 2014-03-26 无锡华润华晶微电子有限公司 Planar VDMOS (Vertical Double-Diffusion Metal-Oxide-Semiconductor) transistor and preparation method thereof
CN103779414A (en) * 2012-10-18 2014-05-07 富士电机株式会社 Semiconductor device and method for manufacturing the same
WO2014207793A1 (en) * 2013-06-24 2014-12-31 株式会社日立製作所 Semiconductor device, and method for manufacturing same
CN104282574A (en) * 2013-07-02 2015-01-14 通用电气公司 Semiconductor device and method for manufacturing same
US20150155355A1 (en) * 2013-12-04 2015-06-04 General Electric Company Systems and methods for semiconductor devices
WO2015177914A1 (en) * 2014-05-23 2015-11-26 株式会社日立製作所 Semiconductor device, semiconductor device manufacturing method, power conversion device, three-phase motor system, automobile, and train car

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Application publication date: 20200904