CN111627936B - Array substrate, preparation method thereof and remote touch liquid crystal display device - Google Patents
Array substrate, preparation method thereof and remote touch liquid crystal display device Download PDFInfo
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- CN111627936B CN111627936B CN202010525361.3A CN202010525361A CN111627936B CN 111627936 B CN111627936 B CN 111627936B CN 202010525361 A CN202010525361 A CN 202010525361A CN 111627936 B CN111627936 B CN 111627936B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/13338—Input devices, e.g. touch panels
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136286—Wiring, e.g. gate line, drain line
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
- G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
- G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
- G06F3/0412—Digitisers structurally integrated in a display
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
- H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1251—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs comprising TFTs having a different architecture, e.g. top- and bottom gate TFTs
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2203/00—Indexing scheme relating to G06F3/00 - G06F3/048
- G06F2203/041—Indexing scheme relating to G06F3/041 - G06F3/045
- G06F2203/04103—Manufacturing, i.e. details related to manufacturing processes specially suited for touch sensitive devices
Abstract
The application provides an array substrate and a preparation method thereof. The application provides a remote touch liquid crystal display device, which comprises the array substrate. According to the array substrate, the preparation method thereof and the remote touch liquid crystal display device, the horizontal channel structure of the TFT in the display pixel area is designed to be the vertical channel, so that the occupied area of the TFT on the substrate is reduced, the aperture ratio of a pixel unit is improved, the vertical channel structure of the TFT reduces the channel length, and the conductivity of the TFT is improved, and therefore the power consumption can be reduced; and the TFT of the display pixel area of the array substrate is compatible with the TFT of the photosensitive pixel area, so that the remote sensing is realized and the manufacturing cost is reduced.
Description
Technical Field
The application relates to the technical field of display, in particular to an array substrate, a preparation method thereof and a remote touch liquid crystal display device.
Background
Thin film transistors are widely used in the display field, and new technologies such as oxide thin film transistors, low-temperature polysilicon thin film transistors and the like are continuously updated. In recent years, hydrogenated amorphous silicon thin film transistor (a-Si: H TFT) technology has been widely used for switching elements of LCDs. Currently, a-Si: the H TFT technology is simple, is suitable for large-area electronic devices, and is helpful for the development of the display industry.
Furthermore, a-Si: the highly photosensitive nature of H-TFTs also offers potential for the application of optical sensors. Using a-Si: the electro-optical properties of the H thin film can be such that a-Si: the H TFT realizes various value-added functions such as X-ray image sensing, fingerprint and optical touch display. For example, oversized interactive screens with remote touch function with these new TFT technologies are highly appreciated in conference room and conference room applications, however, the a-Si photo-sensor needs to occupy a larger device area, which reduces the light transmission area of the lcd, i.e. reduces the aperture ratio.
On the other hand, with the new development of technology, the liquid crystal panel is required to be further refined, improve the aperture ratio, reduce the power consumption and reduce the manufacturing cost, so how to embed the photosensitive thin film transistor into the touch liquid crystal display device and be compatible with the TFT switching process of the touch liquid crystal display device, improve the aperture ratio and further reduce the energy consumption is a problem to be solved.
Disclosure of Invention
The application aims to provide an array substrate, a preparation method thereof and a remote touch liquid crystal display device, so as to solve the problems that a photosensitive thin film transistor cannot be compatible with a manufacturing process of the touch liquid crystal display device when the conventional touch liquid crystal display device realizes remote touch, and the liquid crystal display device has low aperture opening ratio, high power consumption and the like.
The application solves the technical problems by adopting the following technical proposal.
The application provides an array substrate which comprises a substrate, a first data line, a second data line, a first scanning line and a second scanning line, wherein the first data line, the second data line, the first scanning line and the second scanning line are arranged on the substrate, and each two first data lines and each two first scanning lines are crossed to limit a plurality of sub-pixels arranged in an array; each sub-pixel comprises a display pixel area and a photosensitive pixel area, a first thin film transistor is arranged in the display pixel area, a second thin film transistor is arranged in the photosensitive pixel area, the first thin film transistor is electrically connected with the first data line and the first scanning line, and the second thin film transistor is electrically connected with the second data line and the second scanning line;
the first thin film transistor comprises a first source electrode, a first oxide semiconductor layer, a first insulating layer, a second oxide semiconductor layer, a first drain electrode, a third oxide semiconductor layer, a second insulating layer and a first gate electrode which are sequentially stacked from bottom to top;
the second thin film transistor comprises a second grid electrode, the first insulating layer, a channel layer, a second source/drain layer and the second insulating layer which are sequentially stacked from bottom to top;
the first thin film transistor and the second thin film transistor are simultaneously formed on the substrate.
Further, the third oxide semiconductor layer includes a first connection portion, a second connection portion, and a third connection portion; the first connection portion and the first drain electrode are stacked, the second connection portion is electrically connected with one end of the second oxide semiconductor layer, one end of the first oxide semiconductor layer and one end of the first source electrode in sequence, and the third connection portion and the substrate are stacked.
Further, the array substrate further comprises a pixel electrode and a common electrode; the pixel electrode is electrically connected with the first drain electrode, and the common electrode and the pixel electrode are mutually insulated.
Further, the first oxide semiconductor layer, the second oxide semiconductor layer, and the third oxide semiconductor layer are In-Ga-Zn-O-based semiconductors; the channel layer is an amorphous silicon semiconductor.
The application also provides a method for preparing the array substrate, which comprises the following steps: forming a first thin film transistor in the display pixel region of the substrate, and forming a second thin film transistor in the photosensitive pixel region of the substrate, wherein the first thin film transistor and the second thin film transistor are formed synchronously;
and forming a pixel electrode and a common electrode which are mutually insulated on the first thin film transistor, wherein the pixel electrode is electrically connected with the first thin film transistor.
Further, the step of forming the first thin film transistor and the second thin film transistor simultaneously includes: forming a first source electrode and a second gate electrode on the display pixel region and the photosensitive pixel region, respectively, on which the substrate is formed, and forming the first oxide semiconductor layer on the first source electrode.
Further, the first insulating layer is formed over the first source electrode and over the second gate electrode where the first oxide semiconductor layer is formed; the second oxide semiconductor layer is formed over the first oxide semiconductor layer over which the first insulating layer is formed, and a channel layer is formed over the second gate electrode over which the first insulating layer is formed.
Further, the step after forming the second oxide semiconductor layer and the channel layer on the first insulating layer includes: and forming a source/drain metal layer on the second oxide semiconductor layer and the channel layer, etching the source/drain metal layer, forming the first drain electrode above the second oxide semiconductor layer of the display pixel region after etching, and forming the second source/drain layer above the channel layer of the photosensitive pixel region.
Further, the step of etching the source-drain metal layer to form the first drain electrode and the second source/drain layer includes: forming a third oxide semiconductor layer on the first drain electrode; forming a second insulating layer simultaneously over the first drain electrode on which the third oxide semiconductor layer is formed and over the second source/drain layer; a first gate electrode is formed over the third oxide semiconductor layer on which the second insulating layer is formed.
The application also provides a remote touch liquid crystal display device which comprises the array substrate.
According to the array substrate and the preparation method thereof, the horizontal channel structure of TFT (ThinFilm Transistor) of the display pixel area is designed to be the vertical channel, so that the occupied area of the TFT on the substrate is reduced, the aperture opening ratio of the pixel unit is improved, the vertical channel structure of the TFT reduces the channel length, and the conductivity of the TFT is improved, and therefore the power consumption can be reduced. And the manufacturing process of the thin film transistor of the display pixel area of the array substrate is compatible with the manufacturing process of the thin film transistor of the photosensitive pixel area, so that the manufacturing cost can be reduced while the remote sensing is realized.
Drawings
Fig. 1 is a schematic cross-sectional view of a remote touch liquid crystal display device according to an embodiment of the application.
Fig. 2 is a schematic plan view of a color filter substrate according to an embodiment of the application.
Fig. 3 is a schematic plan view of an array substrate according to an embodiment of the application.
Fig. 4a to fig. 4n are flowcharts of a process for manufacturing an array substrate according to an embodiment of the application.
Detailed Description
In order to further describe the technical manner and efficacy of the present application for achieving the intended purpose, the following detailed description of the embodiments, structures, features and efficacy of the application refers to the accompanying drawings and examples.
Fig. 1 is a schematic cross-sectional view of a remote touch liquid crystal display device according to an embodiment of the present application, fig. 2 is a schematic plan view of a color filter substrate according to an embodiment of the present application, and fig. 3 is a schematic plan view of an array substrate according to an embodiment of the present application. Referring to fig. 1 to 3, an embodiment of the application provides a remote touch liquid crystal display device, which includes an array substrate 100, wherein the array substrate 100 includes a plurality of sub-pixels SP (sub-pixels) arranged in an array, a first data line 41, a second data line 42, a first scan line 51, a second scan line 52, and a substrate 110.
In this embodiment, the sub-pixel SP is, for example, a red R, green G or blue B sub-pixel, and a plurality of adjacent sub-pixels SP form one display pixel (pixel). For example, one display pixel may include three subpixels SP of red R, green G, and blue B.
Each sub-pixel SP includes a display pixel area SP1, a photosensitive pixel area SP2, and a pixel electrode 31 and a first thin film transistor 10 electrically connected and a common electrode 32 insulated from the pixel electrode 31 are disposed in the display pixel area SP 1; the second thin film transistor 20 is disposed in the photosensitive pixel region SP2.
The first thin film transistor 10, i.e., the TFT of the display pixel area SP1, includes: the first source electrode 12, the first oxide semiconductor layer 141, the first insulating layer 101, the second oxide semiconductor layer 142, the first drain electrode 13, the third oxide semiconductor layer 143, the second insulating layer 103, and the first gate electrode 11. Wherein the third oxide semiconductor layer 143 includes a first connection portion 143a, a second connection portion 143b, and a third connection portion 143c; the first connection portion 143a is stacked on the first drain electrode 13, the second connection portion 143b is electrically connected to one end of the second oxide semiconductor layer 142, one end of the first oxide semiconductor layer 141, and one end of the first source electrode 12 in this order, and the third connection portion 143c is stacked on the substrate 110. In this embodiment, the materials of the first oxide semiconductor layer 141, the second oxide semiconductor layer 142 and the third oxide semiconductor layer 143 are amorphous indium gallium zinc oxide (indium gallium zinc oxide, IGZO), and the amorphous oxide IGZO is used as the material of the semiconductor layer, so that the problem of overheating of the transistor leakage current caused by using conventional silicon oxide can be effectively reduced.
Preferably, in the present embodiment, the ratio (composition ratio) of indium (In), gallium (Ga) and zinc (Zn) In the first oxide semiconductor layer 141 is 1:1:1, that is, in: ga: zn=1:3:6, the composition ratio of indium gallium zinc In the second oxide semiconductor layer 142 is In: ga: zn=1:3:6, and the composition ratio of indium gallium zinc In the third oxide semiconductor layer 143 is In: ga: zn=1:1:1.
In addition, it can be seen that the first oxide semiconductor layer 141, the second oxide semiconductor layer 142 and the third oxide semiconductor layer 143 in the first thin film transistor 10 of the present embodiment form a vertical channel structure, and the channel length is the vertical distance from the first source electrode 12 to the first drain electrode 13, and the vertical distance is only formed by the thicknesses of the three layers of films of the first oxide semiconductor layer 141, the first insulating layer 101 and the second oxide semiconductor layer 142, so that compared with the horizontal channel structure in the prior art, the channel length is greatly reduced, the conductivity of the TFT (first thin film transistor 10) of the display pixel area SP1 is increased, and the power consumption of the liquid crystal display is reduced.
Because of the vertical channel design of the first thin film transistor 10, the first source 12 and the first drain 13 of the first thin film transistor 10 are not horizontally arranged on the same layer similar to the TFT source and drain in the prior art, but are vertically stacked, so that the overall width of the TFT is reduced, that is, the area occupied by the TFT element in the pixel display area is reduced, and the aperture ratio of the pixel unit is improved.
The second thin film transistor 20 includes a second gate electrode 21, a first insulating layer 101, a channel layer 24, a second source/drain layer 22, and a second insulating layer 103, which are sequentially stacked from bottom to top, wherein the channel layer 24 is made of hydrogenated amorphous silicon (a-Si: H) and has a photosensitive property, and a portion of the photosensitive channel layer needs to be exposed to receive light, so that the second thin film transistor 20 is designed as a horizontal channel.
Referring to fig. 1 to 3, the first data line 41 and the second data line 42 are adjacent and disposed in parallel, and the first scan line 51 and the second scan line 52 are adjacent and disposed in parallel. The first source electrode 12 of the first thin film transistor 10 is electrically connected to the first data line 41, the first gate electrode 11 is connected to the first scan line 51, and the first drain electrode 15 is electrically connected to the pixel electrode 31.
Further, the second gate electrode 21 of the second thin film transistor 20 is connected to the second scan line 52, and the channel layer 24 is disposed above the second gate electrode 21 and electrically connected to the source and drain electrodes of the second source/drain layer 22, respectively. One of the source and drain electrodes of the second source/drain layer 22 is connected to the second data line 42, and the other of the source and drain electrodes of the second source/drain layer 22 is connected to the second scan line 52 through a contact hole, for example, the source electrode of the second source/drain layer 22 is connected to the second data line 42, and the drain electrode of the second source/drain layer 22 is connected to the second scan line 52 through a contact hole.
Thus, the first thin film transistor 10 is electrically connected to the first data line 41 and the first scanning line 51, and the second thin film transistor 20 is electrically connected to the second data line 42 and the second scanning line 52. In this embodiment, the first scan line 51 and the second scan line 52 may be connected to the same signal terminal to receive the same electrical signal.
Referring to fig. 1 to 3, the lcd touch display device further includes a color filter substrate 200 disposed opposite to the array substrate 100, where the color filter substrate 200 includes a first color blocking region 201, a second color blocking region 202, and a third color blocking region 203, for example: the first color resist region 201 is a red color resist region, the second color resist region is a green color resist region, and the third color resist region 203 is a blue color resist region. Each color resistance region is disposed corresponding to one sub-pixel SP on the array substrate 100.
When the LED light or the laser irradiates on the liquid crystal touch display device, the LED light or the laser irradiates on the array substrate 100 through the color filter substrate 200, and the photosensitive thin film transistor 20 of the array substrate 100 can convert the light intensity into an electrical signal, so that the non-contact remote touch can be realized.
Fig. 4a to 4n are flowcharts of a process for manufacturing an array substrate according to an embodiment of the present application, and referring to fig. 4a to 4n, an embodiment of the present application provides a method for manufacturing an array substrate, including:
the first thin film transistor 10 and the second thin film transistor 20 are formed simultaneously in the display pixel area SP1 and the photosensitive pixel area SP2 on the base 110 of the array substrate 100.
The following describes the manufacturing process of the array substrate 100 in detail.
Referring to fig. 4a, a substrate 110 is provided, and a first source electrode 12 and a second gate electrode 21 are formed on the substrate 110 simultaneously, wherein the first source electrode 12 is located in the display pixel area SP1, and the second gate electrode 21 is located in the photosensitive pixel area SP2.
Referring to fig. 4b, a first oxide semiconductor layer 141, which is an amorphous indium gallium zinc oxide semiconductor material, is formed over the first source electrode 12.
Referring to fig. 4c, a first insulating layer 101 is simultaneously formed over the first source electrode 12 and over the second gate electrode 21 where the first oxide semiconductor layer 141 is formed.
Referring to fig. 4d, a second oxide semiconductor layer 142 is formed over the first oxide semiconductor layer 141 where the first insulating layer 101 is formed.
Referring to fig. 4e, a channel layer 24 is formed over the second gate electrode 21 having the first insulating layer 101 formed thereon.
The channel layer 24 may be formed over the second gate electrode 21 in which the first insulating layer 101 is formed, and then the second oxide semiconductor layer 142 may be formed over the first oxide semiconductor layer 141 in which the first insulating layer 101 is formed. That is, the two film formation sequences of fig. 4d and 4e may be reversed.
Referring to fig. 4f, a source-drain metal layer (not shown) is formed on the second oxide semiconductor layer 142 and the channel layer 24, and is etched after the source-drain metal layer is formed. The first drain electrode 13 is formed over the second oxide semiconductor layer 142 of the display pixel region SP1 after etching, and the second source/drain layer 22 is formed over the channel layer 24 of the photosensitive pixel region SP2.
Referring to fig. 4g, the third oxide semiconductor layer 143 is formed on the first drain electrode 13, and in fig. 4g, the first connection portion 143a of the third oxide semiconductor layer 143 is stacked on the first drain electrode 13, and the second connection portion 143b of the third oxide semiconductor layer 143 is sequentially electrically connected to one end of the second oxide semiconductor layer 142, one end of the first oxide semiconductor layer 141, and one end of the first source electrode 12, and the third connection portion 143c of the third oxide semiconductor layer 143 is stacked on the substrate 110.
Referring to fig. 4h, a second insulating layer 103 is simultaneously formed over the first drain electrode 13 formed with the third oxide semiconductor layer 143 and over the second source/drain layer 22, the second insulating layer 103 covering the display pixel region SP1 and the photosensitive pixel region SP2.
Referring to fig. 4i, the first gate electrode 11 is formed over the third oxide semiconductor layer 143 having the second insulating layer 103 formed thereon. An organic planarization layer 104 is formed over the second insulating layer 103 formed with the first gate electrode 11, and the organic planarization layer 104 covers the display pixel region SP1 and the photosensitive pixel region SP2.
Referring to fig. 4j to 4k, after etching the organic planarization layer 104, a first contact hole 106 is formed to partially expose the second insulating layer 103, and then a common electrode 32 is formed over the second insulating layer 103. The common electrode 32 is formed only in the display pixel area SP 1.
Referring to fig. 4l, a third insulating layer 105 is formed over the substrate 110 on which the common electrode 32 is formed, the third insulating layer 105 being in contact with the second insulating layer 103 at the first contact hole 106. The third insulating layer 105 covers the display pixel area SP1 and the photosensitive pixel area SP2.
Referring to fig. 4m to 4n, the third insulating layer 105 is etched to expose the first drain electrode 13, and then the pixel electrode 31 is formed over the third insulating layer 105, and the pixel electrode 31 contacts with the first drain electrode 13. Wherein the pixel electrode 31 is formed only above the display pixel area SP 1.
According to the array substrate and the preparation method thereof, the horizontal channel structure of the TFT of the display pixel area SP1 is designed to be the vertical channel, so that the occupied area of the TFT on the substrate is reduced, the aperture opening ratio of the pixel unit is improved, the vertical channel structure of the TFT reduces the channel length, and the conductivity of the TFT is improved, and therefore the power consumption can be reduced. And the manufacturing process of the thin film transistor of the display pixel area SP1 of the array substrate and the manufacturing process of the thin film transistor of the photosensitive pixel area SP2 are compatible, so that the manufacturing cost can be reduced while the remote sensing is realized.
In this document, terms such as front, rear, upper, lower, etc. are defined with respect to the positions of the components in the drawings and with respect to each other, for clarity and convenience in expressing the technical solution. It should be understood that the use of such orientation terms should not limit the scope of the claimed application.
The foregoing description of the preferred embodiments of the application is not intended to limit the application to the precise form disclosed, and any such modifications, equivalents, and alternatives falling within the spirit and scope of the application are intended to be included within the scope of the application.
Claims (10)
1. An array substrate (100), wherein the array substrate (100) comprises a base (110) and first data lines (41), second data lines (42), first scanning lines (51) and second scanning lines (52) arranged on the base (110), and each two adjacent first data lines (41) and each two adjacent first scanning lines (51) are crossed to define a plurality of sub-pixels (SP) arranged in an array;
each sub-pixel (SP) comprises a display pixel region (SP 1) and a photosensitive pixel region (SP 2), a first thin film transistor (10) is arranged in the display pixel region (SP 1), a second thin film transistor (20) is arranged in the photosensitive pixel region (SP 2), a first gate (11) of the first thin film transistor (10) is connected to the first scanning line (51), a first source (12) of the first thin film transistor (10) is electrically connected to the first data line (41), a first drain (13) of the first thin film transistor (10) is electrically connected to a pixel electrode (31), the pixel electrode (31) is formed only above the display pixel region (SP 1), a second gate (21) of the second thin film transistor (20) is connected to a second scanning line (52), one of a source and a drain of a second source/drain layer (22) of the second thin film transistor (20) is connected to the second data line (41), and the other source/drain is connected to the second scanning line (42) through the second drain/source hole (52);
the first thin film transistor (10) comprises a first source electrode (12), a first oxide semiconductor layer (141), a first insulating layer (101), a second oxide semiconductor layer (142), a first drain electrode (13), a third oxide semiconductor layer (143), a second insulating layer (103) and a first gate electrode (11) which are sequentially stacked from bottom to top;
the second thin film transistor (20) comprises a second grid electrode (21), the first insulating layer (101), a channel layer (24), a second source/drain layer (22) and the second insulating layer (103) which are sequentially stacked from bottom to top;
the first thin film transistor (10) and the second thin film transistor (20) are formed simultaneously on the substrate (100).
2. The array substrate (100) according to claim 1, wherein the third oxide semiconductor layer (143) includes a first connection portion (143 a), a second connection portion (143 b), and a third connection portion (143 c); the first connection portion (143 a) and the first drain electrode (13) are stacked, the second connection portion (143 b) is electrically connected to one end of the second oxide semiconductor layer (142), one end of the first oxide semiconductor layer (141), and one end of the first source electrode (12) in sequence, and the third connection portion (143 c) and the substrate (110) are stacked.
3. The array substrate (100) of claim 1, wherein the array substrate (100) further comprises a common electrode (32), the common electrode (32) being insulated from the pixel electrode (31).
4. The array substrate (100) according to claim 1, wherein the first oxide semiconductor layer (141), the second oxide semiconductor layer (142), and the third oxide semiconductor layer (143) are all In-Ga-Zn-O-based semiconductors; the channel layer (24) is an amorphous silicon semiconductor.
5. A method for manufacturing an array substrate (100) for manufacturing the array substrate (100) according to any one of claims 1 to 4, comprising the steps of:
forming a first thin film transistor (10) in a display pixel region (SP 1) of a substrate (110), forming a second thin film transistor (20) in a photosensitive pixel region (SP 2) of the substrate (110), the first thin film transistor (10) and the second thin film transistor (20) being formed simultaneously;
a pixel electrode (31) and a common electrode (32) are formed on the first thin film transistor (10) so as to be insulated from each other, and the pixel electrode (31) is electrically connected to the first thin film transistor (10).
6. The method of manufacturing an array substrate (100) according to claim 5, wherein the step of simultaneously forming the first thin film transistor (10) and the second thin film transistor (20) includes: after forming a first source electrode (12) and a second gate electrode (21) in the display pixel region (SP 1) and the photosensitive pixel region (SP 2) on which the substrate (110) is formed, respectively, a first oxide semiconductor layer (141) is formed on the first source electrode (12).
7. The method of manufacturing an array substrate (100) according to claim 6, wherein the step of forming the first oxide semiconductor layer (141) on the first source electrode (12) further comprises: forming an insulating layer (101) over the first source electrode (12) and over the second gate electrode (21) in which the first oxide semiconductor layer (141) is formed; a second oxide semiconductor layer (142) is formed on the first oxide semiconductor layer (141) on which the first insulating layer (101) is formed, and a channel layer (24) is formed on the second gate electrode (21) on which the first insulating layer (101) is formed.
8. The method of manufacturing an array substrate (100) according to claim 7, wherein the step after forming the second oxide semiconductor layer (142) and the channel layer (24) on the first insulating layer (101) includes: a source-drain metal layer is formed on the second oxide semiconductor layer (142) and the channel layer (24), the source-drain metal layer is etched, a first drain electrode (13) is formed over the second oxide semiconductor layer (142) of the display pixel region (SP 1) after etching, and a second source/drain layer (22) is formed over the channel layer (24) of the photosensitive pixel region (SP 2).
9. The method of manufacturing an array substrate (100) according to claim 8, wherein the step of etching the source-drain metal layer to form the first drain electrode (13) and the second source/drain layer (22) includes: forming a third oxide semiconductor layer (143) on the first drain electrode (13);
-forming a second insulating layer (103) simultaneously on the first drain electrode (13) on which the third oxide semiconductor layer (143) is formed and on the second source/drain layer (22); a first gate electrode (11) is formed over the third oxide semiconductor layer (143) on which the second insulating layer (103) is formed.
10. A remote touch liquid crystal display device comprising the device according to any one of claims 1 to 4
The array substrate (100) according to any one of the above.
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| CN108446051A (en) * | 2018-03-16 | 2018-08-24 | 深圳市华星光电技术有限公司 | Array substrate and touch control display apparatus |
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| CN108446051A (en) * | 2018-03-16 | 2018-08-24 | 深圳市华星光电技术有限公司 | Array substrate and touch control display apparatus |
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