CN117525083A - Array substrate and display panel - Google Patents

Array substrate and display panel Download PDF

Info

Publication number
CN117525083A
CN117525083A CN202310998223.0A CN202310998223A CN117525083A CN 117525083 A CN117525083 A CN 117525083A CN 202310998223 A CN202310998223 A CN 202310998223A CN 117525083 A CN117525083 A CN 117525083A
Authority
CN
China
Prior art keywords
layer
electrode
substrate
array substrate
insulating layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202310998223.0A
Other languages
Chinese (zh)
Inventor
刘娜
陈中明
艾飞
黄灿
张春鹏
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Wuhan China Star Optoelectronics Technology Co Ltd
Original Assignee
Wuhan China Star Optoelectronics Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Wuhan China Star Optoelectronics Technology Co Ltd filed Critical Wuhan China Star Optoelectronics Technology Co Ltd
Priority to CN202310998223.0A priority Critical patent/CN117525083A/en
Publication of CN117525083A publication Critical patent/CN117525083A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/126—Shielding, e.g. light-blocking means over the TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H10K59/1315—Interconnections, e.g. wiring lines or terminals comprising structures specially adapted for lowering the resistance

Abstract

The invention provides an array substrate and a display panel, wherein the array substrate comprises a substrate, and an active layer, a grid electrode and a source drain electrode which are sequentially arranged on the substrate. By arranging the color resistance layer below the source drain electrode, the color resistance layer does not affect the overlap joint distance between the pixel electrode and the source drain electrode, so that the overlap joint impedance between the pixel electrode and the source drain electrode is reduced, and finally the electrical stability of the display panel is effectively improved.

Description

Array substrate and display panel
Technical Field
The invention relates to the technical field of display, in particular to an array substrate and a display panel.
Background
In LCD (Liquid Crystal Display) display and part OLED (Organic Emitting Diode) display, micro/mini LED (Light Emitting Diode) display modes, color Filters (CF) are used to display Color or enhance Color rendering. In the related art, the color resistance layer in the color film causes the increase of the overlap impedance between the pixel electrode and the source/drain electrode, which affects the display stability of the display panel.
Disclosure of Invention
The embodiment of the invention provides an array substrate and a display panel, which are used for solving the problem that in the related art, the overlap impedance between a pixel electrode and a source drain electrode is increased due to a color resistance layer in a color film, so that the display stability of the display panel is affected.
In a first aspect, the application provides an array substrate, including a substrate, and set gradually in active layer, grid and source drain electrode on the substrate, array substrate still includes the look and hinders the layer, look hinder the layer set up in the grid with between the source drain electrode, the source drain electrode pass through the via hole with active layer electric connection, and at least one the via hole runs through look hinders the layer.
In an embodiment, the device further includes a gate insulating layer and a first interlayer insulating layer, the gate insulating layer is disposed between the gate and the active layer, the first interlayer insulating layer is disposed on the gate, and the color resist layer is disposed on the first interlayer insulating layer.
In an embodiment, the device further includes a second interlayer insulating layer and a first planarization layer, the second interlayer insulating layer is disposed on a side of the color resistance layer away from the substrate, and the first planarization layer is disposed on a side of the second interlayer insulating layer away from the substrate.
In an embodiment, the via hole includes a first via hole and a second via hole, the first via hole penetrates through the second interlayer insulating layer, the color resistance layer, the first interlayer insulating layer and the gate insulating layer in sequence, and the second via hole penetrates through the first flat layer, the second interlayer insulating layer, the color resistance layer, the first interlayer insulating layer and the gate insulating layer in sequence; the source electrode comprises a first source electrode and a second source electrode, the first source electrode is located on the second interlayer insulating layer, the second source electrode is electrically connected with the active layer through the first via hole, the drain electrode comprises a first drain electrode portion and a second drain electrode portion, the first drain electrode portion is located on the first flat layer, and the second drain electrode portion is electrically connected with the active layer through the second via hole.
In an embodiment, the semiconductor device further includes a first passivation layer, the first passivation layer is disposed on a side of the first planarization layer away from the substrate, the first passivation layer is provided with an opening, and the first drain portion is exposed to the opening.
In an embodiment, the display device further includes a pixel electrode layer, the pixel electrode layer is disposed on a side of the first passivation layer away from the substrate, and the pixel electrode layer includes a pixel electrode electrically connected to the first drain portion.
In an embodiment, the pixel electrode layer is located between the second passivation layer and the third passivation layer, the wiring layer comprises a common electrode wiring, the common electrode layer comprises a common electrode electrically connected with the common electrode wiring, the common electrode is provided with a groove corresponding to the opening, and the groove is filled with a flat part.
In an embodiment, the display device further includes a light shielding portion, the light shielding portion is disposed on a side of the common electrode layer away from the substrate, and the material of the first light shielding layer is a low-reflection metal material.
In an embodiment, the source and drain electrodes are made of copper metal.
In a second aspect, the present application provides a display panel comprising an array substrate as described in any one of the above.
In the array substrate provided by the embodiment of the invention, the color resistance layer is arranged below the source drain electrode, so that the color resistance layer does not influence the overlap joint distance between the pixel electrode and the source drain electrode, and further the overlap joint impedance between the pixel electrode and the source drain electrode is reduced, and finally the electrical stability of the display panel is effectively improved.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings that are needed in the description of the embodiments will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present invention, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic structural diagram of a display panel according to an embodiment of the present invention.
Detailed Description
In the following detailed description, certain embodiments of the invention are shown and described, simply by way of illustration. As will be appreciated by those skilled in the art, the embodiments described herein may be modified in numerous ways without departing from the spirit or scope of the present invention.
In the drawings, the thickness of layers, films, plates, regions, etc. may be exaggerated for clarity and for better understanding and ease of description. It will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" another element, it can be directly on the other element or intervening elements may also be present.
In addition, unless explicitly described to the contrary, the word "comprise" and variations such as "comprises" or "comprising" will be understood to imply the inclusion of stated elements but not the exclusion of other elements. Further, in the specification, the word "on … …" means placed above or below the object portion, and not necessarily placed on the upper side of the object portion based on the direction of gravity.
It will be understood that, although the terms "first," "second," etc. may be used herein to describe various components, these components should not be limited by these terms. These components are only used to distinguish one component from another.
As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.
It will be further understood that the terms "comprises" and/or "comprising," when used herein, specify the presence of stated features or components, but do not preclude the presence or addition of one or more other features or components.
It will be understood that when a layer, region or element is referred to as being "formed on" another layer, region or element, it can be directly or indirectly formed on the other layer, region or element. For example, intervening layers, regions, or components may be present.
As shown in fig. 1, the present embodiment provides an array substrate, which includes a substrate 110, a buffer layer 130, an active layer 140, a gate insulating layer 150, a gate electrode 160, a first interlayer insulating layer 170, a second dielectric layer, a source electrode 200, a drain electrode 220, and a planarization layer.
The substrate base 110 may be made of an organic material having insulating properties and being flexible so as to be capable of heat treatment at a temperature equal to or greater than about 450 ℃, and the substrate base 110 may be formed as a single layer formed of polyimide, for example, or may be formed as a plurality of layers formed by repeatedly stacking polyimide by coating and curing. The substrate 110 may be a flexible substrate 110 formed by coating a polymeric material such as polyimide on a supporting substrate 110 (not shown) and curing the polymeric material. In this case, the base substrate 110 may be formed into a plurality of layers by repeatedly coating and curing the polymeric material. The supporting substrate 110 may be formed of glass, metal, or ceramic, and polyimide may be coated on the supporting substrate 110 through a coating process such as spin coating, slot coating, inkjet coating, or the like. The support substrate 110 may be removed in a subsequent process.
The buffer layer 130 may provide a planarization layer on the upper surface of the substrate base 110, and may prevent or prevent impurities and moisture from penetrating from the substrate base 110 into the display unit (i.e., the organic light emitting element).
The active layer 140 is formed on the buffer layer 130, wherein the active layer 140 is formed of polysilicon. Wherein the active layer 140 is divided into a channel region and source and drain regions (not shown) formed at both sides of the channel region. The channel region of the active layer 140 is polysilicon, i.e., the intrinsic active layer 140, which is not doped with impurities. The source and drain regions are polysilicon doped with conductive impurities, i.e., impurity active layers 140. The impurity doped in the source region and the drain region may be any one of a P-type impurity and an N-type impurity.
The gate insulating layer 150 is formed on the active layer 140. The gate insulating layer 150 may be a plurality of layers or a single layer including at least one of tetraethyl orthosilicate (TEOS), silicon nitride, silicon oxide, and the like.
A gate electrode 160 is formed on the gate insulating layer 150, and the gate electrode 160 overlaps the channel region. The gate electrode 160 may be formed as multiple layers or monolayers including a low resistance material such as Al, ti, mo, cu, ni, or an alloy thereof, or a material having high corrosion resistance properties. The first interlayer insulating layer 170 is formed on the gate electrode 160.
The source electrode 200 and the drain electrode 220 are formed on the first interlayer insulating layer 170. Among them, the source electrode 200 and the drain electrode 220 may be formed as a plurality of layers or single layers of a low-resistance material such as Al, ti, mo, cu, ni, or an alloy thereof, or a material having high corrosion resistance. For example, the source electrode 200 and the drain electrode 220 may be triple layers of Ti/Cu/Ti, ti/Ag/Ti, ti/Al/Ti or Mo/Al/Mo, among others.
In addition, the gate electrode 160, the source electrode 200, and the drain electrode 220 are control electrodes, input electrodes, and output electrodes of the thin film transistors in the display panel driving circuit, respectively, and form the thin film transistors together with the active layer 140. The channel of the thin film transistor is between the source electrode 200 and the drain electrode 220.
In an embodiment, the array substrate further includes a color resist layer 180, where the color resist layer 180 is disposed on the first interlayer insulating layer 170 and is located below the source/drain electrode, and the source/drain electrode is electrically connected to the active layer 140 through a via hole. Specifically, the source electrode 200 is connected to the source region through the via hole, the drain electrode 220 is connected to the drain region through the via hole, and at least one of the via holes penetrates through the color resist layer 180.
It can be appreciated that, since the color resist layer 180 is disposed below the source and drain electrodes, the color resist layer 180 does not affect the overlap distance between the pixel electrode 260 and the source and drain electrodes, i.e., the depth of the via hole for overlapping the pixel electrode 260 and the source and drain electrodes is reduced, thereby reducing the overlap resistance between the pixel electrode 260 and the source and drain electrodes.
In this embodiment, the color resist layer 180 is disposed below the source/drain electrode, so that the color resist layer 180 does not affect the overlap distance between the pixel electrode 260 and the source/drain electrode, and further the overlap impedance between the pixel electrode 260 and the source/drain electrode is reduced, thereby finally effectively improving the electrical stability of the display panel.
In one embodiment, the color resist layer 180 includes a first color resist (R), a second color resist (G), and a third color resist (B).
As can be appreciated, in the present embodiment, by disposing the color resist layer 180 below the drain electrode, compared with the structure of a common color film substrate, the color resist layer 180 is not disposed on the color film substrate, that is, the color resist layer 180 is not disposed on the second substrate 330 in the present embodiment, so that the liquid crystal layer is not interposed between the color resist layer 180 and the backlight, and the distance between the backlight and the color resist layer 180 is closer because the liquid crystal layer is not interposed therebetween, thereby improving the color cast condition of the manufactured display panel, and effectively reducing the color cast defect of the display panel under a large viewing angle.
In an embodiment, the array substrate further includes a second interlayer insulating layer 190 and a first planarization layer 210, the second interlayer insulating layer 190 is disposed on a side of the color resist layer 180 away from the substrate 110, and the source electrode 200 is formed on the second interlayer insulating layer 190. The first planarization layer 210 is disposed on a side of the second interlayer insulating layer 190 remote from the substrate base 110, and the drain electrode 220 is formed on the first planarization layer 210.
In an embodiment, the via hole includes a first via hole and a second via hole, the first via hole penetrates through the second interlayer insulating layer 190, the color resist layer 180, the first interlayer insulating layer 170 and the gate insulating layer 150 in sequence, and the second via hole penetrates through the first planarization layer 210, the second interlayer insulating layer 190, the color resist layer 180, the first interlayer insulating layer 170 and the gate insulating layer 150 in sequence.
The source electrode 200 includes a first source portion and a second source portion, the first source portion is located on the second interlayer insulating layer 190, and the second source portion is electrically connected to the active layer 140 through the first via hole. The drain electrode 220 includes a first drain portion and a second drain portion, the first drain portion is located on the first planarization layer 210, and the second drain portion is electrically connected to the active layer 140 through the second via hole.
In an embodiment, the source and drain electrodes are made of copper metal. By adopting the metallic copper with good conductivity, the step of annealing treatment is not needed in the process technology, so that the stability of the prepared color resistance layer 180 can be effectively ensured, and meanwhile, the contact resistance can be reduced, and the successful lap joint of a circuit can be ensured.
In an embodiment, the array substrate further includes a first passivation layer 230, a routing layer 240, a second passivation layer 250, a pixel electrode layer, a third passivation layer 270, and a common electrode layer 280, wherein the first passivation layer 230 is disposed on a side of the first planarization layer 210 away from the substrate 110, and the first passivation layer 230 is provided with an opening, and the first drain portion is exposed to the opening. The trace layer 240 includes common electrode traces. The pixel electrode layer includes a pixel electrode 260 electrically connected to the first drain portion, and is located between the second passivation layer 250 and the third passivation layer 270. The common electrode layer 280 includes a common electrode electrically connected to the common electrode trace, the common electrode is provided with a groove corresponding to the opening, and a second flat layer is filled in the groove, and the second flat layer includes a flat portion 340.
Although not explicitly shown in fig. 1, in the present embodiment, the common electrode trace is substantially connected to the common electrode, and the common electrode trace is connected to the common electrode, so that the common electrode trace and the common electrode have the same voltage, and the pixel electrode 260 and the common electrode have different driving voltages, so that the adjacent liquid crystal 300 in the liquid crystal layer can be driven to rotate.
In the display panel, the color resist layer is formed on the substrate 110, which can increase the aperture ratio of the display panel, improve the transmittance and reduce the parasitic capacitance, but when the black organic BM film layer is used to shield the metal reflection of the substrate 110, the black organic BM film layer is easy to generate edge burrs and corner arc angles when the line width is relatively narrow, resulting in defects such as reduced picture definition.
Therefore, in an embodiment, the array substrate further includes a light shielding portion 290, a first light shielding layer 320, and a second light shielding layer 120. The light shielding portion 290 is disposed on a side of the common electrode layer 280 away from the substrate 110, and the material of the light shielding portion 290 is a low-reflection metal material, and at least a portion of the light shielding portion 290 covers a boundary between two of the first color resistor, the second color resistor and the third color resistor. The first light shielding layer 320 is positioned under the second substrate 330, and the light shielding portion 290 is positioned under the first light shielding layer 320. The second light shielding layer 120 is located on the substrate 110 and below the active layer 140.
In this embodiment, the first light shielding layer 320 and the light shielding portion 290 are simultaneously disposed on the substrate 110, where the first light shielding layer 320 is disposed on the second substrate 330, the light shielding portion 290 is disposed on the substrate 110, and at least a portion of the light shielding portion 290 covers a boundary between any two of the first color resistor, the second color resistor and the third color resistor, and positions of the first light shielding layer 320 and the light shielding portion 290 do not overlap each other.
It can be appreciated that, in this embodiment, the light shielding portion 290 is made of a non-conventional organic material, but a metal material is used to prepare the first light shielding layer 320, and a film layer prepared by using a low-reflection metal material replaces the existing black organic BM film layer, so that, on one hand, a positive photoresist mask can be used to prepare a line width with higher resolution, and further, the resolution of the prepared display panel is improved, and on the other hand, since the material of the first light shielding layer 320 is replaced by the existing organic material by the low-reflection metal material, edge burrs and corner arc angles are not easy to occur, so that the problem of blurring of the display screen of the prepared display panel can be improved, and the prepared display panel has better display effect.
Wherein the low reflection metal material is selected from one or more of metal or metal oxide, wherein the metal is selected from Mo, W, ti or Al.
In this embodiment, the material of the light shielding portion 290 may be selected from Mo, W, ti, or Al alone, or may be selected from one or more of Mo and W, mo and Al, W and Ti, W and Al, ti and Al, or Ti and Al.
Specifically, in some embodiments, a width of at least a portion of the light shielding portion 290 is smaller than a width of the first light shielding layer 320.
As can be appreciated, in this embodiment, the light shielding portion 290 is made of the low reflective metal material, and the low reflective metal material is not prone to edge burrs and corner arc angles, so that the width of the light shielding portion 290 can be reduced according to practical requirements, and after the width of the light shielding portion 290 is reduced, the resolution of the manufactured display panel is directly improved.
Further, as shown in fig. 1, the array substrate further includes a liquid crystal layer between the substrate 110 and the second substrate 330, and the first light shielding layer 320 and the light shielding part 290 are located at opposite sides of the liquid crystal layer.
Further, the array substrate further includes spacers 310, and the spacers 310 are located between the first light shielding layer 320 and the flat portion 340, and it is understood that the spacers 310 can support the second substrate 330.
The present embodiment also provides a display panel, which includes the array substrate and the second substrate 330.
The principles and embodiments of the present invention have been described herein with reference to specific examples, the description of which is intended only to assist in understanding the methods of the present invention and the core ideas thereof; meanwhile, as those skilled in the art will have variations in the specific embodiments and application scope in light of the ideas of the present invention, the present description should not be construed as limiting the present invention.

Claims (10)

1. The array substrate comprises a substrate, an active layer, a grid electrode and a source drain electrode, wherein the active layer, the grid electrode and the source drain electrode are sequentially arranged on the substrate, and the array substrate is characterized by further comprising a color resistance layer, wherein the color resistance layer is arranged between the grid electrode and the source drain electrode, the source drain electrode is electrically connected with the active layer through a via hole, and at least one via hole penetrates through the color resistance layer.
2. The array substrate of claim 1, further comprising a gate insulating layer disposed between the gate and the active layer and a first interlayer insulating layer disposed on the gate, the color resist layer disposed on the first interlayer insulating layer.
3. The array substrate according to claim 2, further comprising a second interlayer insulating layer and a first planarization layer, wherein the second interlayer insulating layer is disposed on a side of the color resist layer away from the substrate, and the first planarization layer is disposed on a side of the second interlayer insulating layer away from the substrate.
4. The array substrate of claim 3, wherein the via hole comprises a first via hole and a second via hole, the first via hole penetrates through the second interlayer insulating layer, the color resist layer, the first interlayer insulating layer and the gate insulating layer in sequence, and the second via hole penetrates through the first planarization layer, the second interlayer insulating layer, the color resist layer, the first interlayer insulating layer and the gate insulating layer in sequence;
the source electrode comprises a first source electrode and a second source electrode, the first source electrode is located on the second interlayer insulating layer, the second source electrode is electrically connected with the active layer through the first via hole, the drain electrode comprises a first drain electrode portion and a second drain electrode portion, the first drain electrode portion is located on the first flat layer, and the second drain electrode portion is electrically connected with the active layer through the second via hole.
5. The array substrate of claim 4, further comprising a first passivation layer disposed on a side of the first planarization layer remote from the substrate, the first passivation layer being provided with an opening, the first drain portion being exposed to the opening.
6. The array substrate of claim 5, further comprising a pixel electrode layer disposed on a side of the first passivation layer away from the substrate, the pixel electrode layer including a pixel electrode electrically connected to the first drain portion.
7. The array substrate of claim 6, further comprising a routing layer, a second passivation layer, a third passivation layer, and a common electrode layer sequentially disposed on the first passivation layer, wherein the pixel electrode layer is disposed between the second passivation layer and the third passivation layer, the routing layer comprises a common electrode routing, the common electrode layer comprises a common electrode electrically connected to the common electrode routing, the common electrode is provided with a groove corresponding to the opening, and the groove is filled with a flat portion.
8. The array substrate according to claim 7, further comprising a light shielding portion disposed on a side of the common electrode layer away from the substrate, wherein a material of the light shielding portion is a low-reflection metal material.
9. The array substrate of claim 1, wherein the source and drain electrodes are made of copper metal.
10. A display panel comprising an array substrate according to any one of claims 1-9.
CN202310998223.0A 2023-08-09 2023-08-09 Array substrate and display panel Pending CN117525083A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202310998223.0A CN117525083A (en) 2023-08-09 2023-08-09 Array substrate and display panel

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202310998223.0A CN117525083A (en) 2023-08-09 2023-08-09 Array substrate and display panel

Publications (1)

Publication Number Publication Date
CN117525083A true CN117525083A (en) 2024-02-06

Family

ID=89742681

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202310998223.0A Pending CN117525083A (en) 2023-08-09 2023-08-09 Array substrate and display panel

Country Status (1)

Country Link
CN (1) CN117525083A (en)

Similar Documents

Publication Publication Date Title
JP4301259B2 (en) Liquid crystal display device and manufacturing method thereof
US20190227373A1 (en) Liquid crystal display device and manufacturing method thereof
US10535682B2 (en) Active device array substrate
US9673229B2 (en) Array substrate, method for manufacturing the same and display apparatus
KR20060114744A (en) Tft array panel and liquid crystal display having the same
CN102456696A (en) Display device and method for manufacturing the same
KR101799048B1 (en) Thin film transistor array panel and manufacturing method thereof
CN111668242A (en) OLED display panel and preparation method thereof
TWI651574B (en) Display panel and method of manufacturing same
KR101006436B1 (en) Thin film transistor array panel for display device
KR101006435B1 (en) exposure mask and method for manufacturing a panel for a display device using the mask
US10068924B2 (en) Display panel and display apparatus
CN107452748B (en) Element substrate and display device
CN113467145B (en) Array substrate, manufacturing method and display panel
CN111627936B (en) Array substrate, preparation method thereof and remote touch liquid crystal display device
US20230253416A1 (en) Display device
US9459505B2 (en) Display device and manufacturing method thereof
WO2020258478A1 (en) Pixel electrode, array substrate and display device
CN117525083A (en) Array substrate and display panel
US20140027761A1 (en) Thin film transistor substrate, display thereof and manufacturing method thereof
CN114236931B (en) Array substrate, manufacturing method and display panel
WO2024065111A1 (en) Array substrate and manufacturing method therefor, and display panel
CN116224666A (en) Array substrate, preparation method thereof, display panel and display device
KR102142477B1 (en) Array substrate and method of fabricating the same
CN1275303C (en) Method for reducing leakage current on surface of base plate in thin film transistor

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination