CN111627903B - Programmable overvoltage protection device with U-MOSFET and thyristor - Google Patents

Programmable overvoltage protection device with U-MOSFET and thyristor Download PDF

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CN111627903B
CN111627903B CN202010500408.0A CN202010500408A CN111627903B CN 111627903 B CN111627903 B CN 111627903B CN 202010500408 A CN202010500408 A CN 202010500408A CN 111627903 B CN111627903 B CN 111627903B
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mosfet
region
thyristor
heavily doped
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CN111627903A (en
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李泽宏
何云娇
王志明
程然
王彤阳
莫家宁
蒲小庆
任敏
张金平
高巍
张波
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University of Electronic Science and Technology of China
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0259—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using bipolar transistors as protective elements
    • H01L27/0262—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using bipolar transistors as protective elements including a PNP transistor and a NPN transistor, wherein each of said transistors has its base coupled to the collector of the other transistor, e.g. silicon controlled rectifier [SCR] devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0266—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0296—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices involving a specific disposition of the protective devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Thyristors (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

The invention relates to a programmable overvoltage protection device with a U-MOSFET and a thyristor, belonging to the technical field of power semiconductors. The programmable overvoltage protection device utilizes two U-MOSFETs to respectively provide independent control for two NPNP thyristors, and the grid end of the U-MOSFET is connected with negative power supply voltage; or two U-MOSFETs are used for respectively providing independent control for the two PNPN thyristors, the grid end of the U-MOSFET is connected with a positive power supply voltage, and when a negative voltage on a telephone line is lower than the power supply voltage by a threshold voltage or a positive voltage is higher than the power supply voltage by a threshold voltage, the device is started and conducts an overvoltage generated by surge on a transmission line to the ground, so that unidirectional programmable protection of a subscriber line interface circuit is realized. The U-MOSFET groove gate structure reduces the device on-resistance, is a unipolar device, has lower power consumption and higher temperature stability, has higher switching speed to enable the device to have faster surge response, and is compatible with the thyristor process and easy to integrate.

Description

Programmable overvoltage protection device with U-MOSFET and thyristor
Technical Field
The invention belongs to the technical field of power semiconductors, and particularly relates to a programmable overvoltage protection device with a U-MOSFET and a thyristor.
Background
Modern electronic communication technology is rapidly developed, transmission speed and transmission efficiency are continuously increased, and meanwhile, requirements of electronic equipment and a whole system on external voltage are higher and higher. Both voltage transient and surge current can cause misoperation and even damage to communication equipment and a whole system, so that a surge protection device is required to protect the communication equipment and the whole system. After the communication equipment lightning-strike-resistant surge standard is issued in succession in European and American countries, the technical requirements of lightning strike prevention of the telecommunication terminal equipment and the experimental method YD/T9931998 of the communication industry standard of the people's republic of China are issued in 1998.
Typical voltage limiting type protection devices are a voltage dependent resistor and a transient voltage suppressor. A Voltage Dependent Resistor (varistor) is a non-linear element sensitive to Voltage, and when an overvoltage occurs in a circuit, the varistor firstly bears the external overvoltage and clamps the Voltage at a safer level. When the Transient Voltage Suppressor (Transient Voltage Suppressor) bears surge Voltage, the Transient Voltage Suppressor is in an avalanche breakdown state, impedance is rapidly reduced, surge current is discharged to the ground, and the Voltage is clamped at a preset level. Typical voltage switching type protection devices are gas discharge tubes and thyristors. Two or more electrodes are provided in a Gas Discharge Tube (Gas Discharge Tube) and filled with a certain amount of inert Gas. When high voltage is applied to the two electrodes, gas in the tube can be ionized, the resistance is small, and the gas discharge tube enters a conducting state to realize the discharge of surge energy. A Thyristor (Thyristor), also called Silicon Controlled Rectifier (Silicon Controlled Rectifier), can be switched from a forward blocking state to a forward conducting state under the action of a gate trigger current, and discharges a surge current, and has a relatively low conducting voltage drop in the forward conducting state. In recent years, thyristors gradually replace voltage limiting type protection devices and gas discharge tubes due to long service life, good stability, low price, strong surge discharge capacity and shorter response time.
In communication systems, particularly telephone systems, signals are typically transmitted between subscriber stations and a central switching office over a two-wire two-way communication channel. In long-distance transmission, the working power supply of a Subscriber Line Interface Circuit (SLIC) needs to be increased, so that voltage programmable following protection needs to be carried out on the subscriber line interface circuit. The existing programmable one-way anti-surge protection structure of a semiconductor is based on the principle of a four-layer thyristor structure, and can realize one-way following protection, two independent NPN control triodes are respectively connected with two NPNP thyristors to provide negative surge protection, and two independent PNP control triodes are respectively connected with two PNPN thyristors to provide positive surge protection. However, the structure also has a certain problem, and the triode is a bipolar device, so that the switching speed is slow, the frequency is low, the on-resistance is large, the power consumption is high, the temperature influence on the current amplification factor beta is large, and the overall protection device has the poor characteristics of slow response speed, poor temperature characteristic, large power consumption and the like.
Disclosure of Invention
The invention aims to solve the technical problem in the prior art and provides a programmable overvoltage protection device with a U-MOSFET and a thyristor.
In order to solve the above technical problem, an embodiment of the present invention provides a programmable overvoltage protection device having a U-MOSFET and a thyristor, including a first U-MOSFET, a first NPNP thyristor, a second U-MOSFET, and a second NPNP thyristor, wherein a source of the first U-MOSFET is connected to a P-type gate of the first NPNP thyristor, and a drain of the first U-MOSFET is connected to an anode of the first NPNP thyristor; the source electrode of the second U-MOSFET is connected with the P-type grid electrode of the second NPNP thyristor, and the drain electrode of the second U-MOSFET is connected with the anode electrode of the second NPNP thyristor;
the grid electrode of the first U-MOSFET and the grid electrode of the second U-MOSFET are connected in parallel and connected with a negative power supply voltage; the drain electrode of the first U-MOSFET, the anode electrode of the first NPNP thyristor, the drain electrode of the second U-MOSFET and the anode electrode of the second NPNP thyristor are connected to the ground in common; the cathode of the first NPNP thyristor is connected with a first transmission telephone line, and the cathode of the second NPNP thyristor is connected with a second transmission telephone line.
On the basis of the technical scheme, the invention can be improved as follows.
Further, forming a first NPNP thyristor, a first U-MOSFET, a second U-MOSFET and a second NPNP thyristor on the N-type silicon single crystal; the second U-MOSFET and the second NPNP thyristor are arranged symmetrically to the first U-MOSFET and the first NPNP thyristor.
Furthermore, the cellular structure of the first NPNP thyristor comprises a first back metal, a first N-type base region and a front metal structure which are sequentially stacked from bottom to top, wherein the first N-type base region is an N-type silicon single crystal;
the bottom layer of the first N-type base region is sequentially provided with a heavily doped P-type anode contact region and a first P-type anode in a stacked mode from bottom to top, and the heavily doped P-type anode contact region is located on the upper surface of the first back metal;
the top layer of the first N-type base region is provided with a P-type isolation region, a first P-type base region and a heavily doped N-type region, the heavily doped N-type region is positioned at two sides of the first P-type base region at intervals, the P-type isolation region is positioned at one side of the heavily doped N-type region, which is far away from the first P-type base region, and is positioned on the upper surface of the first P-type anode, and the top layer of the P-type isolation region is provided with a heavily doped P-type isolation region;
a plurality of first N-type cathodes are arranged at intervals on the top layer of the first P-type base region, and gaps among the first N-type cathodes are cathode short-circuit holes formed in the first P-type base region;
the front metal structure comprises a cathode electrode and a first front electrode, the cathode electrode is positioned on the first N-type cathode and the cathode short circuit hole, and the first front electrode is positioned on the first P-type base region and used as a base electrode of the first NPNP thyristor.
Furthermore, the cellular structure of the first U-MOSFET comprises a first back metal, an N-type substrate and a first front electrode which are sequentially stacked from bottom to top; the N-type substrate is an N-type silicon single crystal;
the bottom layer of the N-type substrate is provided with a heavily doped N-type drain contact region, the heavily doped N-type drain contact region is positioned on the upper surface of the first back metal, and one side of the heavily doped N-type drain contact region is in contact with one side of the heavily doped P-type anode contact region;
the top layer of the N-type substrate is provided with a P-type body region and a first gate oxide layer, wherein the side surfaces of the P-type body region and the first gate oxide layer are mutually contacted; the top layer of the P-type body region is provided with a heavily doped P-type contact region and a heavily doped N-type source region, the side surfaces of which are mutually contacted, and one side of the heavily doped N-type source region is contacted with one side of the first gate oxide layer; the first gate oxide layer is provided with a first polysilicon gate electrode;
the first front electrode is positioned on the heavily doped P-type contact region and the heavily doped N-type source region and used as a source electrode of the first U-MOSFET.
Furthermore, a first front electrode of the first NPNP thyristor is connected with a first front electrode of the first U-MOSFET, a second front electrode of the second U-MOSFET is connected with a second front electrode of the second NPNP thyristor, and first back metal of the first NPNP thyristor and first back metal of the second NPNP thyristor are connected with first back metal of the first U-MOSFET and the second back metal of the second U-MOSFET.
In order to solve the above technical problem, an embodiment of the present invention provides a programmable overvoltage protection device having a U-MOSFET and a thyristor, including a third U-MOSFET, a first PNPN thyristor, a fourth U-MOSFET and a second PNPN thyristor, where a source of the third U-MOSFET is connected to an N-type gate of the first PNPN thyristor, and a drain of the third U-MOSFET is connected to a cathode of the first PNPN thyristor; the source electrode of the fourth U-MOSFET is connected with the N-type grid electrode of the second PNPN thyristor, and the drain electrode of the fourth U-MOSFET is connected with the cathode electrode of the second PNPN thyristor;
the grid electrode of the third U-MOSFET and the grid electrode of the fourth U-MOSFET are connected and connected with a positive power voltage; the drain electrode of the third U-MOSFET, the cathode of the first PNPN thyristor, the drain electrode of the fourth U-MOSFET and the cathode of the second PNPN thyristor are grounded together; the anode of the first PNPN thyristor is connected with a first transmission telephone line, and the anode of the second PNPN thyristor is connected with a second transmission telephone line.
On the basis of the technical scheme, the invention can be further improved as follows.
Further, a first PNPN thyristor, a third U-MOSFET, a fourth U-MOSFET and a second PNPN thyristor are formed on the P-type silicon single crystal; the fourth U-MOSFET and the second PNPN thyristor are symmetrically arranged with the third U-MOSFET and the first PNPN thyristor.
Further, the cellular structure of the first PNPN thyristor comprises a second back metal, a second P-type base region and a front metal structure which are sequentially stacked from bottom to top, wherein the second P-type base region is a P-type silicon single crystal;
the bottom layer of the second P-type base region is sequentially provided with a heavily doped N-type cathode contact region and a second N-type cathode in a laminated mode from bottom to top, and the heavily doped N-type cathode contact region is located on the upper surface of the second back metal;
the top layer of the second P-type base region is provided with an N-type isolation region, a second N-type base region and a heavily doped P-type region, the heavily doped P-type region is positioned at two sides of the second N-type base region at intervals, the N-type isolation region is positioned at one side of the heavily doped P-type region, which is far away from the second N-type base region, and is positioned on the upper surface of the second N-type cathode, and the top layer of the N-type isolation region is provided with a heavily doped N-type isolation region;
a plurality of second P-type anodes are arranged at intervals on the top layer of the second N-type base region, and gaps among the second P-type anodes are anode short circuit holes formed in the second N-type base region;
the front metal structure comprises an anode electrode and a third front electrode, the anode electrode is positioned on the second P-type anode and the anode short circuit hole, and the third front electrode is positioned on the second N-type base region and used as a base electrode of the first PNPN thyristor.
Furthermore, the cell structure of the third U-MOSFET includes a second back metal, a P-type substrate, and a third front electrode, which are sequentially stacked from bottom to top; the P-type substrate is a P-type silicon single crystal;
the bottom layer of the P-type substrate is provided with a heavily doped P-type drain contact region, the heavily doped P-type drain contact region is positioned on the upper surface of the second back metal, and one side of the heavily doped P-type drain contact region is in contact with one side of the heavily doped N-type cathode contact region;
the top layer of the P-type substrate is provided with an N-type body region and a second gate oxide layer, the side surfaces of which are mutually contacted; the top layer of the N-type body region is provided with a heavily doped N-type contact region and a heavily doped P-type source region, the side surfaces of which are mutually contacted, and one side of the heavily doped P-type source region is contacted with one side of the second gate oxide layer; the second gate oxide layer is provided with a second polysilicon gate electrode;
and the third front electrode is positioned on the heavily doped N-type contact region and the heavily doped P-type source region and is used as a source electrode of the third U-MOSFET.
Furthermore, a third front electrode of the first PNPN thyristor is connected with a third front electrode of the third U-MOSFET, a fourth front electrode of the fourth U-MOSFET is connected with a fourth front electrode of the second PNPN thyristor, and second back metals of the first PNPN thyristor and the second PNPN thyristor are connected with second back metals of the third U-MOSFET and the fourth U-MOSFET.
The invention has the beneficial effects that: the invention provides a programmable overvoltage protection device with U-MOSFETs and thyristors, which utilizes the two U-MOSFETs to respectively provide independent control for two NPNP thyristors, and the grid end of the U-MOSFETs is connected with a negative power supply voltage; or the two U-MOSFETs respectively provide independent control for the two PNPN thyristors, the grid end of the U-MOSFET is connected with a positive power supply voltage, and when a negative voltage on a telephone line is lower than the power supply voltage by a threshold voltage or a positive voltage is higher than the power supply voltage by a threshold voltage, the device is started and conducts an overvoltage generated by surge on a transmission line to the ground, so that unidirectional programmable protection of a subscriber line interface circuit is realized. The U-MOSFET groove gate structure reduces the device on-resistance, is a unipolar device, has lower power consumption and higher temperature stability, has higher switching speed to enable the device to have faster surge response, and is compatible with the thyristor process and easy to integrate.
Drawings
Fig. 1A is a schematic diagram of a programmable overvoltage protection device having a U-MOSFET and a thyristor according to a first embodiment of the present invention;
FIG. 1B is a schematic diagram of a programmable overvoltage protection device having a U-MOSFET and a thyristor according to a second embodiment of the present invention;
fig. 2A is a schematic cross-sectional view of a programmable overvoltage protection device having a U-MOSFET and a thyristor according to a first embodiment of the present invention;
fig. 2B is a schematic cross-sectional view of a programmable overvoltage protection device having a U-MOSFET and a thyristor according to a second embodiment of the present invention;
fig. 3A is an output characteristic of a programmable overvoltage protection device having a U-MOSFET and a thyristor according to a first embodiment of the present invention;
fig. 3B is an output characteristic of a programmable overvoltage protection device having a U-MOSFET and a thyristor according to a second embodiment of the invention.
In the drawings, the components represented by the respective reference numerals are listed below:
4. a first N-type base region, 5, a first P-type anode, 6, a heavily doped P-type anode contact region, 7, a P-type isolation region, 8, a heavily doped P-type isolation region, 9, a first P-type base region, 10, a heavily doped N-type region, 11, a first N-type cathode, 12, a cathode short hole, 13, an N-type substrate, 14, a heavily doped N-type drain contact region, 15, a heavily doped P-type contact region, 16, a P-type body region, 17, a heavily doped N-type source region, 18, a first front electrode, 19, a first gate oxide layer, 20, a first polysilicon gate electrode, 21, a first back metal, 22, a cathode electrode, 23, a first oxide layer, 24, a first U-MOSFET, 25, a second U-MOSFET, 26, a first NPNP thyristor, 27, a second NPNP thyristor, 34, a second P-type base region, 35, a second N-type cathode, 36, a heavily doped N-type cathode contact region, 37, a heavily doped P-type isolation region, a heavily doped P-type contact region, a second P-type contact region, a second P-type P-MOSFET, a second P-type P-, An N-type isolation region 38, a heavily doped N-type isolation region 39, a second N-type base region 40, a heavily doped P-type region 41, a second P-type anode 42, an anode short circuit hole 43, a P-type substrate 44, a heavily doped P-type drain contact region 45, a heavily doped N-type contact region 46, an N-type body region 47, a heavily doped P-type source region 48, a third front electrode 49, a second gate oxide layer 50, a second polysilicon gate electrode 51, a second back metal 52, an anode electrode 53, a second oxide layer 54, a third U-MOSFET55, a fourth U-MOSFET 56, a first PNPN thyristor 57 and a second PNPN thyristor.
Detailed Description
The principles and features of this invention are described below in conjunction with the following drawings, which are set forth to illustrate, but are not to be construed to limit the scope of the invention.
As shown in fig. 1A, a first embodiment of the present invention provides a programmable overvoltage protection device having U-MOSFETs and thyristors, including a first U-MOSFET24, a first NPNP thyristor 26, a second U-MOSFET25 and a second NPNP thyristor 27, wherein the source of the first U-MOSFET24 is connected to the P-type gate of the first NPNP thyristor 26, and the drain of the first U-MOSFET24 is connected to the anode of the first NPNP thyristor 25; the source of the second U-MOSFET25 is connected with the P-type gate of the second NPNP thyristor 27, and the drain of the second U-MOSFET25 is connected with the anode of the second NPNP thyristor 27;
the gate of the first U-MOSFET24 and the gate of the second U-MOSFET25 are connected and connected to a negative supply voltage; the drain of the first U-MOSFET24, the anode of the first NPNP thyristor 26, the drain of the second U-MOSFET25, and the anode of the second NPNP thyristor 27 are commonly grounded; the cathode of the first NPNP thyristor 26 is connected to the first transmission telephone line and the cathode of the second NPNP thyristor 27 is connected to the second transmission telephone line.
The working principle of the first embodiment of the invention is as follows:
in a programmable negative overvoltage protection device having U-MOSFETs and thyristors according to a first embodiment of the present invention, cathodes of two NPNP thyristors are respectively connected to a first transmission telephone Line1 and a second transmission telephone Line2, anodes of the two NPNP thyristors and a drain of the U-MOSFET are connected to ground, two sources of the U-MOSFET are respectively connected to gates of the two NPNP thyristors, and a gate of the U-MOSFET is connected to a negative power supply voltage.
The output characteristic curve of the programmable negative overvoltage protection device with the U-MOSFET and the thyristor is shown in figure 3A, the device realizes negative overvoltage protection and works in a third quadrant, when the voltage range on Line is between the ground and negative power supply voltage, the NPNP thyristor is in a positive blocking state, the source potential of the U-MOSFET is higher than that of a grid, no depletion region exists below the grid, no channel is generated, the U-MOSFET is not started, the overvoltage protection device does not work, and at the moment, leakage current flows through the device; when the voltage on the Line is lower than the negative power voltage, the source potential of the U-MOSFET is lower than the grid, a depletion region is generated under the grid, when the voltage difference between the grid and the source is larger than the threshold voltage, a channel is generated, the U-MOSFET is started and works in a saturation region, current flows from the drain to the source to serve as grid trigger current of the NPNP thyristor, and the trigger thyristor is turned over by positive blockingEntering a forward conduction state, and releasing surge current to the ground to realize the protection of a subsequent circuit on Line, wherein V in the figureBOIs a breakover voltage, the corresponding current is a breakover current, and the minimum current entering and maintaining the forward conduction is a maintaining current IHThe corresponding voltage is a sustain voltage VH. When the voltage on the Line is changed into positive voltage, the NPNP thyristor is in a reverse blocking state, a PN junction formed by the P-type body region 16 in the U-MOSFET and the N-type substrate 13 is in forward bias, and current flows from the source to the drain to realize voltage clamping.
Alternatively, as shown in fig. 2A, the first NPNP thyristor 26, the first U-MOSFET24, the second U-MOSFET25, and the second NPNP thyristor 27 are formed on an N-type silicon single crystal; the second U-MOSFET25 and the second NPNP thyristor 27 are arranged symmetrically to the first U-MOSFET24 and the first NPNP thyristor 26.
Optionally, as shown in fig. 2A, the cell structure of the first NPNP thyristor 26 includes a first back metal 21, a first N-type base region 4, and a front metal structure, which are stacked in sequence from bottom to top, where the first N-type base region 4 is an N-type silicon single crystal;
the bottom layer of the first N-type base region 4 is sequentially provided with a heavily doped P-type anode contact region 6 and a first P-type anode 5 in a stacking mode from bottom to top, and the heavily doped P-type anode contact region 6 is located on the upper surface of the first back metal 21;
a P-type isolation region 7, a first P-type base region 9 and a heavily doped N-type region 10 are arranged in the top layer of the first N-type base region 4, the heavily doped N-type regions 10 are positioned at two sides of the first P-type base region 9 at intervals, the P-type isolation region 7 is positioned at one side, away from the first P-type base region 9, of the heavily doped N-type region 10 at intervals and positioned on the upper surface of the first P-type anode 5, and a heavily doped P-type isolation region 8 is arranged in the top layer of the P-type isolation region 7;
a plurality of first N-type cathodes 11 are arranged at the top layer of the first P-type base region 9 at intervals, and gaps among the plurality of first N-type cathodes 11 are cathode short circuit holes 12 formed in the first P-type base region 9;
the front-side metal structure comprises a cathode electrode 22 and a first front-side electrode 18, wherein the cathode electrode 22 is positioned on the first N-type cathode 11 and the cathode short-circuit hole 12, and the first front-side electrode 18 is positioned on the first P-type base region 9 and is used as a base electrode of the first NPNP thyristor 26.
In the above embodiment, the first back metal 21 in the first NPNP thyristor 26 serves as an anode. Wherein the front metal structures are separated from each other by a first oxide layer 23.
Alternatively, as shown in fig. 2A, the cell structure of the first U-MOSFET24 includes a first back metal 21, an N-type substrate 13, and a first front electrode 18, which are stacked in this order from bottom to top; the N-type substrate 13 is an N-type silicon single crystal;
wherein, the bottom layer of the N-type substrate 13 is provided with a heavily doped N-type drain contact region 14, the heavily doped N-type drain contact region 14 is located on the upper surface of the first back metal 21, and one side of the heavily doped N-type drain contact region 14 is in contact with one side of the heavily doped P-type anode contact region 6;
the top layer of the N-type substrate 13 is provided with a P-type body region 16 and a first gate oxide layer 19, the side surfaces of which are mutually contacted; the P-type body region 16 is arranged close to one side of the P-type isolation region 7, the first gate oxide layer 19 is arranged far away from one side of the P-type isolation region 7, the top layer of the P-type body region 16 is provided with a heavily doped P-type contact region 15 and a heavily doped N-type source region 17, the side surfaces of the heavily doped P-type contact region and the side surfaces of the heavily doped N-type source region are mutually contacted, and one side of the heavily doped N-type source region 17 is contacted with one side of the first gate oxide layer 19; the first gate oxide layer 19 has a first polysilicon gate electrode 20 therein;
a first front electrode 18 is located over the heavily doped P-type contact region 15 and the heavily doped N-type source region 17 for serving as the source of the first U-MOSFET 24.
In the above embodiment, the first back side metal 21 in the first U-MOSFET24 serves as the drain. The first front electrode 18 is separated from the other front electrodes by a first oxide layer 23.
Alternatively, as shown in fig. 2A, the first front electrode 18 of the first NPNP thyristor 26 is connected to the first front electrode 18 of the first U-MOSFET24, the second front electrode of the second U-MOSFET25 is connected to the second front electrode of the second NPNP thyristor 27, and the first back metal 21 of the first and second NPNP thyristors 26, 27 is connected to the first back metal 21 of the first and second U-MOSFETs 24, 25.
As shown in fig. 1B, a second embodiment of the present invention provides a programmable overvoltage protection device having U-MOSFETs and thyristors, which includes a third U-MOSFET54, a first PNPN thyristor 56, a fourth U-MOSFET55, and a second PNPN thyristor 57, wherein a source of the third U-MOSFET54 is connected to an N-type gate of the first PNPN thyristor 56, and a drain of the third U-MOSFET54 is connected to a cathode of the first PNPN thyristor 55; the source electrode of the fourth U-MOSFET55 is connected with the N-type grid electrode of the second PNPN thyristor 57, and the drain electrode of the fourth U-MOSFET55 is connected with the cathode electrode of the second PNPN thyristor 57;
the gate of the third U-MOSFET54 and the gate of the fourth U-MOSFET55 are connected and connected to the positive supply voltage; the drain of the third U-MOSFET54, the cathode of the first PNPN thyristor 56, the drain of the fourth U-MOSFET55 and the cathode of the second PNPN thyristor 57 are commonly grounded; the anode of the first PNPN thyristor 56 is connected to the first transmission telephone line, and the anode of the second PNPN thyristor 57 is connected to the second transmission telephone line.
The working principle of the second embodiment of the invention is as follows:
in a programmable forward overvoltage protection device having U-MOSFETs and thyristors according to a second embodiment of the present invention, anodes of two PNPN thyristors are respectively connected to a first transmission telephone Line1 and a second transmission telephone Line2, cathodes of the two PNPN thyristors and a drain of the U-MOSFET are connected to ground, two sources of the U-MOSFET are respectively connected to N-type gates of the two PNPN thyristors, and a gate of the U-MOSFET is connected to a positive power supply voltage.
The output characteristic curve of the programmable forward overvoltage protection device with the U-MOSFET and the thyristor is shown in FIG. 3B, the device realizes forward overvoltage protection and works in a first quadrant, when the voltage range on Line is between the ground and the positive power supply voltage, the PNPN thyristor is in a forward blocking state, the potential of the source electrode of the U-MOSFET is lower than that of the grid electrode, no depletion region exists below the grid electrode, no channel is generated, the U-MOSFET is not started, the overvoltage protection device does not work, and at the moment, leakage current flows through the device; when the voltage on the Line is higher than the positive power supply voltage, the source potential of the U-MOSFET is higher than the grid, a depletion region is generated under the grid, when the voltage difference between the grid and the source is larger than the threshold voltage, a channel is generated, the U-MOSFET is started and works in a saturation region, current flows from the source to the drain to serve as grid trigger current of the PNPN thyristor, and the trigger thyristor is converted into the PNPN thyristor from positive blockingEnters a forward conduction state, and discharges surge current to the ground to realize the protection of a subsequent circuit on the Line, wherein V in the figureBOIs a breakover voltage, the corresponding current is a breakover current, and the minimum current entering and maintaining the forward conduction is a maintaining current IHThe corresponding voltage is a sustain voltage VH. When the voltage on Line becomes negative voltage, the PNPN thyristor is in a reverse blocking state, the PN junction formed by the N-type body region 46 in the U-MOSFET and the P-type substrate 43 is in forward bias, and current flows from the drain to the source to realize voltage clamping.
Alternatively, as shown in FIG. 2B, a first PNPN thyristor 56, a third U-MOSFET54, a fourth U-MOSFET55 and a second PNPN thyristor 57 are formed on a P-type silicon single crystal; the fourth U-MOSFET55 and the second PNPN thyristor 57 are arranged symmetrically to the third U-MOSFET54 and the first PNPN thyristor 56.
In the above embodiment, the P-type silicon single crystal is preferably a P-type lightly doped silicon single crystal.
Optionally, as shown in fig. 2B, the cell structure of the first PNPN thyristor 56 includes a second back metal 51, a second P-type base region 34, and a front metal structure, which are sequentially stacked from bottom to top, where the second P-type base region 34 is a P-type silicon single crystal;
the bottom layer of the second P-type base region 34 is sequentially provided with a heavily doped N-type cathode contact region 36 and a second N-type cathode 35 in a stacked manner from bottom to top, and the heavily doped N-type cathode contact region 36 is located on the upper surface of the second back metal 51;
an N-type isolation region 37, a second N-type base region 39 and a heavily doped P-type region 40 are arranged in the top layer of the second P-type base region 34, the heavily doped P-type regions 40 are positioned at two sides of the second N-type base region 39 at intervals, the N-type isolation region 37 is positioned at one side of the heavily doped P-type region 40 far away from the second N-type base region 39 at intervals and positioned on the upper surface of the second N-type cathode 35, and a heavily doped N-type isolation region 38 is arranged in the top layer of the N-type isolation region 37;
a plurality of second P-type anodes 41 are arranged at intervals on the top layer of the second N-type base region 39, and gaps among the plurality of second P-type anodes 41 are anode short-circuit holes 42 formed in the second N-type base region 39;
the front metal structure comprises an anode electrode 52 and a third front electrode 48, wherein the anode electrode 52 is positioned on the second P-type anode 41 and the anode short-circuit hole 42, and the third front electrode 48 is positioned on the second N-type base region 39 and is used as a base electrode of the first PNPN thyristor 56.
In the above embodiment, the second back metal 51 in the first PNPN thyristor 56 serves as a cathode. Wherein the front side metal structures are separated from each other by the second oxide layer 53.
Optionally, as shown in fig. 2B, the cell structure of the third U-MOSFET54 includes a second back metal 51, a P-type substrate 43, and a third front electrode 48, which are stacked in sequence from bottom to top; the P-type substrate 43 is a P-type silicon single crystal;
wherein, the bottom layer of the P-type substrate 43 is provided with a heavily doped P-type drain contact region 44, the heavily doped P-type drain contact region 44 is located on the upper surface of the second back metal 51, and one side of the heavily doped P-type drain contact region 44 is in contact with one side of the heavily doped N-type cathode contact region 36;
the top layer of the P-type substrate 43 is provided with an N-type body region 46 and a second gate oxide layer 49 which are laterally contacted with each other; the N-type body region 46 is arranged close to one side of the N-type isolation region 37, the second gate oxide layer 49 is arranged far away from one side of the N-type isolation region 37, the top layer of the N-type body region 46 is provided with a heavily doped N-type contact region 45 and a heavily doped P-type source region 47, the side surfaces of which are mutually contacted, and one side of the heavily doped P-type source region 47 is contacted with one side of the second gate oxide layer 49; the second gate oxide layer 49 is provided with a second polysilicon gate electrode 50;
a third front electrode 48 is located over heavily doped N-type contact region 45 and heavily doped P-type source region 47 for serving as the source of a third U-MOSFET 54.
In the above embodiment, the second back side metal 51 in the third U-MOSFET54 serves as the drain. Wherein the third front electrode 48 is separated from the other front electrodes by a second oxide layer 53.
Alternatively, as shown in fig. 2B, the third front electrode 48 of the first PNPN thyristor 56 is connected to the third front electrode 48 of the third U-MOSFET54, the fourth front electrode of the fourth U-MOSFET55 is connected to the fourth front electrode of the second PNPN thyristor 57, and the second back metal 51 of the first and second PNPN thyristors 56, 57 is connected to the second back metal 51 of the third and fourth U-MOSFETs 54, 55.
The invention relates to a programmable overvoltage protection device with U-MOSFETs and thyristors, which utilizes the two U-MOSFETs to respectively provide independent control for two NPNP thyristors, and the grid end of the U-MOSFETs is connected with a negative power supply voltage; or the two U-MOSFETs respectively provide independent control for the two PNPN thyristors, the grid end of the U-MOSFET is connected with a positive power supply voltage, and when a negative voltage on a telephone line is lower than the power supply voltage by a threshold voltage or a positive voltage is higher than the power supply voltage by a threshold voltage, the device is started and conducts an overvoltage generated by surge on a transmission line to the ground, so that unidirectional programmable protection of a subscriber line interface circuit is realized. The U-MOSFET groove gate structure reduces the device on-resistance, is a unipolar device, has lower power consumption and higher temperature stability, has higher switching speed to enable the device to have faster surge response, and is compatible with the thyristor process and easy to integrate.
In the description of the present invention, it is to be understood that the terms "central," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," "axial," "radial," "circumferential," and the like are used in the orientations and positional relationships indicated in the drawings for convenience in describing the invention and to simplify the description, and are not intended to indicate or imply that the referenced devices or elements must have a particular orientation, be constructed and operated in a particular orientation, and are therefore not to be considered limiting of the invention.
Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. In the description of the present invention, "a plurality" means at least two, e.g., two, three, etc., unless specifically limited otherwise.
In the present invention, unless otherwise explicitly stated or limited, the terms "mounted," "connected," "fixed," and the like are to be construed broadly, e.g., as being permanently connected, detachably connected, or integral; can be mechanically or electrically connected; they may be directly connected or indirectly connected through intervening media, or they may be connected internally or in any other suitable relationship, unless expressly stated otherwise. The specific meanings of the above terms in the present invention can be understood by those skilled in the art according to specific situations.
In the present invention, unless otherwise expressly stated or limited, the first feature "on" or "under" the second feature may be directly contacting the first and second features or indirectly contacting the first and second features through an intermediate. Also, a first feature "on," "above," and "over" a second feature may be directly on or obliquely above the second feature, or simply mean that the first feature is at a higher level than the second feature. A first feature being "under," "below," and "beneath" a second feature may be directly under or obliquely under the first feature, or may simply mean that the first feature is at a lesser elevation than the second feature.
In the description herein, references to the description of the term "one embodiment," "some embodiments," "an example," "a specific example," or "some examples," etc., mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, the schematic representations of the terms used above are not necessarily intended to refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, various embodiments or examples and features of different embodiments or examples described in this specification can be combined and combined by one skilled in the art without contradiction.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents, improvements and the like that fall within the spirit and principle of the present invention are intended to be included therein.

Claims (10)

1. A programmable overvoltage protection device with U-MOSFETs and thyristors comprises a first U-MOSFET (24), a first NPNP thyristor (26), a second U-MOSFET (25) and a second NPNP thyristor (27), wherein the source of the first U-MOSFET (24) is connected with the P-type grid of the first NPNP thyristor (26), and the drain of the first U-MOSFET (24) is connected with the anode of the first NPNP thyristor (25); the source of the second U-MOSFET (25) is connected with the P-type grid of the second NPNP thyristor (27), and the drain of the second U-MOSFET (25) is connected with the anode of the second NPNP thyristor (27);
characterized in that the gate of the first U-MOSFET (24) and the gate of the second U-MOSFET (25) are connected and connected to a negative supply voltage; the drain electrode of the first U-MOSFET (24), the anode electrode of the first NPNP thyristor (26), the drain electrode of the second U-MOSFET (25) and the anode electrode of the second NPNP thyristor (27) are connected to the ground in common; the cathode of the first NPNP thyristor (26) is connected with a first transmission telephone line, and the cathode of the second NPNP thyristor (27) is connected with a second transmission telephone line.
2. A programmable overvoltage protection device with U-MOSFET and thyristor according to claim 1 characterized in that the first NPNP thyristor (26), the first U-MOSFET (24), the second U-MOSFET (25) and the second NPNP thyristor (27) are formed on N-type silicon single crystal; the second U-MOSFET (25) and the second NPNP thyristor (27) are arranged symmetrically to the first U-MOSFET (24) and the first NPNP thyristor (26).
3. The programmable overvoltage protection device with the U-MOSFET and the thyristor according to claim 1, wherein the cell structure of the first NPNP thyristor (26) comprises a first back metal (21), a first N-type base region (4) and a front metal structure which are sequentially stacked from bottom to top, the first N-type base region (4) is an N-type silicon single crystal;
the bottom layer of the first N-type base region (4) is sequentially provided with a heavily doped P-type anode contact region (6) and a first P-type anode (5) in a stacking mode from bottom to top, and the heavily doped P-type anode contact region (6) is located on the upper surface of the first back metal (21);
a P-type isolation region (7), a first P-type base region (9) and a heavily doped N-type region (10) are arranged in the top layer of the first N-type base region (4), the heavily doped N-type regions (10) are positioned on two sides of the first P-type base region (9) at intervals, the P-type isolation region (7) is positioned on one side, away from the first P-type base region (9), of the heavily doped N-type region (10) at intervals and positioned on the upper surface of the first P-type anode (5), and a heavily doped P-type isolation region (8) is arranged in the top layer of the P-type isolation region (7);
a plurality of first N-type cathodes (11) are arranged at the top layer of the first P-type base region (9) at intervals, and gaps among the first N-type cathodes (11) are cathode short-circuit holes (12) formed in the first P-type base region (9);
the front-side metal structure comprises a cathode electrode (22) and a first front-side electrode (18), wherein the cathode electrode (22) is positioned on the first N-type cathode (11) and the cathode short-circuit hole (12), and the first front-side electrode (18) is positioned on the first P-type base region (9) and is used as a base electrode of the first NPNP thyristor (26).
4. A programmable overvoltage protection device with U-MOSFET and thyristor according to claim 3 characterized in that the cell structure of the first U-MOSFET (24) comprises a first back metal (21), an N-type substrate (13) and a first front electrode (18) stacked in sequence from bottom to top; the N-type substrate (13) is an N-type silicon single crystal;
the bottom layer of the N-type substrate (13) is provided with a heavily doped N-type drain contact region (14), the heavily doped N-type drain contact region (14) is positioned on the upper surface of the first back metal (21), and one side of the heavily doped N-type drain contact region is in contact with one side of the heavily doped P-type anode contact region (6);
the top layer of the N-type substrate (13) is provided with a P-type body region (16) and a first gate oxide layer (19) which are contacted with each other at the side surfaces; the P-type body region (16) is arranged close to one side of the P-type isolation region (7), the first gate oxide layer (19) is arranged far away from one side of the P-type isolation region (7), the top layer of the P-type body region (16) is provided with a heavily doped P-type contact region (15) and a heavily doped N-type source region (17) of which the side surfaces are mutually contacted, and one side of the heavily doped N-type source region (17) is contacted with one side of the first gate oxide layer (19); the first gate oxide layer (19) is provided with a first polysilicon gate electrode (20);
a first front electrode (18) is located on the heavily doped P-type contact region (15) and the heavily doped N-type source region (17) for serving as a source of a first U-MOSFET (24).
5. A programmable overvoltage protection device with U-MOSFETs and thyristors according to claim 4 characterised in that the first front side electrode (18) of the first NPNP thyristor (26) is connected to the first front side electrode (18) of the first U-MOSFET (24), the second front side electrode of the second U-MOSFET (25) is connected to the second front side electrode of the second NPNP thyristor (27), and the first back side metal (21) of the first and second NPNP thyristors (26, 27) is connected to the first back side metal (21) of the first and second U-MOSFETs (24, 25).
6. A programmable overvoltage protection device with U-MOSFETs and thyristors, comprising a third U-MOSFET (54), a first PNPN thyristor (56), a fourth U-MOSFET (55) and a second PNPN thyristor (57), wherein the source of the third U-MOSFET (54) is connected to the N-type gate of the first PNPN thyristor (56), and the drain of the third U-MOSFET (54) is connected to the cathode of the first PNPN thyristor (55); the source electrode of the fourth U-MOSFET (55) is connected with the N-type grid electrode of the second PNPN thyristor (57), and the drain electrode of the fourth U-MOSFET (55) is connected with the cathode electrode of the second PNPN thyristor (57);
characterized in that the gate of the third U-MOSFET (54) and the gate of the fourth U-MOSFET (55) are connected and connected to a positive supply voltage; the drain electrode of the third U-MOSFET (54), the cathode electrode of the first PNPN thyristor (56), the drain electrode of the fourth U-MOSFET (55) and the cathode electrode of the second PNPN thyristor (57) are commonly grounded; the anode of the first PNPN thyristor (56) is connected with a first transmission telephone line, and the anode of the second PNPN thyristor (57) is connected with a second transmission telephone line.
7. A programmable overvoltage protection device with U-MOSFETs and thyristors according to claim 6 characterized in that the first PNPN thyristor (56), the third U-MOSFET (54), the fourth U-MOSFET (55) and the second PNPN thyristor (57) are formed on a P-type silicon single crystal; the fourth U-MOSFET (55) and the second PNPN thyristor (57) are arranged symmetrically to the third U-MOSFET (54) and the first PNPN thyristor (56).
8. The programmable overvoltage protection device with the U-MOSFET and the thyristor according to claim 6, wherein the cell structure of the first PNPN thyristor (56) comprises a second back metal (51), a second P-type base region (34) and a front metal structure which are sequentially stacked from bottom to top, and the second P-type base region (34) is a P-type silicon single crystal;
the bottom layer of the second P-type base region (34) is sequentially provided with a heavily doped N-type cathode contact region (36) and a second N-type cathode (35) in a stacked mode from bottom to top, and the heavily doped N-type cathode contact region (36) is located on the upper surface of the second back metal (51);
an N-type isolation region (37), a second N-type base region (39) and a heavily doped P-type region (40) are arranged in the top layer of the second P-type base region (34), the heavily doped P-type regions (40) are positioned on two sides of the second N-type base region (39) at intervals, the N-type isolation region (37) is positioned on one side, far away from the second N-type base region (39), of the heavily doped P-type region (40) at intervals and positioned on the upper surface of the second N-type cathode (35), and a heavily doped N-type isolation region (38) is arranged in the top layer of the N-type isolation region (37);
a plurality of second P-type anodes (41) are arranged at the top layer of the second N-type base region (39) at intervals, and gaps among the plurality of second P-type anodes (41) are anode short-circuit holes (42) formed in the second N-type base region (39);
the front metal structure comprises an anode electrode (52) and a third front electrode (48), wherein the anode electrode (52) is positioned on the second P-type anode (41) and the anode short circuit hole (42), and the third front electrode (48) is positioned on the second N-type base region (39) and is used as a base electrode of the first PNPN thyristor (56).
9. A programmable overvoltage protection device with U-MOSFET and thyristor according to claim 8 characterized in that the cell structure of the third U-MOSFET (54) comprises a second back metal (51), a P-type substrate (43) and a third front electrode (48) stacked in sequence from bottom to top; the P-type substrate (43) is a P-type silicon single crystal;
the bottom layer of the P-type substrate (43) is provided with a heavily doped P-type drain contact region (44), the heavily doped P-type drain contact region (44) is positioned on the upper surface of the second back metal (51), and one side of the heavily doped P-type drain contact region is in contact with one side of the heavily doped N-type cathode contact region (36);
the top layer of the P-type substrate (43) is provided with an N-type body region (46) and a second gate oxide layer (49) which are contacted with each other at the side surfaces; the N-type body region (46) is arranged close to one side of the N-type isolation region (37), the second gate oxide layer (49) is arranged far away from one side of the N-type isolation region (37), the top layer of the N-type body region (46) is provided with a heavily doped N-type contact region (45) and a heavily doped P-type source region (47) of which the side surfaces are mutually contacted, and one side of the heavily doped P-type source region (47) is contacted with one side of the second gate oxide layer (49); the second gate oxide layer (49) is provided with a second polysilicon gate electrode (50);
a third front electrode (48) is located on the heavily doped N-type contact region (45) and the heavily doped P-type source region (47) for serving as a source of a third U-MOSFET (54).
10. A programmable overvoltage protection device with U-MOSFETs and thyristors in accordance with claim 9 characterised in that the third front electrode (48) of the first PNPN thyristor (56) is connected to the third front electrode (48) of the third U-MOSFET (54), the fourth front electrode of the fourth U-MOSFET (55) is connected to the fourth front electrode of the second PNPN thyristor (57), and the second back metal (51) of the first and second PNPN thyristors (56, 57) is connected to the second back metal (51) of the third and fourth U-MOSFETs (54, 55).
CN202010500408.0A 2020-06-04 2020-06-04 Programmable overvoltage protection device with U-MOSFET and thyristor Active CN111627903B (en)

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