CN111627486A

CN111627486A - Shift register, driving method thereof and driving circuit

Info

Publication number: CN111627486A
Application number: CN202010559001.5A
Authority: CN
Inventors: 邓可; 王崇浔; 郭会斌; 李博; 闫帅; 刘赫
Original assignee: BOE Technology Group Co Ltd; Wuhan BOE Optoelectronics Technology Co Ltd
Current assignee: BOE Technology Group Co Ltd; Wuhan BOE Optoelectronics Technology Co Ltd
Priority date: 2020-06-18
Filing date: 2020-06-18
Publication date: 2020-09-04
Anticipated expiration: 2040-06-18
Also published as: CN111627486B

Abstract

The invention discloses a shift register, a driving method thereof and a driving circuit, which comprise an input module, a reset module, an output module and a noise reduction module. Through the mutual cooperation of the modules, the signal can be shifted and output. And, through having set up the module of making an uproar, can make an uproar to first node. The noise reduction module of the embodiment of the invention controls through the signal of the reset signal end and the signal of the input signal end, so that additional signal wires are not needed. The transistors required to be arranged are reduced, the structure of the shift register is simplified, the wiring area of the shift register is reduced, and the light weight and the high effect of the structure are realized.

Description

Shift register, driving method thereof and driving circuit

Technical Field

The present invention relates to the field of display technologies, and in particular, to a shift register, a driving method thereof, and a driving circuit thereof.

Background

With the rapid development of display technology, display panels are increasingly developed toward high integration and low cost. The Array substrate line driving (GOA) technology integrates a Thin Film Transistor (TFT) Gate switch Circuit on an Array substrate of a display panel to form a scan driving of the display panel, so that a wiring space of a binding (binding) region and a Fan-out (Fan-out) region of an Integrated Circuit (IC) can be omitted, and not only can the product cost be reduced in two aspects of material cost and preparation process, but also the display panel can be designed to be symmetrical at two sides and beautiful with a narrow frame; moreover, the integration process can also omit the Bonding process in the direction of a grid scanning line, thereby improving the productivity and the yield.

Disclosure of Invention

The embodiment of the invention provides a shift register, a driving method thereof and a driving circuit, which can realize the shift output of signals.

Therefore, the embodiment of the invention provides a shift register, which comprises an input module, a reset module, an output module and a noise reduction module;

wherein the input module is configured to provide a signal of an input signal terminal to a first node under control of a signal of the input signal terminal;

the output module is configured to provide a signal of a clock signal terminal to an output signal terminal under the control of the signal of the first node;

the reset module is configured to provide a signal of a power supply voltage terminal to the first node and the output signal terminal under signal control of a reset signal terminal;

the noise reduction module is configured to provide a signal of the power supply voltage terminal to the first node and the output signal terminal under control of a signal of the reset signal terminal and a signal of the input signal terminal.

Optionally, the noise reduction module comprises a node control module and a stabilization module;

wherein the node control module is configured to provide the signal of the reset signal terminal to a second node under the control of the signal of the reset signal terminal, and to provide the signal of the power supply voltage terminal to the second node under the control of the signal of the input signal terminal;

the stabilization module is configured to provide a signal of the supply voltage terminal to the first node and the output signal terminal under signal control of the second node.

Optionally, the node control module comprises a first switch transistor, a second switch transistor and a first capacitor;

a first end and a control end of the first switching transistor are electrically connected with the reset signal end, and a second end of the first switching transistor is electrically connected with the second node;

a first end of the second switching transistor is electrically connected with the power supply voltage end, a control end of the second switching transistor is electrically connected with the input signal end, and a second end of the second switching transistor is electrically connected with the second node;

the first end of the first capacitor is electrically connected with the control end of the first switching transistor, and the second end of the first capacitor is electrically connected with the second node.

Optionally, the node control module comprises a third switching transistor, a fourth switching transistor and a second capacitor;

a first end and a control end of the third switching transistor are electrically connected with the reset signal end, and a second end of the third switching transistor is electrically connected with the second node;

a first end of the fourth switching transistor is electrically connected with the power supply voltage end, a control end of the fourth switching transistor is electrically connected with the input signal end, and a second end of the fourth switching transistor is electrically connected with the second node;

the first end of the second capacitor is electrically connected with the input signal end, and the second end of the second capacitor is electrically connected with the second node.

Optionally, the stabilizing module comprises a fifth switching transistor and a sixth switching transistor;

a first end of the fifth switching transistor is electrically connected with the power supply voltage end, a control end of the fifth switching transistor is electrically connected with the second node, and a second end of the fifth switching transistor is electrically connected with the first node;

the first end of the sixth switching transistor is electrically connected with the power supply voltage end, the control end of the sixth switching transistor is electrically connected with the second node, and the second end of the sixth switching transistor is electrically connected with the output signal end.

Optionally, the input module includes an input transistor, a first terminal and a control terminal of the input transistor are electrically connected to the input signal terminal, and a second terminal of the input transistor is electrically connected to the first node.

Optionally, the reset module comprises a first reset transistor and a second reset transistor;

a first end of the first reset transistor is electrically connected with the power supply voltage end, a control end of the first reset transistor is electrically connected with the reset signal end, and a second end of the first reset transistor is electrically connected with the first node;

the first end of the second reset transistor is electrically connected with the power supply voltage end, the control end of the second reset transistor is electrically connected with the reset signal end, and the second end of the second reset transistor is electrically connected with the output signal end.

Optionally, the output module comprises an output transistor and a third capacitor;

the first end of the output transistor is electrically connected with the clock signal end, the control end of the output transistor is electrically connected with the first node, and the second end of the output transistor is electrically connected with the output signal end;

and the first end of the third capacitor is electrically connected with the first node, and the second end of the third capacitor is electrically connected with the output signal end.

Correspondingly, the embodiment of the invention also provides a driving circuit, which comprises a plurality of cascaded shift registers of any one of the shift registers; wherein:

the input signal end of the first-stage shift register is electrically connected with the trigger signal end;

in each adjacent two stages of shift registers, the output signal end of the previous stage shift register is electrically connected with the input signal end of the next stage shift register, and the output signal end of the next stage shift register is electrically connected with the reset signal end of the previous stage shift register.

Correspondingly, an embodiment of the present invention further provides a method for driving any one of the shift registers, including:

the first stage, loading a signal of a first level to an input signal end, loading a signal of a second level to a reset signal end, and loading a signal of a second level to a clock signal end;

in the second stage, a signal of a second level is loaded on the input signal end, a signal of the second level is loaded on the reset signal end, and a signal of a first level is loaded on the clock signal end;

and in the third stage, a signal of the second level is loaded to the input signal end, a signal of the first level is loaded to the reset signal end, and a signal of the second level is loaded to the clock signal end.

The invention has the following beneficial effects:

the shift register, the driving method thereof and the driving circuit provided by the embodiment of the invention comprise an input module, a reset module, an output module and a noise reduction module. Through the mutual cooperation of the modules, the signal can be shifted and output. And, through having set up the module of making an uproar, can make an uproar to first node. The noise reduction module of the embodiment of the invention controls through the signal of the reset signal end and the signal of the input signal end, so that additional signal wires are not needed. The transistors required to be arranged are reduced, the structure of the shift register is simplified, the wiring area of the shift register is reduced, and the light weight and the high effect of the structure are realized.

Drawings

FIG. 1 is a diagram illustrating a shift register according to the related art;

FIG. 2 is a diagram illustrating a shift register according to another related art;

FIG. 3 is a timing diagram of signals corresponding to the shift register shown in FIG. 2;

FIG. 4 is a diagram illustrating a shift register according to another related art;

FIG. 5 is a timing diagram of signals corresponding to the shift register shown in FIG. 4;

FIG. 6 is a diagram illustrating a shift register according to an embodiment of the present invention;

fig. 7 is a schematic structural diagram of a shift register according to an embodiment of the present invention;

FIG. 8 is a diagram illustrating a structure of another shift register according to an embodiment of the present invention;

FIG. 9 is a timing diagram of signals corresponding to the shift register shown in FIG. 7;

fig. 10 is a flowchart of a driving method of a shift register according to an embodiment of the present invention;

fig. 11 is a schematic diagram of a driving circuit according to an embodiment of the invention.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the drawings of the embodiments of the present invention. It is to be understood that the embodiments described are only a few embodiments of the present invention, and not all embodiments. And the embodiments and features of the embodiments may be combined with each other without conflict. All other embodiments, which can be derived by a person skilled in the art from the described embodiments of the invention without any inventive step, are within the scope of protection of the invention.

Unless defined otherwise, technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this invention belongs. The use of "first," "second," and similar terms in the present application do not denote any order, quantity, or importance, but rather the terms are used to distinguish one element from another. The word "comprising" or "comprises", and the like, means that the element or item listed before the word covers the element or item listed after the word and its equivalents, but does not exclude other elements or items. The terms "connect" or "electrically connect," and the like, are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect.

It should be noted that the sizes and shapes of the figures in the drawings are not to be considered true scale, but are merely intended to schematically illustrate the present invention. And the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout.

As shown in fig. 1, a shift register in the related art includes four transistors M01-M04 and a capacitor Cst, wherein the signal at node PU has noise, which may affect the output of the signal.

In order to solve the above problem, in the related art, a noise reduction unit is added to the shift register to stabilize the signal of the node PU. Illustratively, in a modification, as shown in fig. 2, six transistors M05 to M10 and one signal line for supplying a clock signal ClkB are added on the basis of the structure of the shift register shown in fig. 1, and the corresponding signal timing diagram is shown in fig. 3. As can be seen from fig. 2 and 3, the transistor M07 is turned on only when the clock signal ClkB is at a high level, so as to reduce noise at the node PU, and there is no noise reduction effect when the clock signal ClkB is at a low level. I.e. the node PU is denoised only about half of the time, which is less effective.

In another modification, as shown in fig. 4, on the basis of the structure of the shift register shown in fig. 1, six transistors M11 to M16 and one signal line VDD for providing a high level are added, and a corresponding signal timing diagram is shown in fig. 5, and it can be seen from fig. 4 and 5 that the node PD is at a high level most of the time, so that the transistor M13 is turned on, and the noise reduction effect on the node PU is good. However, the lifetime of the transistor is short.

In addition, in both of the above two improvements, signal lines and many transistors need to be added, which increases the wiring area of the shift register and is not favorable for realizing a narrow frame.

As shown in fig. 6 to 8, the shift register according to the embodiment of the present invention includes an input module 10, a reset module 20, an output module 30, and a noise reduction module 40;

wherein the Input module 10 is configured to provide the signal of the Input signal terminal Input to the first node N1 under the control of the signal of the Input signal terminal Input;

the Output module 30 is configured to provide the signal of the clock signal terminal CLK to the Output signal terminal Output under the control of the signal of the first node N1;

the Reset module 20 is configured to provide a signal of the power supply voltage terminal VSS to the first node N1 and the Output signal terminal Output under the control of a signal of the Reset signal terminal Reset;

the noise reduction module 40 is configured to supply a signal of the power supply voltage terminal VSS to the first node N1 and the Output signal terminal Output under control of a signal of the Reset signal terminal Reset and a signal of the Input signal terminal Input.

The shift register provided by the embodiment of the invention can realize the shift output of signals through the mutual matching of the modules. And, through having set up the module of making an uproar, can make an uproar to first node. The noise reduction module of the embodiment of the invention controls through the signal of the reset signal end and the signal of the input signal end, so that additional signal wires are not needed. The transistors required to be arranged are reduced, the structure of the shift register is simplified, the wiring area of the shift register is reduced, and the light weight and the high effect of the structure are realized.

In particular implementation, in the embodiment of the present invention, as shown in fig. 7 and 8, the noise reduction module 40 may include a node control module 41 and a stabilization module 42;

wherein the node control module 41 is configured to provide the signal of the Reset signal terminal Reset to the second node N2 under the control of the signal of the Reset signal terminal Reset, and to provide the signal of the power supply voltage terminal VSS to the second node N2 under the control of the signal of the Input signal terminal Input;

the stabilization block 42 is configured to provide a signal of the power supply voltage terminal VSS to the first node N1 and the Output signal terminal Output under the control of the signal of the second node N2.

In practical implementation, in the embodiment of the present invention, as shown in fig. 7 and fig. 8, the node control module 41 may include a first switch transistor M1, a second switch transistor M2, and a first capacitor C1;

wherein, the first terminal and the control terminal of the first switching transistor M1 are electrically connected to the Reset signal terminal Reset, and the second terminal of the first switching transistor M1 is electrically connected to the second node N2;

a first terminal of the second switching transistor M2 is electrically connected to the power supply voltage terminal VSS, a control terminal of the second switching transistor M2 is electrically connected to the Input signal terminal Input, and a second terminal of the second switching transistor M2 is electrically connected to the second node N2;

a first terminal of the first capacitor C1 is electrically connected to the control terminal of the first switching transistor M1, and a second terminal of the first capacitor C1 is electrically connected to the second node N2.

In a specific implementation, the first switching transistor M1 may provide a signal of the Reset signal terminal Reset to the second node N2 when the signal of the Reset signal terminal Reset is in a turned-on state.

In an implementation, the second switching transistor M2 may provide the signal of the power supply voltage terminal VSS to the second node N2 when the signal of the Input signal terminal Input is in a conducting state.

In particular, the first capacitor C1 may store the voltage input across it, and keep its voltage constant while the second node N2 is floating.

In practical implementation, in the embodiment of the present invention, as shown in fig. 7 and fig. 8, the node control module 41 may include a third switching transistor M3, a fourth switching transistor M4, and a second capacitor C2;

a first terminal and a control terminal of the third switching transistor M3 are electrically connected to the Reset signal terminal Reset, and a second terminal of the third switching transistor M3 is electrically connected to the second node N2;

a first end of the fourth switching transistor M4 is electrically connected to the power supply voltage terminal VSS, a control end of the fourth switching transistor M4 is electrically connected to the Input signal terminal Input, and a second end of the fourth switching transistor M4 is electrically connected to the second node N2;

a first terminal of the second capacitor C2 is electrically connected to the Input signal terminal Input, and a second terminal of the second capacitor C2 is electrically connected to the second node N2.

In a specific implementation, the third switching transistor M3 may provide a signal of the Reset signal terminal Reset to the second node N2 when the signal of the Reset signal terminal Reset is in a turned-on state.

In an implementation, the fourth switching transistor M4 may provide the signal of the power supply voltage terminal VSS to the second node N2 when responding to the signal of the Input signal terminal Input in the on state.

In an implementation, the second capacitor C2 may store the voltage inputted to its two terminals, and may keep the voltage difference between its two terminals stable when the second node N2 is floating. For example, when the voltage of the signal Input at the Input signal terminal changes while the second node N2 is floating, the second capacitor C2 may adjust the voltage of the signal at the second node N2.

In particular implementation, in the embodiment of the present invention, as shown in fig. 7 and 8, the stabilizing module 42 may include a fifth switching transistor M5 and a sixth switching transistor M6;

a first terminal of the fifth switching transistor M5 is electrically connected to the power voltage terminal VSS, a control terminal of the fifth switching transistor M5 is electrically connected to the second node N2, and a second terminal of the fifth switching transistor M5 is electrically connected to the first node N1;

a first terminal of the sixth switching transistor M6 is electrically connected to the power supply voltage terminal VSS, a control terminal of the sixth switching transistor M6 is electrically connected to the second node N2, and a second terminal of the sixth switching transistor M6 is electrically connected to the Output signal terminal Output.

In a specific implementation, when the fifth switching transistor M5 is in a turned-on state in response to the signal of the second node N2, the voltage of the power supply voltage terminal VSS may be supplied to the first node N1, thereby stabilizing the voltage of the signal of the first node N1.

In a specific implementation, when the sixth switching transistor M6 is in a conducting state in response to the signal at the second node N2, the voltage of the power supply voltage terminal VSS can be provided to the Output signal terminal Output, so that the voltage of the signal at the Output signal terminal Output is kept stable.

In practical implementation, as shown in fig. 7 and 8, in the embodiment of the present invention, the Input module 10 may include an Input transistor MI, a first terminal and a control terminal of the Input transistor MI are electrically connected to the Input signal terminal Input, and a second terminal of the Input transistor MI is electrically connected to the first node N1. The Input transistor MI may supply the signal of the Input signal terminal Input to the first node N1 when it is in a turned-on state in response to the signal of the Input signal terminal Input.

In specific implementation, in the embodiment of the present invention, as shown in fig. 7 and 8, the reset module 20 may include a first reset transistor Mr1 and a second reset transistor Mr 2;

a first end of the first Reset transistor Mr1 is electrically connected to the power supply voltage terminal VSS, a control end of the first Reset transistor Mr1 is electrically connected to the Reset signal terminal Reset, and a second end of the first Reset transistor Mr1 is electrically connected to the first node N1;

a first terminal of the second Reset transistor Mr2 is electrically connected to the power supply voltage terminal VSS, a control terminal of the second Reset transistor Mr2 is electrically connected to the Reset signal terminal Reset, and a second terminal of the second Reset transistor Mr2 is electrically connected to the Output signal terminal Output.

In a specific implementation, the first Reset transistor Mr1 may provide a signal of the power supply voltage terminal VSS to the first node N1 when it is in a turned-on state in response to a signal of the Reset signal terminal Reset.

In a specific implementation, the second Reset transistor Mr2 may provide the signal of the power supply voltage terminal VSS to the Output signal terminal Output when the signal of the Reset signal terminal Reset is in a conducting state.

In practical implementation, in the embodiment of the present invention, as shown in fig. 7 and fig. 8, the output module 30 may include an output transistor MO and a third capacitor C3;

a first end of the Output transistor MO is electrically connected to the clock signal end CLK, a control end of the Output transistor MO is electrically connected to the first node N1, and a second end of the Output transistor MO is electrically connected to the Output signal end Output;

a first terminal of the third capacitor C3 is electrically connected to the first node N1, and a second terminal of the third capacitor C3 is electrically connected to the Output signal terminal Output.

In a specific implementation, the Output transistor MO may provide the signal of the clock signal terminal CLK to the Output signal terminal Output when the signal of the first node N1 is in a conducting state.

In an implementation, the third capacitor C3 may store the voltage inputted to its two terminals, and may keep the voltage difference between its two terminals stable when the first node N1 is floating. For example, when the voltage of the signal at the Output signal terminal Output changes while the first node N1 is floating, the third capacitor C3 may adjust the voltage of the signal at the first node N1.

The specific structure of each circuit in the shift register provided in the embodiment of the present invention is merely illustrated, and in the implementation, the specific structure of each circuit is not limited to the structure provided in the embodiment of the present invention, and may be other structures known to those skilled in the art, and is not limited herein.

Specifically, in order to make the manufacturing process uniform, in the shift register provided in the embodiment of the present invention, as shown in fig. 7 and fig. 8, all the transistors may be N-type transistors, and of course, all the transistors may also be P-type transistors, which is not limited herein.

Specifically, in the shift register provided in the embodiment of the present invention, the P-type transistor is turned on by a low-level signal and turned off by a high-level signal; the N-type transistor is turned on under the action of a high-level signal and is turned off under the action of a low-level signal.

Specifically, in the shift register provided in the embodiment of the present invention, each Transistor may be a Thin Film Transistor (TFT) or a Metal oxide semiconductor field effect Transistor (MOS), which is not limited herein. The control terminal of each transistor is used as a gate, the first terminal of each transistor is used as a source, and the second terminal of each transistor is used as a drain, or the first terminal of each transistor is used as a drain and the second terminal of each transistor is used as a source, according to the type of each transistor and the signal of the control terminal of each transistor, which is not particularly distinguished herein.

The present invention will be described in detail with reference to specific examples. It should be noted that the present embodiment is intended to better explain the present invention, but not to limit the present invention.

The operation of the shift register provided in the embodiment of the present invention is described below with reference to a circuit timing diagram. In the following description, 1 represents a high level, and 0 represents a low level. It should be noted that 1 and 0 are logic levels, which are only used to better explain the specific operation of the embodiment of the present invention, and not specific voltage values.

The operation of the shift register according to the embodiment of the invention is described with reference to the signal timing diagram shown in fig. 9 by taking the structure of the shift register shown in fig. 7 as an example, wherein the signal of the power supply voltage terminal VSS is a low level signal, and specifically, three stages of the first stage t1, the second stage t2 and the third stage t3 in the signal timing diagram shown in fig. 9 are selected for description.

In the first phase t1, Input is 1, Reset is 0, and CLK is 0.

Since Input is 1, the Input transistor MI is turned on, and the second switching transistor M2 is turned on. Since Reset is 0, the first switching transistor M1, the first Reset transistor Mr1, and the second Reset transistor Mr2 are all turned off.

The turned-on second switching transistor M2 provides a low level signal to the second node N2, so that the second node N2 is at a low level, and the fifth switching transistor M5 and the sixth switching transistor M6 are turned off. The turned-on input transistor MI supplies a high level signal to the first node N1 to make the first node N1 high, and the Output transistor MO is turned on to supply a low level signal of the clock signal terminal to the Output signal terminal Output to make the shift register Output a low level.

In the second stage t2, Input is 0, Reset is 0, and CLK is 1.

Since Input is 0, the Input transistor MI is turned off, and the second switching transistor M2 is turned off. Since Reset is 0, the first switching transistor M1, the first Reset transistor Mr1, and the second Reset transistor Mr2 are all turned off.

The second node N2 is maintained at a low level, and the fifth switching transistor M5 and the sixth switching transistor M6 are turned off. The first node N1 is kept at a high level, the Output transistor MO is turned on, and a high level signal of the clock signal terminal is supplied to the Output signal terminal Output, so that the shift register outputs a high level.

In the third stage t3, Input is 0, Reset is 1, and CLK is 0.

Since Input is 0, the Input transistor MI is turned off, and the second switching transistor M2 is turned off. Since Reset is 1, the first switching transistor M1, the first Reset transistor Mr1, and the second Reset transistor Mr2 are all turned on.

The turned-on first switching transistor M1 provides a high level signal to the second node N2, making the second node N2 high, and the fifth and sixth switching transistors M5 and M6 are turned on. The turned-on first reset transistor Mr1 and the fifth switching transistor M5 supply a low level signal to the first node N1, so that the first node N1 is at a low level and the output transistor MO is turned off. The turned-on second reset transistor Mr2 and sixth switching transistor M6 supply a low level signal to the Output signal terminal Output, so that the shift register outputs a low level.

After the third stage t3, Input is 0 and Reset is 0, and the Input transistor MI, the first switching transistor M1, the second switching transistor M2, the first Reset transistor Mr1, and the second Reset transistor Mr2 remain turned off. The second node N2 is kept at a high level, the fifth switching transistor M5 and the sixth switching transistor M6 are kept on, a low level signal is supplied to the first node N1 and the Output signal terminal Output, the first node N1 is kept at a low level, the Output transistor MO is turned off, and the shift register outputs a low level until the next first stage t 1.

Based on the same inventive concept, an embodiment of the present invention further provides a method for driving any one of the shift registers, as shown in fig. 10, including:

Based on the same inventive concept, an embodiment of the present invention further provides a driving circuit, as shown in fig. 11, including a plurality of cascaded shift registers according to any one of the embodiments of the present invention: SR (1), SR (2) … SR (N-1), SR (N) …, SR (N-1), SR (N) (N shift registers in total, N is more than or equal to 1 and less than or equal to N); wherein:

an Input signal end of the first-stage shift register is electrically connected with a trigger signal end STV;

in each two adjacent stages of shift registers, an Output signal end Output of the previous stage of shift register is electrically connected with an Input signal end Input of the next stage of shift register, and an Output signal end Output of the next stage of shift register is electrically connected with a Reset signal end Reset of the previous stage of shift register.

Specifically, the specific structure of each shift register in the driving circuit is the same as any one of the shift registers provided in the embodiments of the present invention in function and structure, and repeated descriptions are omitted.

In specific implementation, in the specific implementation, the clock signal terminal CLK of the odd-numbered stage shift register is electrically connected to the first clock line CLK 1; the clock signal terminal CLK of the even-numbered stage shift register is electrically connected to the second clock line CLK 2.

In specific implementation, the driving circuit provided by the embodiment of the invention can be used as a gate driving circuit and applied to providing a gate scanning signal of the scanning control transistor.

In practical implementation, the driving circuit provided by the embodiment of the invention can be used as a light emitting driving circuit and applied to provide a light emitting control signal of the light emitting control transistor.

Based on the same inventive concept, the embodiment of the invention also provides a display device, which comprises the driving circuit provided by the invention. The specific implementation of the shift register can be referred to the implementation process of the shift register, and the same parts are not described again.

In a specific implementation, the display device provided in the embodiment of the present invention may be an organic light emitting display device, or may also be a liquid crystal display device, which is not limited herein.

In general, an organic light emitting display device includes a plurality of organic light emitting diodes and pixel circuits connected to the organic light emitting diodes. A light emission control transistor for controlling light emission of the organic light emitting diode and a scan control transistor for controlling input of a data signal are provided in a general pixel circuit. In a specific implementation, when the display device provided in the embodiment of the present invention is an organic light emitting display device, the organic light emitting display device may include the driving circuit provided in the embodiment of the present invention, and the driving circuit may be used as a light emitting driving circuit for providing a light emitting control signal of the light emitting control transistor; alternatively, the driving circuit may be applied to supply a gate scanning signal of the scanning control transistor as a gate driving circuit. Of course, the organic light emitting display device may also include two driving control circuits provided in the embodiments of the present invention, where one of the driving circuits may be used as a light emitting driving circuit and applied to provide a light emitting control signal for the light emitting control transistor; the other driving circuit is used as a gate driving circuit for providing a gate scanning signal of the scanning control transistor, and is not limited herein.

In general, a liquid crystal display device includes a plurality of pixel electrodes and switching transistors connected to the pixel electrodes. In a specific implementation, when the display device provided by the embodiment of the present invention is a liquid crystal display device, the driving circuit provided by the embodiment of the present invention can be used as a gate driving circuit for providing a gate scanning signal of a switching transistor.

The display device may be: any product or component with a display function, such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator and the like. Other essential components of the display device are understood by those skilled in the art, and are not described herein or should not be construed as limiting the invention.

It will be apparent to those skilled in the art that various changes and modifications may be made in the present invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.

Claims

1. A shift register comprises an input module, a reset module and an output module, and is characterized by also comprising a noise reduction module;

2. The shift register of claim 1, wherein the noise reduction module comprises a node control module and a stabilization module;

3. The shift register of claim 2, wherein the node control module includes a first switching transistor, a second switching transistor, and a first capacitor;

4. The shift register of claim 2, wherein the node control module includes a third switching transistor, a fourth switching transistor, and a second capacitor;

5. The shift register of claim 2, wherein the stabilization block includes a fifth switching transistor and a sixth switching transistor;

6. The shift register of any one of claims 1-5, wherein the input block includes an input transistor, a first terminal and a control terminal of the input transistor are electrically connected to the input signal terminal, and a second terminal of the input transistor is electrically connected to the first node.

7. The shift register of any one of claims 1-5, wherein the reset module includes a first reset transistor and a second reset transistor;

8. The shift register of any one of claims 1-5, wherein the output module includes an output transistor and a third capacitor;

9. A driver circuit comprising a plurality of shift registers according to any one of claims 1 to 8 in cascade; wherein:

10. A driving method of a shift register according to any one of claims 1 to 8, comprising: