CN111626015B - Method, device and chip for reducing core size of nonvolatile flash memory - Google Patents
Method, device and chip for reducing core size of nonvolatile flash memory Download PDFInfo
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- CN111626015B CN111626015B CN202010549603.2A CN202010549603A CN111626015B CN 111626015 B CN111626015 B CN 111626015B CN 202010549603 A CN202010549603 A CN 202010549603A CN 111626015 B CN111626015 B CN 111626015B
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Abstract
The invention discloses a method, a device and a chip for reducing the core size of a nonvolatile flash memory.A distance between adjacent well regions with consistent working voltage is removed if the adjacent well regions with consistent working voltage exist by judging whether the adjacent well regions with consistent working voltage exist on the chip, so that the adjacent well regions with consistent working voltage are merged together; the technical scheme can greatly reduce the total area of a specific module area of the chip without reducing the width-length ratio of the mos device, so that the problems of increase of leakage current and reduction of breakdown voltage caused by reduction of the width-length ratio of the mos device are solved.
Description
Technical Field
The invention relates to the field of IC process manufacturing, in particular to a method, a device and a chip for reducing the core size of a nonvolatile flash memory.
Background
As IC chips become more integrated, the total chip area becomes more important to the chip manufacturing cost, and in order to be able to manufacture more mos devices in the same area, we need to reduce the size of the mos devices used as much as possible without losing the device performance.
The traditional method for shrinking devices, such as the shrinking method of mos transistors, mainly reduces the width (width) and length (length) of the mos transistor compared with the same proportion, but as the length (length) of the mos transistor channel is reduced, the mos transistor is faced with the serious degradation of device performance, such as increase of leakage current, reduction of breakdown voltage, and the like, so that the challenge of a circuit design end is greatly increased.
Therefore, the prior art still needs to be improved and developed.
Disclosure of Invention
The invention aims to provide a method, a device and a chip for reducing the core size of a nonvolatile flash memory, and aims to solve the problem that the performance of a device is influenced by the conventional method for improving the utilization rate of the area of the chip by shrinking the size of the device.
The technical scheme of the invention is as follows: a method for reducing the core size of a non-volatile flash memory specifically comprises the following steps:
s1: judging whether adjacent well regions with consistent working voltage exist on the chip, if so, jumping to S2, otherwise, jumping to S3;
s2: the distance between the adjacent well regions with consistent working voltage is removed, so that the adjacent well regions with consistent working voltage are combined together;
s3: the distance between adjacent well regions is not changed.
In the method for reducing the core size of the nonvolatile flash memory, the adjacent well regions with consistent working voltage are N well regions.
The method for reducing the core size of the nonvolatile flash memory comprises the following steps that adjacent well regions with consistent working voltage are provided, wherein one of the adjacent well regions is a high-voltage N well (HV NW), and a high-voltage P pipe is manufactured on the adjacent well regions; the other is a high-voltage N well (DNW) and a high-voltage P well (TPW) on the DNW, and a high-voltage N tube is manufactured in the TPW well. .
The method for reducing the core size of the non-volatile flash memory, wherein the step S2 further includes the steps of:
s 21: judging whether the adjacent well regions with the consistent working voltage are arranged along the X direction or the Y direction, if so, jumping to s22, and if so, jumping to s 23;
s 22: the distance between the adjacent well regions with the same working voltage in the X direction is removed, so that the adjacent well regions with the same working voltage are combined together in the X direction;
s 23: and removing the distance between the adjacent well regions with consistent working voltage in the Y direction, so that the adjacent well regions with consistent working voltage are combined together in the Y direction.
An apparatus for employing the method for reducing the core size of a non-volatile flash memory as described in any of the above, comprising:
the judging module is used for judging whether adjacent well regions with consistent working voltage exist on the chip;
and the merging module is used for removing the distance between the adjacent well regions with consistent working voltage so as to merge the adjacent well regions with consistent working voltage together.
The device comprises a merging module, a direction judging module and a control module, wherein the merging module is used for judging whether adjacent well regions with consistent working voltage are arrayed along the X direction or the Y direction and sending an instruction to the merging module according to the array direction, and after the direction judging module judges the array direction between the adjacent well regions with consistent working voltage, the direction judging module sends an instruction to the merging module and controls the merging module to merge the adjacent well regions with consistent working voltage along the array direction.
A chip manufactured by the method for reducing the core size of the nonvolatile flash memory comprises a chip body, wherein adjacent well regions with consistent working voltage are arranged on the chip body, the distance between the adjacent well regions with consistent working voltage is zero, namely the adjacent well regions with consistent working voltage are merged together.
In the chip, the adjacent well regions with the same working voltage are arranged along the X direction, and the distance between the adjacent well regions with the same working voltage along the X direction is zero, that is, the adjacent well regions with the same working voltage are combined together along the X direction.
In the chip, the adjacent well regions with the same working voltage are arranged along the Y direction, and the distance between the adjacent well regions with the same working voltage in the Y direction is zero, that is, the adjacent well regions with the same working voltage are merged together along the Y direction.
In the chip, one of the adjacent well regions with the same working voltage is a high-voltage N-well (HV NW), and a high-voltage P-tube is manufactured on the high-voltage N-well; the other is a high-voltage N well (DNW) and a high-voltage P well (TPW) on the DNW, and a high-voltage N tube is manufactured in the TPW well.
The invention has the beneficial effects that: the invention provides a method, a device and a chip for reducing the core size of a nonvolatile flash memory, wherein the method comprises the steps of judging whether adjacent well regions with consistent working voltage exist on the chip, and if the adjacent well regions with consistent working voltage exist, removing the distance between the adjacent well regions with consistent working voltage to combine the adjacent well regions with consistent working voltage; the technical scheme can greatly reduce the total area of a specific module area of the chip without reducing the width-length ratio of the mos device, so that the problems of increase of leakage current and reduction of breakdown voltage caused by reduction of the width-length ratio of the mos device are solved.
Drawings
FIG. 1 is a flow chart of the steps of a method of reducing the core size of a non-volatile flash memory according to the present invention.
FIG. 2 is a schematic view of the apparatus of the present invention.
FIG. 3 is a schematic diagram of a chip according to the present invention.
FIG. 4 is a layout specified by the design rule at the fab side in the prior art.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. The components of the embodiments of the present application, generally described and illustrated in the figures herein, can be arranged and designed in a wide variety of different configurations. Thus, the following detailed description of the embodiments of the present application, presented in the accompanying drawings, is not intended to limit the scope of the claimed application, but is merely representative of selected embodiments of the application. All other embodiments, which can be derived by a person skilled in the art from the embodiments of the present application without making any creative effort, shall fall within the protection scope of the present application.
It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures. Meanwhile, in the description of the present application, the terms "first", "second", and the like are used only for distinguishing the description, and are not to be construed as indicating or implying relative importance.
As shown in fig. 1, a method for reducing the core size of a non-volatile flash memory specifically includes the following steps:
s1: judging whether adjacent well regions with consistent working voltage exist on the chip, if so, jumping to S2, otherwise, jumping to S3;
s2: the distance between the adjacent well regions with consistent working voltage is removed, so that the adjacent well regions with consistent working voltage are combined together;
s3: the distance between adjacent well regions is not changed.
In some embodiments, the well region is an N well region, and the operating voltage of the N well region has a high value and a low value, so that when there is an adjacent well region with a uniform operating voltage, the whole area of the chip can be reduced by removing the spacing distance between the adjacent well regions and reducing the module area.
In this embodiment, the well regions are HV NW (high voltage NWELL high voltage N well region), DNW (DEEP N WELL, deep N well region), and TPW (TRIPLE P WELL, P well region). The HV NW and DNW two N-wells are merged.
In certain embodiments, the S2 further comprises the following steps:
s 21: judging whether the adjacent well regions with the consistent working voltage are arranged along the X direction or the Y direction, if so, jumping to s22, and if so, jumping to s 23;
s 22: the distance between the adjacent well regions with the same working voltage in the X direction is removed, so that the adjacent well regions with the same working voltage are combined together in the X direction;
s 23: and removing the distance between the adjacent well regions with consistent working voltage in the Y direction, so that the adjacent well regions with consistent working voltage are combined together in the Y direction.
As shown in fig. 2, an apparatus adopting the method for reducing the core size of the non-volatile flash memory as described above comprises:
a judging module A1 for judging whether there is an adjacent well region with consistent working voltage on the chip;
and a merging module A2 for merging the adjacent well regions with the same operating voltage by removing the distance between the adjacent well regions with the same operating voltage.
In some embodiments, the apparatus further includes a direction determining module A3 configured to determine whether the adjacent well regions with the same operating voltage are arranged along the X direction or the Y direction, and send a command to the combining module a2 according to the arrangement direction, where after the direction determining module A3 determines the arrangement direction between the adjacent well regions with the same operating voltage, the direction determining module A3 sends a command to the combining module a2, and controls the combining module a2 to combine the adjacent well regions with the same operating voltage along the arrangement direction.
As shown in fig. 3, a chip manufactured by the method for reducing the core size of the non-volatile flash memory as described above includes a chip body 1, and adjacent well regions 2 with uniform operating voltages are disposed on the chip body 1, and the distance between the adjacent well regions with uniform operating voltages is zero, that is, the adjacent well regions with uniform operating voltages are merged together.
In some embodiments, the adjacent well regions 2 with the same operating voltage are arranged along the X direction, and the distance between the adjacent well regions 2 with the same operating voltage along the X direction is zero, that is, the adjacent well regions 2 with the same operating voltage are merged together along the X direction.
In some embodiments, the adjacent well regions 2 with uniform operating voltages are arranged along the Y direction, and the distance between the adjacent well regions 2 with uniform operating voltages along the Y direction is zero, that is, the adjacent well regions 2 with uniform operating voltages merge together along the Y direction.
In some embodiments, the adjacent well regions 2 with the same operating voltage are HV NW and DNW.
According to the technical scheme, the following embodiments are listed for illustration:
fig. 4 is a schematic diagram of a conventional layout structure, i.e., a layout designed according to design rule given by fab. Two mos transistors, one High Voltage PMOS (HVPMOS) is fabricated in high voltage NWELL, the other high voltage NMOS is fabricated in TPW (triple p well), and TPW is fabricated in dnw (deep n well). According to the design rule provided by fab, the well region of the HN NW and the well region of the DNW must satisfy a certain distance X, i.e. the distance between these two well regions is greater than or equal to X.
In the circuit design, the potential of the HV NW, the potential of the DNW, and the potential of the three wells of the TPW may be applied with voltages each required according to the needs of a circuit designer. If the potential of HV NW and the potential of DNW do not match, the two wells do satisfy a certain pitch X. However, if the voltage of the HV NW and the voltage of the DNW are the same, the above-mentioned definition of ≧ X is superfluous and can be completely removed, i.e. we can combine the HV NW well and the DNW well, which reduces our chip size from the original a to a' (a-X) in the direction of X, as shown in fig. 3.
Through the description of the above embodiments, it can be seen that the reduction of the area of a specific module is successfully achieved, thereby achieving the reduction of the whole area of a chip; in the technical scheme, by combining the HVNW and the DNW, an additional mask photomask is not added, and the conventional process flow can be compatible.
In the embodiments provided in the present application, it should be understood that the disclosed apparatus and method may be implemented in other ways. The above-described embodiments of the apparatus are merely illustrative, and for example, the division of the units is only one logical division, and there may be other divisions when actually implemented, and for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection of devices or units through some communication interfaces, and may be in an electrical, mechanical or other form.
In addition, units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.
Furthermore, the functional modules in the embodiments of the present application may be integrated together to form an independent part, or each module may exist separately, or two or more modules may be integrated to form an independent part.
In this document, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions.
The above description is only an example of the present application and is not intended to limit the scope of the present application, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present application shall be included in the protection scope of the present application.
Claims (8)
1. A method for reducing the core size of a non-volatile flash memory is characterized by comprising the following steps:
s1: judging whether adjacent well regions with consistent working voltage exist on the chip, if so, jumping to S2, otherwise, jumping to S3;
s2: the distance between the adjacent well regions with consistent working voltage is removed, so that the adjacent well regions with consistent working voltage are combined together;
s3: the distance between adjacent well regions is not changed;
one of the adjacent well regions with consistent working voltage is a high-voltage N well (HV NW), and a high-voltage P tube is manufactured on the high-voltage N well region; the other is a high-voltage N well (DNW) and a high-voltage P well (TPW) on the DNW, and a high-voltage N tube is manufactured in the TPW well.
2. The method for reducing the core size of a non-volatile flash memory according to claim 1, wherein said S2 further comprises the steps of:
s 21: judging whether the adjacent well regions with the consistent working voltage are arranged along the X direction or the Y direction, if so, jumping to s22, and if so, jumping to s 23; s 22: the distance between the adjacent well regions with the same working voltage in the X direction is removed, so that the adjacent well regions with the same working voltage are combined together in the X direction;
s 23: and removing the distance between the adjacent well regions with consistent working voltage in the Y direction, so that the adjacent well regions with consistent working voltage are combined together in the Y direction.
3. An apparatus employing the method of reducing the core size of a non-volatile flash memory according to any of claims 1 to 2, comprising:
a judging module (A1) for judging whether adjacent well regions with consistent working voltage exist on the chip;
and a merging module (A2) for merging the adjacent well regions with the same operating voltage by removing the distance between the adjacent well regions with the same operating voltage.
4. The apparatus of claim 3, further comprising a direction determining module (A3) for determining whether the adjacent well regions with the same operating voltage are arranged along the X direction or the Y direction, and sending a command to the combining module (A2) according to the arrangement direction, wherein the direction determining module (A3) sends a command to the combining module (A2) after determining the arrangement direction between the adjacent well regions with the same operating voltage, and controls the combining module (A2) to combine the adjacent well regions with the same operating voltage along the arrangement direction.
5. A chip manufactured by the method for reducing the core size of the non-volatile flash memory according to any one of claims 1 to 2, comprising a chip body (1), wherein adjacent well regions (2) with uniform operating voltages are arranged on the chip body (1), and the distance between the adjacent well regions (2) with uniform operating voltages is zero, i.e. the adjacent well regions (2) with uniform operating voltages are merged together.
6. The chip according to claim 5, wherein the adjacent well regions (2) with uniform operating voltages are arranged along the X direction, and the distance between the adjacent well regions (2) with uniform operating voltages along the X direction is zero, i.e. the adjacent well regions (2) with uniform operating voltages merge together along the X direction.
7. The chip according to claim 5, wherein the adjacent well regions (2) with uniform operating voltages are arranged along the Y direction, and the distance between the adjacent well regions (2) with uniform operating voltages along the Y direction is zero, i.e. the adjacent well regions (2) with uniform operating voltages are merged together along the Y direction.
8. The chip according to any of claims 5 to 7, wherein said adjacent well regions (2) of uniform operating voltage, one of which is a high voltage N-well (HV NW), on which are fabricated high voltage P-tubes; the other is a high-voltage N well (DNW) and a high-voltage P well (TPW) on the DNW, and a high-voltage N tube is manufactured in the TPW well.
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| CN202010549603.2A CN111626015B (en) | 2020-06-16 | 2020-06-16 | Method, device and chip for reducing core size of nonvolatile flash memory |
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| US7119399B2 (en) * | 2004-02-27 | 2006-10-10 | Infineon Technologies Ag | LDMOS transistor |
| JP4868934B2 (en) * | 2006-05-11 | 2012-02-01 | ルネサスエレクトロニクス株式会社 | Semiconductor memory device |
| US8138049B2 (en) * | 2009-05-29 | 2012-03-20 | Silergy Technology | Fabrication of lateral double-diffused metal oxide semiconductor (LDMOS) devices |
| CN102184894B (en) * | 2011-04-22 | 2015-04-01 | 上海华虹宏力半导体制造有限公司 | Semiconductor device and forming method thereof, vertical double diffused metal oxide semiconductor (VDMOS) transistor and forming method of VDMOS transistor |
| CN103295887A (en) * | 2013-06-04 | 2013-09-11 | 上海华力微电子有限公司 | Method for improving trap proximity effect |
| CN104485332B (en) * | 2014-12-10 | 2017-05-03 | 中国电子科技集团公司第四十七研究所 | Arrangement method of trap connecting units and semiconductor chip comprising trap connecting units |
| US9761712B1 (en) * | 2016-10-31 | 2017-09-12 | International Business Machines Corporation | Vertical transistors with merged active area regions |
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