CN111613617A - Power semiconductor device, manufacturing method thereof and groove layout structure - Google Patents
Power semiconductor device, manufacturing method thereof and groove layout structure Download PDFInfo
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 68
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 23
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 106
- 238000000034 method Methods 0.000 claims abstract description 33
- 229920005591 polysilicon Polymers 0.000 claims description 64
- 239000000758 substrate Substances 0.000 claims description 22
- 238000005530 etching Methods 0.000 claims description 9
- 238000000151 deposition Methods 0.000 claims description 2
- 230000003647 oxidation Effects 0.000 claims description 2
- 238000007254 oxidation reaction Methods 0.000 claims description 2
- 230000008569 process Effects 0.000 abstract description 12
- 238000010586 diagram Methods 0.000 description 5
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28114—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor characterised by the sectional shape, e.g. T, inverted-T
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
- H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
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Abstract
The invention provides a power semiconductor device, a manufacturing method thereof and a groove layout structure, wherein the groove layout structure comprises a plurality of groove units which are adjacently arranged, each groove unit comprises a first part, a second part and a third part, and the widths of the first part and the third part are smaller than that of the second part; the first groove connecting unit connects the adjacent first portions, the second groove connecting unit connects the adjacent third portions, and the widths of the first groove connecting unit and the second groove connecting unit are smaller than the width of the second portions. According to the invention, the width of the first part and the width of the third part are smaller than that of the second part, so that the two ends of the formed trench can not deposit the shield gate polycrystalline silicon layer and only can deposit the gate polycrystalline silicon layer, and the first trench connection unit and the second trench connection unit are provided with the connection holes, so that the risk of bridging the gate polycrystalline silicon layer and the shield gate polycrystalline silicon layer is avoided, the mask for defining the region where the connection holes are connected with the gate polycrystalline silicon layer is saved, the working procedures are reduced, and the process cost is reduced.
Description
Technical Field
The invention relates to the field of semiconductor integrated circuit manufacturing, in particular to a power semiconductor device, a manufacturing method thereof and a groove structure.
Background
As the degree of integration of semiconductor devices increases, the pitch of integrated circuits also decreases. When a layout structure of a shield gate polysilicon layer trench (SGT) in a power semiconductor device is used for preparing the power semiconductor device subsequently, the process steps are multiple, so that the process cost is high.
Therefore, a trench layout structure is needed to simplify the process steps of the power semiconductor device, thereby reducing the process cost.
Disclosure of Invention
The invention provides a power semiconductor device, a manufacturing method thereof and a groove layout structure, and aims to solve the problems.
The invention provides a groove layout structure, which comprises a plurality of groove units, a first groove connecting unit and a second groove connecting unit, wherein the groove units are arranged adjacently;
the trench unit comprises a first part, a second part and a third part, wherein the first part and the third part are arranged at two sides of the second part along the extension direction of the second part, and the length of the first part and the length of the third part in the extension direction perpendicular to the second part are smaller than that of the second part in the extension direction perpendicular to the second part;
the first groove connection unit connects the adjacent first portions, the second groove connection unit connects the adjacent third portions, and the lengths of the first groove connection unit and the second groove connection unit in the direction perpendicular to the extending direction of the second portions are smaller than the lengths of the second portions in the direction perpendicular to the extending direction of the second portions.
Optionally, the second portion is strip-shaped, and the first portion and the third portion are the same in shape and are both regular two-dimensional figures.
Optionally, the first portion and the third portion are both rectangular and have the same size.
Furthermore, the patterns of the first groove connecting unit and the second groove connecting unit are both long strips, and the first groove connecting unit and the second groove connecting unit are both vertically connected with the groove units.
In another aspect, the present invention provides a method for manufacturing a power semiconductor device, including the steps of:
step S1: forming a plurality of grooves on a semiconductor substrate by using a mask plate with the groove layout structure as a mask;
step S2: sequentially forming a first oxide layer and a shielding grid polycrystalline silicon layer in the groove, wherein the first oxide layer covers the inner wall of the groove, the shielding grid polycrystalline silicon layer fills the groove, the height of the first oxide layer is lower than that of the shielding grid polycrystalline silicon layer, and an opening is formed above the first oxide layer;
step S3: forming a second oxide layer on the semiconductor substrate, wherein the second oxide layer wraps the shielding grid polycrystalline silicon layer and exposes the first oxide layer, so that an opening is formed above the first oxide layer;
step S4: and forming a polysilicon layer at the opening, and etching the polysilicon layer by taking the second oxide layer as a mask to form a grid polysilicon layer so as to form the power semiconductor device.
Optionally, step S1 specifically includes:
and forming a plurality of grooves on the semiconductor substrate by using a mask plate with a plurality of groove units as a mask, wherein the width of two ends of each groove in the extending direction of the groove is narrower than the width of the groove in the middle position in the extending direction of the groove.
Further, the width of both ends of the trench in the extending direction thereof is less than twice the thickness of the first oxide layer.
Optionally, step S2 specifically includes the following steps:
depositing a first oxide layer in the trench, the first oxide layer covering an inner wall of the trench at an intermediate position of the trench in an extending direction thereof, the first oxide layer filling the trench at both ends of the trench in the extending direction thereof;
forming a first polysilicon layer in the trench, wherein the first polysilicon layer fills the middle position of the trench and covers a first oxidation layer on the semiconductor substrate;
etching the first polycrystalline silicon layer on the semiconductor substrate, and reserving the first polycrystalline silicon layer in the middle position of the groove to form a shield grid polycrystalline silicon layer;
and etching the first oxide layer on the semiconductor substrate, and etching the first oxide layer with partial depth in the groove, so that the height of the first oxide layer is lower than that of the shield grid polycrystalline silicon layer, and an opening is arranged above the first oxide layer.
Further, there is a shield gate polysilicon layer at a middle position of the trench in an extending direction thereof, and there is no shield gate polysilicon layer at both ends of the trench in the extending direction thereof.
In another aspect, the invention provides a power semiconductor device, which is prepared by the above method for manufacturing a power semiconductor device and includes a trench.
Compared with the prior art, the invention has the following beneficial effects:
the invention provides a power semiconductor device, a manufacturing method thereof and a groove layout structure, which comprise a plurality of groove units, a first groove connecting unit and a second groove connecting unit which are arranged adjacently; the trench unit comprises a first part, a second part and a third part, wherein the first part and the third part are arranged at two sides of the second part along the extension direction of the second part, and the length of the first part and the length of the third part in the extension direction perpendicular to the second part are smaller than that of the second part in the extension direction perpendicular to the second part; the first groove connection unit connects the adjacent first portions, the second groove connection unit connects the adjacent third portions, and the lengths of the first groove connection unit and the second groove connection unit in the direction perpendicular to the extending direction of the second portions are smaller than the lengths of the second portions in the direction perpendicular to the extending direction of the second portions. According to the invention, the lengths of the first part and the third part in the extending direction vertical to the second part are smaller than the length of the second part in the extending direction vertical to the extending direction, so that the shielding grid polycrystalline silicon layer can not be deposited and only the grid polycrystalline silicon layer can be deposited in the grooves at two ends of the power semiconductor device when the power semiconductor device is formed subsequently, the risk of bridging between the grid polycrystalline silicon layer and the shielding grid polycrystalline silicon layer is avoided by arranging the connecting holes (contact) in the first groove connecting unit and the second groove connecting unit, the normal work of the device is also prevented from being influenced by the occurrence of problems of individual connecting holes in the subsequently formed connecting holes, the mask for defining the region of the connecting holes for connecting the grid polycrystalline silicon layer is saved, the working procedures are also reduced, and the process cost is reduced.
Drawings
FIG. 1 is a schematic structural diagram of an SGT layout structure in the prior art;
FIG. 2 is a schematic diagram of a prior art power semiconductor device;
fig. 3 is a schematic structural diagram of a trench layout structure according to an embodiment of the present invention;
fig. 4 is a schematic flow chart illustrating a method for manufacturing a power semiconductor device according to an embodiment of the invention;
fig. 5a to 5f are schematic structural diagrams of steps of a method for manufacturing a power semiconductor device according to an embodiment of the present invention.
Description of reference numerals:
in FIGS. 1-2:
10-trench cells; a-a preset area;
in FIGS. 3-5 f:
100-trench cells; 110-a first portion; 120-a second portion; 130-a third portion;
100' -a trench;
210-a first trench connection unit; 220-second trench connection unit;
300-a semiconductor substrate;
410-a first oxide layer; 420-a second oxide layer;
510-a shield gate polysilicon layer; 520-gate polysilicon layer.
Detailed Description
As shown in fig. 1, each trench unit 10 of the SGT layout structure in the prior art is in a long strip shape, when the SGT of the structure forms a power semiconductor device (as shown in fig. 2) in the subsequent process, a special preset region a needs to be reserved to set a connection hole due to the narrow width of a gate polysilicon layer of the power semiconductor device, so as to lead out the gate polysilicon layer, a special photomask is needed to define the preset region a in the whole process, the process cost is high, and the effective area utilization rate of the power semiconductor device is low.
Based on the research, the invention provides a power semiconductor device, a manufacturing method thereof and a groove layout structure, wherein the groove layout structure comprises a plurality of groove units, a first groove connecting unit and a second groove connecting unit which are arranged adjacently; the trench unit comprises a first part, a second part and a third part, wherein the first part and the third part are arranged at two sides of the second part along the extension direction of the second part, and the length of the first part and the length of the third part in the extension direction perpendicular to the second part are smaller than that of the second part in the extension direction perpendicular to the second part; the first groove connection unit connects the adjacent first portions, the second groove connection unit connects the adjacent third portions, and the lengths of the first groove connection unit and the second groove connection unit in the direction perpendicular to the extending direction of the second portions are smaller than the lengths of the second portions in the direction perpendicular to the extending direction of the second portions. According to the invention, the lengths of the first part and the third part in the extending direction vertical to the second part are smaller than the length of the second part in the extending direction vertical to the extending direction, so that the shielding grid polycrystalline silicon layer can not be deposited and only the grid polycrystalline silicon layer can be deposited in the grooves at two ends of the power semiconductor device when the power semiconductor device is formed subsequently, and the first groove connecting unit and the second groove connecting unit are provided with the connecting holes (contact), so that the risk of connecting the grid polycrystalline silicon layer and the shielding grid polycrystalline silicon layer is avoided, the mask for defining the region of the connecting holes for connecting the grid polycrystalline silicon layer is saved, the working procedures are reduced, and the process cost is reduced.
A power semiconductor device, a method for manufacturing the same, and a trench layout structure according to the present invention will be described in further detail below. The present invention will now be described in more detail with reference to the accompanying drawings, in which preferred embodiments of the invention are shown, it being understood that one skilled in the art may modify the invention herein described while still achieving the advantageous effects of the invention. Accordingly, the following description should be construed as broadly as possible to those skilled in the art and not as limiting the invention.
In the interest of clarity, not all features of an actual implementation are described. In the following description, well-known functions or constructions are not described in detail since they would obscure the invention in unnecessary detail. It will of course be appreciated that in the development of any such actual embodiment, numerous implementation-specific details must be set forth in order to achieve the developer's specific goals, such as compliance with system-related and business-related constraints, which will vary from one implementation to another. Moreover, it will be appreciated that such a development effort might be complex and time-consuming, but would nevertheless be a routine undertaking for those of ordinary skill in the art.
In order to make the objects and features of the present invention more comprehensible, embodiments of the present invention are described in detail below with reference to the accompanying drawings. It is to be noted that the drawings are in a very simplified form and are all used in a non-precise ratio for the purpose of facilitating and distinctly aiding in the description of the embodiments of the invention.
Fig. 3 is a schematic structural diagram of the trench layout structure according to this embodiment. As shown in fig. 3, the present embodiment provides a trench layout structure, for example, a Shielded Gate Trench (SGT) layout structure.
The trench layout structure includes a plurality of trench cells 100 arranged adjacently, each trench cell 100 includes, for example, a first portion 110, a second portion 120, and a third portion 130, the first portion 110 and the third portion 130 are arranged on two sides of the second portion 120, specifically, the second portion 120 is, for example, in an elongated shape, the first portion 110 and the third portion 130 are arranged on two sides of the second portion 120 along an extending direction of the second portion 120, and the first portion 110 and the third portion 130 are, for example, in the same shape, for example, in a regular two-dimensional pattern, specifically, in a rectangular shape, a circular shape, a polygonal shape, and the like, and have the same size. Of course, the first portion 110 and the third portion 130 may have different shapes and sizes. In this embodiment, the first portion 110 and the third portion 130 are, for example, rectangular. The lengths of the first portion 110 and the third portion 130 in the extending direction perpendicular to the second portion 120 are smaller than the length of the second portion 120 in the extending direction perpendicular to the extending direction, so that the two ends of the trench cell 100 in the extending direction (i.e. at the first portion 110 and the third portion 130) are narrower than the width of the middle portion (i.e. the second portion 120), so that the shield gate polysilicon layer cannot be deposited in the trenches at the two ends and only the gate polysilicon layer can be deposited when the power semiconductor device is formed later.
The trench layout structure further includes a first trench connection unit 210 and a second trench connection unit 220 disposed at two ends of the trench unit 100, and the first trench connection unit and the second trench connection unit are used for disposing connection holes. Specifically, the first connection pattern 210 connects the adjacent first portions 110, the second groove connection unit 220 connects the adjacent third portions 130, and the patterns of the first groove connection unit 210 and the second groove connection unit 220 are both long, preferably, the shapes and the sizes of the patterns of the first groove connection unit 210 and the second groove connection unit 220 are the same. The first trench connection unit 210 and the second trench connection unit 220 are both vertically connected with the trench unit 100, so that the adjacent trench units 100 are connected, connection holes can be formed on the first trench connection unit 210 and the second trench connection unit 220, the formation of the connection holes on the trench unit 100 is not needed, the problem that the normal operation of a device is not influenced when individual connection holes of the formed connection holes are in a problem is avoided, the polycrystalline silicon region of a shield gate polycrystalline silicon layer is kept away, and the risk of bridging is avoided. The lengths (i.e., widths) of the first and second trench connection units 210 and 220 in the extending direction perpendicular thereto are smaller than the lengths of the second portion 120 in the extending direction perpendicular thereto.
The lengths of the first trench connection unit 210 and the second trench connection unit 220 in the extending direction thereof are greater than or equal to the length occupied by a plurality of adjacent trench units 100 in the direction perpendicular to the extending direction of the trench units 100.
Fig. 4 is a schematic flow chart of a manufacturing method of the power semiconductor device of the present embodiment. As shown in fig. 4, the present embodiment further provides a method for manufacturing a power semiconductor device, including the following steps:
step S1: forming a plurality of grooves on a semiconductor substrate by using a mask plate with the groove layout structure as a mask;
step S2: sequentially forming a first oxide layer and a shielding grid polycrystalline silicon layer in the groove, wherein the first oxide layer covers the inner wall of the groove, the shielding grid polycrystalline silicon layer fills the groove, the height of the first oxide layer is lower than that of the shielding grid polycrystalline silicon layer, and an opening is formed above the first oxide layer;
step S3: forming a second oxide layer on the semiconductor substrate, wherein the second oxide layer wraps the shielding grid polycrystalline silicon layer and exposes the first oxide layer, so that an opening is formed above the first oxide layer;
step S4: and forming a polysilicon layer at the opening, and etching the polysilicon layer by taking the second oxide layer as a mask to form a grid polysilicon layer so as to form the power semiconductor device.
A method for manufacturing a power semiconductor device according to this embodiment will be described in detail with reference to fig. 4 to 5 f.
As shown in fig. 5a and 5b, step S1 is first performed to form a plurality of trenches 100' on the semiconductor substrate 300 by using the mask having the trench layout structure as a mask. Specifically, a plurality of trenches 100 ' are formed on the semiconductor substrate 300 by using a mask having a plurality of trench cells 100 as a mask, and widths of both ends of the trenches 100 ' in an extending direction thereof (a length in a direction perpendicular to the extending direction of the trenches 100 ') are narrower than a width of a middle position thereof. Specifically, as shown in fig. 5a, the widths of the two ends of the trench 100' in the extending direction thereof are less than twice the thickness of the first oxide layer, that is, on the mask having the trench layout structure, the widths of the first portion 110 and the third portion 130 of the trench layout structure are less than twice the thickness of the first oxide layer, and further, the widths of the first trench connection unit 210 and the second trench connection unit 220 are less than twice the thickness of the first oxide layer. As shown in fig. 5b, the width of the trench 100 ' between the two ends of the trench 100 ' in the extending direction (the middle position of the trench 100 ') is greater than twice the thickness of the first oxide layer, that is, the width of the second portion 120 of the trench layout structure on the mask having the trench layout structure is greater than twice the thickness of the first oxide layer. In this embodiment, the trench 100' is, for example, a shield gate trench.
As shown in fig. 5c-5d, next, step S2 is performed to sequentially form a first oxide layer 410 and a shield gate polysilicon layer 510 in the trench 100 ', wherein the first oxide layer 410 covers the inner wall of the trench 100 ', the shield gate polysilicon layer 510 fills the trench 100 ', and the first oxide layer 410 is lower than the shield gate polysilicon layer 510.
The method specifically comprises the following steps:
first, a first oxide layer 410 is deposited in the trench 100 ', the first oxide layer 410 covers the inner wall of the trench 100 ', and at this time, as shown in fig. 5c, since the width of the mask forming the trench 100 ' at the first part 110 and the third part 130 of the trench layout structure and the width of the first trench connecting unit 210 and the second trench connecting unit 220 are less than twice the thickness of the first oxide layer 410, the opening of the trench 100 ' at this position is blocked by the first oxide layer 410, so that the mask forming the trench 100 ' cannot form a shield gate polysilicon layer at the first part 110 and the third part 130 of the trench layout structure and the first trench connecting unit 210 and the second trench connecting unit 220 when the shield gate polysilicon layer is formed in the trench later. As shown in fig. 5d, in the trench 100 'located at the middle of the trench 100' (i.e. the mask forming the trench 100 'is located in the second portion 120 of the trench layout structure), the first oxide layer 410 covers the inner wall of the trench 100', and has a U-shaped cross section. The first oxide layer 410 also covers the semiconductor substrate 300.
Next, a first polysilicon layer is formed in the trench 100 ', filling the trench 100' and covering the first oxide layer 410 on the semiconductor substrate 300. At this time, as shown in fig. 5d, only the middle position of the trench 100 'is filled with the first polysilicon layer, and as shown in fig. 5c, the first polysilicon layer is not filled at both ends of the trench 100'.
Next, the first polysilicon layer on the semiconductor substrate 300 is etched, and the first polysilicon layer in the trench 100' is remained, so as to form a shield gate polysilicon layer 510. In this step, a polysilicon layer is formed only at the middle position of the trench 100' due to the shield gate.
Next, the first oxide layer 410 on the semiconductor substrate 300 is etched, and the first oxide layer 410 of a partial depth in the trench 100' is etched, so that an opening is formed above the first oxide layer 410. In this step, at two ends of the trench 100 ' (i.e. the mask forming the trench 100 ' is on the first part 110 and the third part 130 of the trench layout structure, and the first trench connection unit 210 and the second trench connection unit 220), since the trench in this region is filled with the first oxide layer 410, as shown in fig. 5c, when the first oxide layer 410 of a partial depth is etched, there is no shield gate polysilicon layer 510 at two ends of the trench 100 ', and here only one opening with a shape similar to that of two ends of the trench 100 ' is formed, so that in the subsequent process, only a gate polysilicon layer 520 is formed on the first oxide layer at two ends of the trench 100 '; as shown in fig. 5d, a shield gate polysilicon layer exists in the middle of the trench 100 ', and the first oxide layer 410 surrounds the shield gate polysilicon layer 510, and when the first oxide layer 410 is etched to a partial depth, the opening is annular, so that a gate polysilicon layer 520 and a shield gate polysilicon layer 510 are formed in the middle of the trench 100' in the subsequent process, and the gate polysilicon layer 520 surrounds the shield gate polysilicon layer 510 in an annular shape.
Next, step S3 is performed to form a second oxide layer 420 on the semiconductor substrate 300, where the second oxide layer 420 wraps the exposed shield gate polysilicon layer 510 and exposes the first oxide layer 410, so that there is an opening above the first oxide layer 410, and at this time, the second oxide layer 420 serves as an isolation layer between the shield gate polysilicon layer 510 and a later-formed gate polysilicon layer 520, and also forms a gate oxide layer on the silicon sidewall of the opening, that is, the second oxide layer 420 also covers the silicon sidewall of the opening.
As shown in fig. 5e and 5f, step S4 is performed to form a second polysilicon layer at the opening, and the second polysilicon layer is etched using the second oxide layer 420 as a mask to form a gate polysilicon layer 520, so as to form a power semiconductor device.
In this step, as shown in fig. 5e, openings at two ends of the trench 100' have gate polysilicon layers, but do not have shield gate polysilicon layers, so that a connection hole (contact) can be set at the positions of the first trench connection unit 210 and the second trench connection unit 220 of the mask, and the formed connection hole can be far away from the shield gate polysilicon layers, thereby avoiding the risk of bridging the gate polysilicon layers and the shield gate polysilicon layers, further saving the region defining the connection hole of the mask to the gate polysilicon layers, reducing the process steps, and reducing the process cost. As shown in fig. 5f, the gate polysilicon layer 520 and the shield gate polysilicon layer 510 are isolated by the second oxide layer 420 at the middle position of the trench 100'.
The embodiment also provides a power semiconductor device prepared by the method. As shown in fig. 5e, the two ends of the trench of the power semiconductor device only include the first oxide layer 410, the second oxide layer 420 and the gate polysilicon layer 520 from bottom to top. As shown in fig. 5f, the middle of the trench includes a first oxide layer 410 covering the trench, and a shield gate polysilicon layer 510, a second oxide layer 420, and a gate polysilicon layer 520 in sequence from bottom to top, wherein the first oxide layer 410 wraps the sidewall of the shield gate polysilicon layer 510. The gate polysilicon layer 520 and the shield gate polysilicon layer 510 are in an airplane shape in the trench.
In summary, the power semiconductor device, the manufacturing method thereof and the trench layout structure provided by the invention have the advantages that the trench layout structure comprises a plurality of trench units, a first trench connection unit and a second trench connection unit which are arranged adjacently; the trench unit comprises a first part, a second part and a third part, wherein the first part and the third part are arranged at two sides of the second part along the extension direction of the second part, and the length of the first part and the length of the third part in the extension direction perpendicular to the second part are smaller than that of the second part in the extension direction perpendicular to the second part; the first groove connection unit connects the adjacent first portions, the second groove connection unit connects the adjacent third portions, and the lengths of the first groove connection unit and the second groove connection unit in the direction perpendicular to the extending direction of the second portions are smaller than the lengths of the second portions in the direction perpendicular to the extending direction of the second portions. According to the invention, the lengths of the first part and the third part in the extending direction vertical to the second part are smaller than the length of the second part in the extending direction vertical to the extending direction, so that the shielding grid polycrystalline silicon layer can not be deposited and only the grid polycrystalline silicon layer can be deposited in the grooves at two ends of the power semiconductor device when the power semiconductor device is formed subsequently, and the first groove connecting unit and the second groove connecting unit are provided with the connecting holes (contact), so that the risk of connecting the grid polycrystalline silicon layer and the shielding grid polycrystalline silicon layer is avoided, the mask for defining the region of the connecting holes for connecting the grid polycrystalline silicon layer is saved, the working procedures are reduced, and the process cost is reduced.
In addition, it should be noted that the description of the terms "first", "second", and the like in the specification is only used for distinguishing each component, element, step, and the like in the specification, and is not used for representing a logical relationship or a sequential relationship between each component, element, step, and the like, unless otherwise specified or indicated.
It is to be understood that while the present invention has been described in conjunction with the preferred embodiments thereof, it is not intended to limit the invention to those embodiments. It will be apparent to those skilled in the art from this disclosure that many changes and modifications can be made, or equivalents modified, in the embodiments of the invention without departing from the scope of the invention. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention are still within the scope of the protection of the technical solution of the present invention, unless the contents of the technical solution of the present invention are departed.
Claims (10)
1. A groove layout structure is characterized by comprising a plurality of groove units, a first groove connecting unit and a second groove connecting unit which are arranged adjacently;
the trench unit comprises a first part, a second part and a third part, wherein the first part and the third part are arranged at two sides of the second part along the extension direction of the second part, and the length of the first part and the length of the third part in the extension direction perpendicular to the second part are smaller than that of the second part in the extension direction perpendicular to the second part;
the first groove connecting unit and the second groove connecting unit are used for arranging connecting holes, the first groove connecting unit is connected with the adjacent first parts, the second groove connecting unit is connected with the adjacent third parts, and the length of the first groove connecting unit and the length of the second groove connecting unit in the direction perpendicular to the extending direction of the second parts are smaller than the length of the second parts in the direction perpendicular to the extending direction of the second parts.
2. The trench layout structure of claim 1, wherein the second portion has an elongated shape, and the first portion and the third portion have the same shape and are both regular two-dimensional patterns.
3. The trench layout structure of claim 1, wherein the first portion and the third portion are both rectangular and have the same size.
4. The trench layout structure according to claim 1, wherein the patterns of the first trench connection unit and the second trench connection unit are both long-striped, and the first trench connection unit and the second trench connection unit are both vertically connected to the trench unit.
5. A manufacturing method of a power semiconductor device is characterized by comprising the following steps:
step S1: forming a plurality of trenches on a semiconductor substrate by using a reticle having a trench layout structure according to any one of claims 1 to 4 as a mask;
step S2: sequentially forming a first oxide layer and a shielding grid polycrystalline silicon layer in the groove, wherein the first oxide layer covers the inner wall of the groove, the shielding grid polycrystalline silicon layer fills the groove, the height of the first oxide layer is lower than that of the shielding grid polycrystalline silicon layer, and an opening is formed above the first oxide layer;
step S3: forming a second oxide layer on the semiconductor substrate, wherein the second oxide layer wraps the shielding grid polycrystalline silicon layer and exposes the first oxide layer, so that an opening is formed above the first oxide layer;
step S4: and forming a polysilicon layer at the opening, and etching the polysilicon layer by taking the second oxide layer as a mask to form a grid polysilicon layer so as to form the power semiconductor device.
6. The method for manufacturing a power semiconductor device according to claim 5, wherein the step S1 specifically includes:
and forming a plurality of grooves on the semiconductor substrate by using a mask plate with a plurality of groove units as a mask, wherein the width of two ends of each groove in the extending direction of the groove is narrower than the width of the groove in the middle position in the extending direction of the groove.
7. The method for manufacturing a power semiconductor device according to claim 6, wherein a width of both ends of the trench in an extending direction thereof is less than twice a thickness of the first oxide layer.
8. The method for manufacturing a power semiconductor device according to claim 5, wherein the step S2 specifically comprises the steps of:
depositing a first oxide layer in the trench, the first oxide layer covering an inner wall of the trench at an intermediate position of the trench in an extending direction thereof, the first oxide layer filling the trench at both ends of the trench in the extending direction thereof;
forming a first polysilicon layer in the trench, wherein the first polysilicon layer fills the middle position of the trench and covers a first oxidation layer on the semiconductor substrate;
etching the first polycrystalline silicon layer on the semiconductor substrate, and reserving the first polycrystalline silicon layer in the middle position of the groove to form a shield grid polycrystalline silicon layer;
and etching the first oxide layer on the semiconductor substrate, and etching the first oxide layer with partial depth in the groove, so that the height of the first oxide layer is lower than that of the shield grid polycrystalline silicon layer, and an opening is arranged above the first oxide layer.
9. The method for manufacturing a power semiconductor device according to claim 8, wherein a shield gate polysilicon layer is present at a middle position of the trench in an extending direction thereof, and no shield gate polysilicon layer is present at both ends of the trench in the extending direction thereof.
10. A power semiconductor device prepared by the method for manufacturing a power semiconductor device according to any one of claims 5 to 9, comprising a trench.
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