CN111370404A - Power semiconductor device, manufacturing method thereof and groove layout structure - Google Patents
Power semiconductor device, manufacturing method thereof and groove layout structure Download PDFInfo
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- CN111370404A CN111370404A CN202010301015.7A CN202010301015A CN111370404A CN 111370404 A CN111370404 A CN 111370404A CN 202010301015 A CN202010301015 A CN 202010301015A CN 111370404 A CN111370404 A CN 111370404A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 86
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 25
- 238000000034 method Methods 0.000 claims description 31
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 22
- 239000000758 substrate Substances 0.000 claims description 22
- 229920005591 polysilicon Polymers 0.000 claims description 18
- 238000005530 etching Methods 0.000 claims description 9
- 238000000151 deposition Methods 0.000 claims description 2
- 230000003647 oxidation Effects 0.000 claims description 2
- 238000007254 oxidation reaction Methods 0.000 claims description 2
- 238000010586 diagram Methods 0.000 description 5
- 230000010354 integration Effects 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/66734—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the gate electrode, e.g. to form a trench gate electrode
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
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Abstract
The invention provides a power semiconductor device, a manufacturing method thereof and a trench layout structure, wherein the trench layout structure comprises a plurality of trench units which are adjacently arranged, each trench unit comprises a first part, a second part and a third part, the first part and the third part are arranged on two sides of the second part, and the length of the first part and the length of the third part in the extending direction which is vertical to the second part are smaller than the length of the second part in the extending direction which is vertical to the second part. According to the invention, the lengths of the first part and the third part in the extending direction vertical to the second part are smaller than the length of the second part in the extending direction vertical to the second part, so that the source electrode can not be deposited but only the grid electrode can be deposited in the grooves at two ends of the power semiconductor device when the power semiconductor device is formed subsequently, and the grid electrode can be directly led out from two ends of the groove unit, thereby saving the area specially used for forming a connecting hole for leading out the grid electrode, and improving the effective area utilization rate of the power semiconductor device.
Description
Technical Field
The invention relates to the field of semiconductor integrated circuit manufacturing, in particular to a power semiconductor device, a manufacturing method thereof and a groove structure.
Background
As the degree of integration of semiconductor devices increases, the pitch of integrated circuits also decreases. The layout structure of a Shielded Gate Trench (SGT) in the power semiconductor device occupies a large area, so that the circuit integration level of the power semiconductor device is low, and meanwhile, when the power semiconductor device is prepared subsequently, the process steps are multiple, so that the process cost is high.
Therefore, a trench layout structure is needed to improve the circuit integration of the semiconductor device and simplify the process steps of the power semiconductor device, thereby reducing the process cost.
Disclosure of Invention
The invention provides a power semiconductor device, a manufacturing method thereof and a groove layout structure, and aims to solve the problems.
The invention provides a trench layout structure which comprises a plurality of trench units arranged adjacently, wherein each trench unit comprises a first part, a second part and a third part, the first part and the third part are arranged on two sides of the second part along the extending direction of the second part, and the length of the first part and the length of the third part in the extending direction perpendicular to the second part are smaller than the length of the second part in the extending direction perpendicular to the second part.
Optionally, the second portion is strip-shaped, and the first portion and the third portion are the same in shape and are both regular two-dimensional figures.
Furthermore, the first part and the third part are both rectangular and have the same size.
In another aspect, the present invention provides a method for manufacturing a power semiconductor device, including the steps of:
step S1: forming a plurality of trenches on a semiconductor substrate by using a reticle having a trench layout structure according to any one of claims 1 to 3 as a mask;
step S2: sequentially forming a first oxide layer and a source electrode in the groove, wherein the first oxide layer covers the inner wall of the groove, the source electrode fills the groove, the height of the first oxide layer is lower than that of the source electrode, and an opening is formed above the first oxide layer;
step S3: forming a second oxide layer on the semiconductor substrate, wherein the second oxide layer wraps the source electrode and exposes the first oxide layer, so that an opening is formed above the first oxide layer;
step S4: and forming a polysilicon layer at the opening, and etching the polysilicon layer by taking the second oxide layer as a mask to form a grid so as to form the power semiconductor device.
Optionally, step S1 specifically includes:
and forming a plurality of grooves on the semiconductor substrate by using a mask plate with a plurality of groove units as a mask, wherein the width of two ends of each groove in the extending direction of the groove is narrower than the width of the groove in the middle position in the extending direction of the groove.
Further, the width of both ends of the trench in the extending direction thereof is less than twice the thickness of the first oxide layer.
Optionally, step S2 specifically includes the following steps:
depositing a first oxide layer in the trench, the first oxide layer covering an inner wall of the trench at an intermediate position of the trench in an extending direction thereof, the first oxide layer filling the trench at both ends of the trench in the extending direction thereof;
forming a first polysilicon layer in the trench, wherein the first polysilicon layer fills the middle position of the trench and covers a first oxidation layer on the semiconductor substrate;
etching the first polycrystalline silicon layer on the semiconductor substrate, and reserving the first polycrystalline silicon layer in the middle position of the groove to form a source electrode;
and etching the first oxide layer on the semiconductor substrate, and etching the first oxide layer with partial depth in the groove, so that the height of the first oxide layer is lower than that of the source electrode, and an opening is arranged above the first oxide layer.
Further, a source electrode is present at a middle position of the trench in the extending direction thereof, and no source electrode is present at both ends of the trench in the extending direction thereof.
In another aspect, the invention provides a power semiconductor device, which is prepared by the above method for manufacturing a power semiconductor device and includes a trench.
Optionally, at two ends of the trench, the power semiconductor device includes, from bottom to top, a first oxide layer, a second oxide layer, and a gate.
Compared with the prior art, the invention has the following beneficial effects:
the invention provides a power semiconductor device, a manufacturing method thereof and a trench layout structure, wherein the trench layout structure comprises a plurality of trench units which are adjacently arranged, each trench unit comprises a first part, a second part and a third part, the first part and the third part are arranged on two sides of the second part along the extending direction of the second part, and the length of the first part and the length of the third part in the extending direction which is vertical to the second part are smaller than the length of the second part in the extending direction which is vertical to the second part. According to the invention, the lengths of the first part and the third part in the extending direction vertical to the second part are smaller than the length of the second part in the extending direction vertical to the second part, so that the source electrode can not be deposited but only the grid electrode can be deposited in the grooves at two ends of the power semiconductor device when the power semiconductor device is formed subsequently, and the grid electrode can be directly led out from two ends of the groove unit, thereby saving the area specially used for forming a connecting hole for leading out the grid electrode, and improving the effective area utilization rate of the power semiconductor device.
According to the manufacturing method of the power semiconductor device, the openings at the two ends of the groove are provided with the grids, but the openings do not have the sources, so that the connecting holes can be directly arranged at the two ends of the groove to lead out the grids, and a connecting hole does not need to be arranged in a special area, so that the area specially provided with the connecting holes is saved, and the effective area utilization rate of the power semiconductor device is improved. Meanwhile, the openings at the two ends of the groove are provided with the grids, but the source electrodes are not arranged, so that the risk of connecting the grids and the source electrodes in a bridge mode is reduced, the connecting holes can be formed in the positions, masks for defining the areas where the connecting holes are connected with the grids are saved, the processes are reduced, and the process cost is reduced.
Drawings
FIG. 1 is a schematic structural diagram of an SGT layout structure in the prior art;
FIG. 2 is a schematic diagram of a prior art power semiconductor device;
fig. 3 is a schematic structural diagram of a trench layout structure according to an embodiment of the present invention;
fig. 4 is a schematic flow chart illustrating a method for manufacturing a power semiconductor device according to an embodiment of the invention;
fig. 5a to 5f are schematic structural diagrams of steps of a method for manufacturing a power semiconductor device according to an embodiment of the present invention.
Description of reference numerals:
in FIGS. 1-2:
10-trench cells; a-a preset area;
FIG. 3-
100-trench cells; 110-a first portion; 120-a second portion; 130-a third portion;
100' -a trench;
200-a semiconductor substrate;
310-a first oxide layer; 320-a second oxide layer;
410-a source; 420-gate.
Detailed Description
As shown in fig. 1, each trench unit 10 of the SGT layout structure in the prior art is in a long strip shape, when the SGT of the structure forms a power semiconductor device (as shown in fig. 2) in the subsequent process, a special preset region a needs to be reserved to set a connection hole to lead out the gate due to the narrow width of the gate of the power semiconductor device, a special photomask is needed to define the preset region a in the whole process, the process cost is high, and the effective area utilization rate of the power semiconductor device is low.
Based on the above research, the invention provides a power semiconductor device, a manufacturing method thereof and a trench layout structure, wherein the trench layout structure comprises a plurality of trench units which are adjacently arranged, each trench unit comprises a first part, a second part and a third part, the first part and the third part are arranged on two sides of the second part along the extending direction of the second part, and the lengths of the first part and the third part in the extending direction perpendicular to the second part are smaller than the lengths of the second part in the extending direction perpendicular to the second part. According to the invention, the lengths of the first part and the third part in the extending direction vertical to the second part are smaller than the length of the second part in the extending direction vertical to the second part, so that the source electrode can not be deposited but only the grid electrode can be deposited in the grooves at two ends of the power semiconductor device when the power semiconductor device is formed subsequently, and the grid electrode can be directly led out from two ends of the groove unit, thereby saving the area specially used for forming a connecting hole for leading out the grid electrode, and improving the effective area utilization rate of the power semiconductor device.
According to the manufacturing method of the power semiconductor device, the openings at the two ends of the groove are provided with the grids, but the openings do not have the sources, so that the connecting holes can be directly arranged at the two ends of the groove to lead out the grids, and a connecting hole does not need to be arranged in a special area, so that the area specially provided with the connecting holes is saved, and the effective area utilization rate of the power semiconductor device is improved. Meanwhile, the openings at the two ends of the groove are provided with the grids, but the source electrodes are not arranged, so that the risk of connecting the grids and the source electrodes in a bridge mode is reduced, the connecting holes can be formed in the positions, masks for defining the areas where the connecting holes are connected with the grids are saved, the processes are reduced, and the process cost is reduced.
A power semiconductor device, a method for manufacturing the same, and a trench layout structure according to the present invention will be described in further detail below. The present invention will now be described in more detail with reference to the accompanying drawings, in which preferred embodiments of the invention are shown, it being understood that one skilled in the art may modify the invention herein described while still achieving the advantageous effects of the invention. Accordingly, the following description should be construed as broadly as possible to those skilled in the art and not as limiting the invention.
In the interest of clarity, not all features of an actual implementation are described. In the following description, well-known functions or constructions are not described in detail since they would obscure the invention in unnecessary detail. It will of course be appreciated that in the development of any such actual embodiment, numerous implementation-specific details must be set forth in order to achieve the developer's specific goals, such as compliance with system-related and business-related constraints, which will vary from one implementation to another. Moreover, it will be appreciated that such a development effort might be complex and time-consuming, but would nevertheless be a routine undertaking for those of ordinary skill in the art.
In order to make the objects and features of the present invention more comprehensible, embodiments of the present invention are described in detail below with reference to the accompanying drawings. It is to be noted that the drawings are in a very simplified form and are all used in a non-precise ratio for the purpose of facilitating and distinctly aiding in the description of the embodiments of the invention.
Fig. 3 is a schematic structural diagram of the trench layout structure according to this embodiment. As shown in fig. 3, the present embodiment provides a trench layout structure, for example, a Shielded Gate Trench (SGT) layout structure. The trench layout structure includes a plurality of trench cells 100 arranged adjacently, each trench cell 100 includes, for example, a first portion 110, a second portion 120, and a third portion 130, the first portion 110 and the third portion 130 are arranged on two sides of the second portion 120, specifically, the second portion 120 is, for example, in an elongated shape, the first portion 110 and the third portion 130 are arranged on two sides of the second portion 120 along an extending direction of the second portion 120, and the first portion 110 and the third portion 130 are, for example, in the same shape, for example, in a regular two-dimensional pattern, specifically, in a rectangular shape, a circular shape, a polygonal shape, and the like, and have the same size. Of course, the first portion 110 and the third portion 130 may have different shapes and sizes. In this embodiment, the first portion 110 and the third portion 130 are, for example, rectangular. The lengths of the first portion 110 and the third portion 130 in the extending direction perpendicular to the second portion 120 are smaller than the length of the second portion 120 in the extending direction perpendicular to the extending direction, so that the two ends of the trench unit 100 in the extending direction (i.e. the positions of the first portion 110 and the third portion 130) are narrower than the width of the middle portion (i.e. the second portion 120), so that the source electrode cannot be deposited but only the gate electrode can be deposited in the trenches at the two ends when the power semiconductor device is formed subsequently, and therefore the gate electrode can be directly led out from the two ends of the trench unit 100, a region where a connection hole for leading out the gate electrode is specially formed is saved, and the effective area utilization rate of the power semiconductor device is improved.
Fig. 4 is a schematic flow chart of a manufacturing method of the power semiconductor device of the present embodiment. As shown in fig. 4, the present embodiment further provides a method for manufacturing a power semiconductor device, including the following steps:
step S1: forming a plurality of grooves on a semiconductor substrate by using a mask plate with the groove layout structure as a mask;
step S2: sequentially forming a first oxide layer and a source electrode in the groove, wherein the first oxide layer covers the inner wall of the groove, the source electrode fills the groove, the height of the first oxide layer is lower than that of the source electrode, and an opening is formed above the first oxide layer;
step S3: forming a second oxide layer on the semiconductor substrate, wherein the second oxide layer wraps the source electrode and exposes the first oxide layer, so that an opening is formed above the first oxide layer;
step S4: and forming a polysilicon layer at the opening, and etching the polysilicon layer by taking the second oxide layer as a mask to form a grid so as to form the power semiconductor device.
A method for manufacturing a power semiconductor device according to this embodiment will be described in detail with reference to fig. 4 to 5 f.
As shown in fig. 5a and 5b, step S1 is first performed to form a plurality of trenches 100' on the semiconductor substrate 200 by using the mask having the trench layout structure as a mask. Specifically, a plurality of trenches 100 ' are formed on a semiconductor substrate 200 by using a mask having a plurality of trench cells 100 as a mask, and widths of both ends of the trenches 100 ' in an extending direction thereof (a length in a direction perpendicular to the extending direction of the trenches 100 ') are narrower than a width of a middle position thereof. Specifically, as shown in fig. 5a, the width of the trench 100' at both ends in the extending direction thereof is less than twice the thickness of the first oxide layer. As shown in fig. 5b, the width of the trench 100 'between both ends in the extending direction thereof (the middle position of the trench 100') is greater than twice the thickness of the first oxide layer. In this embodiment, the trench 100' is, for example, a shield gate trench.
As shown in fig. 5c-5d, next, step S2 is performed to sequentially form a first oxide layer 310 and a source electrode 410 in the trench 100 ', wherein the first oxide layer 310 covers the inner wall of the trench 100 ', the source electrode 410 fills the trench 100 ', and the height of the first oxide layer 310 is lower than that of the source electrode 410.
The method specifically comprises the following steps:
first, a first oxide layer 310 is deposited in the trench 100 ', and the first oxide layer 310 covers the inner wall of the trench 100', and at this time, as shown in fig. 5c, since the width of both ends of the trench 100 'in the extending direction thereof is less than twice the thickness of the first oxide layer 310, the opening of the trench 100' is blocked by the first oxide layer 310 on the sidewall at the opening of the trench 100 ', so that when a source is subsequently formed in the trench, the source cannot be formed at both ends of the trench 100' in the extending direction thereof. As shown in fig. 5d, in the trench 100 ' at the middle position of the trench 100 ', the first oxide layer 310 covers the inner wall of the trench 100 ' and has a U-shaped cross section. The first oxide layer 310 also covers the semiconductor substrate 200.
Next, a first polysilicon layer is formed in the trench 100 ', filling the trench 100' and covering the first oxide layer 310 on the semiconductor substrate 200. At this time, as shown in fig. 5d, only the middle position of the trench 100 'is filled with the first polysilicon layer, and as shown in fig. 5c, the first polysilicon layer is not filled at both ends of the trench 100'.
Next, the first polysilicon layer on the semiconductor substrate 200 is etched, and the first polysilicon layer in the trench 100' is remained to form a source 410. In this step, the source is formed only in the middle of the trench 100'.
Next, the first oxide layer 310 on the semiconductor substrate 200 is etched, and the first oxide layer 310 in the trench 100' is etched to a partial depth, so that an opening is formed above the first oxide layer 310. In this step, since the trench in this region is filled with the first oxide layer 310 at the two ends of the trench 100 ', as shown in fig. 5c, when the first oxide layer 310 is etched to a partial depth, there is no source 410 at the two ends of the trench 100', and only one opening having a shape similar to that of the two ends of the trench 100 'is formed, so that in the subsequent process, only the gate 420 is formed on the first oxide layer at the two ends of the trench 100'; as shown in fig. 5d, a source electrode is located in the middle of the trench 100 ', and the first oxide layer 310 surrounds the source electrode 410, and when the first oxide layer 310 is etched to a partial depth, the opening is shaped like a ring, so that in the subsequent process, a gate electrode 420 and a source electrode 410 are formed in the middle of the trench 100', and the gate electrode 420 surrounds the source electrode 410 like a ring.
Next, step S3 is performed to form a second oxide layer 320 on the semiconductor substrate 200, where the second oxide layer 320 wraps the exposed source 410 and exposes the first oxide layer 310, so that there is an opening above the first oxide layer 310, and at this time, the second oxide layer 320 serves as an isolation layer between the source 410 and the gate 410 formed later, and it also forms a gate oxide layer on the silicon sidewall of the opening, that is, the second oxide layer 320 also covers the silicon sidewall of the opening.
As shown in fig. 5e and 5f, step S4 is performed to form a second polysilicon layer at the opening, and the second polysilicon layer is etched using the second oxide layer 320 as a mask to form a gate 420, so as to form a power semiconductor device.
In this step, as shown in fig. 5e, the openings at the two ends of the trench 100 'have the gate polysilicon layer, but do not have the source, so that the connection holes can be directly arranged at the two ends of the trench 100' to lead out the gate, and no special area is needed to arrange a connection hole, thereby saving the area specially provided with the connection holes and improving the effective area utilization rate of the power semiconductor device. Meanwhile, the openings at the two ends of the groove are provided with the grids, but the source electrodes are not arranged, so that the risk of connecting the grids and the source electrodes in a bridge mode is reduced, the connecting holes can be formed in the positions, masks for defining the areas where the connecting holes are connected with the grids are saved, the processes are reduced, and the process cost is reduced. As shown in fig. 5f, in the middle of the trench 100', the gate 420 and the source 410 are isolated by the second oxide layer 320.
The embodiment also provides a power semiconductor device prepared by the method. As shown in fig. 5e, the two ends of the trench of the power semiconductor device only include the first oxide layer 310, the second oxide layer 320 and the gate 420 from bottom to top. As shown in fig. 5f, the trench includes a first oxide layer 310 covering the trench, and a source 410, a second oxide layer 320, and a gate 420 sequentially from bottom to top, wherein the first oxide layer 310 wraps a sidewall of the source 410. The gate 420 and source 410 are in the shape of an airplane in the trench.
In summary, the trench layout structure includes a plurality of trench units arranged adjacently, each trench unit includes a first portion, a second portion and a third portion, the first portion and the third portion are arranged on two sides of the second portion, and the lengths of the first portion and the third portion in the extending direction perpendicular to the second portion are smaller than the length of the second portion in the extending direction perpendicular to the second portion. According to the invention, the lengths of the first part and the third part in the extending direction vertical to the second part are smaller than the length of the second part in the extending direction vertical to the second part, so that the source electrode can not be deposited but only the grid electrode can be deposited in the grooves at two ends of the power semiconductor device when the power semiconductor device is formed subsequently, and the grid electrode can be directly led out from two ends of the groove unit, thereby saving the area specially used for forming a connecting hole for leading out the grid electrode, and improving the effective area utilization rate of the power semiconductor device.
According to the manufacturing method of the power semiconductor device, the openings at the two ends of the groove are provided with the grids, but the openings do not have the sources, so that the connecting holes can be directly arranged at the two ends of the groove to lead out the grids, and a connecting hole does not need to be arranged in a special area, so that the area specially provided with the connecting holes is saved, and the effective area utilization rate of the power semiconductor device is improved. Meanwhile, the openings at the two ends of the groove are provided with the grids, but the source electrodes are not arranged, so that the risk of connecting the grids and the source electrodes in a bridge mode is reduced, the connecting holes can be formed in the positions, masks for defining the areas where the connecting holes are connected with the grids are saved, the processes are reduced, and the process cost is reduced.
In addition, it should be noted that the description of the terms "first", "second", and the like in the specification is only used for distinguishing each component, element, step, and the like in the specification, and is not used for representing a logical relationship or a sequential relationship between each component, element, step, and the like, unless otherwise specified or indicated.
It is to be understood that while the present invention has been described in conjunction with the preferred embodiments thereof, it is not intended to limit the invention to those embodiments. It will be apparent to those skilled in the art from this disclosure that many changes and modifications can be made, or equivalents modified, in the embodiments of the invention without departing from the scope of the invention. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention are still within the scope of the protection of the technical solution of the present invention, unless the contents of the technical solution of the present invention are departed.
Claims (10)
1. The utility model provides a trench layout structure, its characterized in that includes a plurality of adjacent trench units that set up, the trench unit includes first portion, second portion and third portion, first portion and third portion set up the second portion is along its extending direction's both sides, first portion and third portion are at the perpendicular to the length of second portion on the extending direction of second portion is less than the length of second portion on the perpendicular to its extending direction.
2. The trench layout structure of claim 1, wherein the second portion has an elongated shape, and the first portion and the third portion have the same shape and are both regular two-dimensional patterns.
3. The trench layout structure of claim 1, wherein the first portion and the third portion are both rectangular and have the same size.
4. A manufacturing method of a power semiconductor device is characterized by comprising the following steps:
step S1: forming a plurality of trenches on a semiconductor substrate by using a reticle having a trench layout structure according to any one of claims 1 to 3 as a mask;
step S2: sequentially forming a first oxide layer and a source electrode in the groove, wherein the first oxide layer covers the inner wall of the groove, the source electrode fills the groove, the height of the first oxide layer is lower than that of the source electrode, and an opening is formed above the first oxide layer;
step S3: forming a second oxide layer on the semiconductor substrate, wherein the second oxide layer wraps the source electrode and exposes the first oxide layer, so that an opening is formed above the first oxide layer;
step S4: and forming a polysilicon layer at the opening, and etching the polysilicon layer by taking the second oxide layer as a mask to form a grid so as to form the power semiconductor device.
5. The method for manufacturing a power semiconductor device according to claim 4, wherein the step S1 specifically includes:
and forming a plurality of grooves on the semiconductor substrate by using a mask plate with a plurality of groove units as a mask, wherein the width of two ends of each groove in the extending direction of the groove is narrower than the width of the groove in the middle position in the extending direction of the groove.
6. The method for manufacturing a power semiconductor device according to claim 5, wherein a width of both ends of the trench in an extending direction thereof is less than twice a thickness of the first oxide layer.
7. The method for manufacturing a power semiconductor device according to claim 4, wherein the step S2 specifically comprises the steps of:
depositing a first oxide layer in the trench, the first oxide layer covering an inner wall of the trench at an intermediate position in an extending direction of the trench, the first oxide layer filling the trench at both ends of the trench in the extending direction thereof;
forming a first polysilicon layer in the trench, wherein the first polysilicon layer fills the middle position of the trench and covers a first oxidation layer on the semiconductor substrate;
etching the first polycrystalline silicon layer on the semiconductor substrate, and reserving the first polycrystalline silicon layer in the middle position of the groove to form a source electrode;
and etching the first oxide layer on the semiconductor substrate, and etching the first oxide layer with partial depth in the groove, so that the height of the first oxide layer is lower than that of the source electrode, and an opening is arranged above the first oxide layer.
8. The method for manufacturing a power semiconductor device according to claim 7, wherein a source electrode is present at a middle position of the trench in an extending direction thereof, and no source electrode is present at both ends of the trench in the extending direction thereof.
9. A power semiconductor device prepared by the method for manufacturing a power semiconductor device according to any one of claims 4 to 8, comprising a trench.
10. The power semiconductor device according to claim 9, wherein the power semiconductor device comprises a first oxide layer, a second oxide layer and a gate from bottom to top at both ends of the trench.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010301015.7A CN111370404A (en) | 2020-04-16 | 2020-04-16 | Power semiconductor device, manufacturing method thereof and groove layout structure |
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| CN112310069A (en) * | 2020-09-18 | 2021-02-02 | 上海华虹宏力半导体制造有限公司 | Layout structure of shielded gate trench type device and manufacturing method thereof |
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| CN103151380A (en) * | 2013-02-02 | 2013-06-12 | 张家港凯思半导体有限公司 | Groove-type semiconductor power device, manufacture method thereof and terminal protective structure |
| US20170294518A1 (en) * | 2016-04-06 | 2017-10-12 | Rohm Co., Ltd. | Semiconductor device and method for manufacturing the same |
| CN107785273A (en) * | 2016-08-31 | 2018-03-09 | 无锡华润上华科技有限公司 | Semiconductor devices and its manufacture method |
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