CN111370404A - A power semiconductor device, its manufacturing method, and trench layout structure - Google Patents

Abstract

The present invention provides a power semiconductor device, a manufacturing method thereof, and a trench layout structure. The trench layout structure includes a plurality of adjacently arranged trench units. The trench unit includes a first part, a second part and a third part. The first part and the third part are arranged on both sides of the second part, and the lengths of the first part and the third part in the extending direction perpendicular to the second part are smaller than the length of the second part in the extending direction perpendicular thereto. According to the present invention, the length of the first part and the third part in the extension direction perpendicular to the second part is smaller than the length of the second part in the extension direction perpendicular to the extension direction, so that when the power semiconductor device is subsequently formed, in the trenches at both ends of the power semiconductor device The source electrode cannot be deposited, but only the gate electrode can be deposited, so that the gate electrode can be directly drawn out from both ends of the trench unit, thereby saving the area where the connection hole for the gate electrode is specially formed, and improving the effective area utilization of the power semiconductor device Rate.

Description

A power semiconductor device, its manufacturing method, and trench layout structure

technical field

The invention relates to the field of semiconductor integrated circuit manufacturing, in particular to a power semiconductor device, a manufacturing method thereof, and a trench structure.

Background technique

As the integration degree of semiconductor devices becomes higher and higher, the pitch of integrated circuits becomes smaller and smaller. The layout structure of the shielded gate trench (SGT, Split gate trench) in the power semiconductor device occupies a large area, which makes the circuit integration of the power semiconductor device low. Its process cost is high.

Therefore, there is a need for a trench layout structure to improve the circuit integration of a semiconductor device and simplify the process steps of the power semiconductor device, thereby reducing the process cost.

SUMMARY OF THE INVENTION

The present invention provides a power semiconductor device, a manufacturing method thereof, and a trench layout structure to solve the above problems.

The present invention provides a trench layout structure, comprising a plurality of adjacent trench units, the trench units include a first part, a second part and a third part, the first part and the third part are arranged on the On both sides of the second part along its extending direction, the lengths of the first part and the third part in the extending direction perpendicular to the second part are smaller than the length of the second part in the extending direction perpendicular thereto.

Optionally, the second part is in the shape of a long strip, and the first part and the third part have the same shape and are both regular two-dimensional figures.

Further, the first part and the third part are both rectangular and have the same size.

On the other hand, the present invention provides a method for manufacturing a power semiconductor device, comprising the following steps:

Step S1: forming a plurality of trenches on the semiconductor substrate by using the mask having the trench layout structure according to any one of claims 1-3 as a mask;

Step S2: forming a first oxide layer and a source electrode in sequence in the trench, the first oxide layer covers the inner wall of the trench, the source electrode fills the trench, and the first oxide layer covers the inner wall of the trench, and the source electrode fills the trench. The height of the oxide layer is lower than the height of the source electrode, and has an opening above the first oxide layer;

Step S3: forming a second oxide layer on the semiconductor substrate, the second oxide layer wraps the source electrode, and exposes the first oxide layer, so that there is an opening above the first oxide layer;

Step S4: forming a polysilicon layer at the opening, and using the second oxide layer as a mask to etch the polysilicon layer to form a gate, thereby forming a power semiconductor device.

Optionally, step S1 specifically includes:

Several trenches are formed on the semiconductor substrate by using a mask having several trench units as a mask, and the widths of both ends of the trenches in the extending direction thereof are narrower than those along the extending direction of the trenches. the width in the middle of the .

Further, the width of both ends of the trench in the extending direction is less than twice the thickness of the first oxide layer.

Optionally, step S2 specifically includes the following steps:

A first oxide layer is deposited in the trench, and at an intermediate position of the trench along its extending direction, the first oxide layer covers the inner wall of the trench, in the extending direction of the trench At both ends of the upper part, the first oxide layer fills the trench;

forming a first polysilicon layer in the trench, the first polysilicon layer filling the middle of the trench and covering the first oxide layer on the semiconductor substrate;

etching the first polysilicon layer on the semiconductor substrate and leaving the first polysilicon layer in the middle of the trench to form a source electrode;

Etching the first oxide layer on the semiconductor substrate, and etching the first oxide layer at a partial depth in the trench, so that the height of the first oxide layer is lower than the source electrode , and has an opening above the first oxide layer.

Further, there is a source electrode at a middle position of the trench along its extending direction, and there is no source electrode at both ends of the trench along its extending direction.

In yet another aspect, the present invention provides a power semiconductor device, which is prepared by the above-mentioned method for manufacturing a power semiconductor device, and includes a trench.

Optionally, at both ends of the trench, the power semiconductor device includes a first oxide layer, a second oxide layer and a gate from bottom to top.

Compared with the prior art, the present invention has the following beneficial effects:

The present invention provides a power semiconductor device, a manufacturing method thereof, and a trench layout structure, wherein the trench layout structure includes a plurality of adjacently arranged trench units, and the trench units include a first part, a second part and a third part part, the first part and the third part are arranged on both sides of the second part along the extending direction thereof, and the lengths of the first part and the third part in the extending direction perpendicular to the second part are smaller than the length of the second part The length of the second portion in a direction perpendicular to its extension. According to the present invention, the length of the first part and the third part in the extension direction perpendicular to the second part is smaller than the length of the second part in the extension direction perpendicular to the extension direction, so that when the power semiconductor device is subsequently formed The source electrode cannot be deposited in the trenches at both ends, but only the gate electrode can be deposited, so that the gate electrode can be directly drawn out from both ends of the trench unit, thereby saving the area for forming the connection hole for the gate electrode and improving the power. Effective area utilization of semiconductor devices.

In a method for manufacturing a power semiconductor device provided by the present invention, the openings at both ends of the trench have gates but no sources, so that connecting holes can be directly provided at both ends of the trench to connect the above-mentioned The gate is drawn out, and there is no need to set a connection space in a special area, thereby saving the area where the connection hole is specially set, and improving the effective area utilization rate of the power semiconductor device. At the same time, since the openings at both ends of the trench have gates but not sources, the risk of bridging the gates and the sources is reduced, so holes can be connected there, thereby saving the need to define connections The mask of the region where the hole is connected to the gate also reduces the number of processes and reduces the process cost.

Description of drawings

Fig. 1 is the structural representation of SGT layout structure in the prior art;

2 is a schematic structural diagram of a power semiconductor device in the prior art;

3 is a schematic structural diagram of a trench layout structure according to an embodiment of the present invention;

4 is a schematic flowchart of a method for fabricating a power semiconductor device according to an embodiment of the present invention;

5a-5f are schematic structural diagrams of steps of a method for fabricating a power semiconductor device according to an embodiment of the present invention.

Description of reference numbers:

In Figure 1-2:

10-groove unit; A-preset area;

image 3-

100 - trench unit; 110 - first part; 120 - second part; 130 - third part;

100'-groove;

200-semiconductor substrate;

310-first oxide layer; 320-second oxide layer;

410-source; 420-gate.

Detailed ways

As shown in FIG. 1 , each trench unit 10 of the SGT layout structure in the prior art is in the shape of a long strip. When the SGT of this structure is subsequently formed into a power semiconductor device (as shown in FIG. 2 ), due to the gate of the power semiconductor device The width of the pole is narrow, so it is necessary to reserve a special preset area A to set the connection holes to lead out the gate. In the whole process, a special mask is needed to define the preset area A, and the process cost is high. , while the effective area utilization of the power semiconductor device is low.

Based on the above research, the present invention provides a power semiconductor device, a manufacturing method thereof, and a trench layout structure, wherein the trench layout structure includes a plurality of adjacently disposed trench units, and the trench unit includes a first part, a second part and a third part, the first part and the third part are arranged on both sides of the second part along its extension direction, the first part and the third part are perpendicular to the extension direction of the second part The length is smaller than the length of the second portion in a direction perpendicular to its extension. According to the present invention, the length of the first part and the third part in the extension direction perpendicular to the second part is smaller than the length of the second part in the extension direction perpendicular to the extension direction, so that when the power semiconductor device is subsequently formed The source electrode cannot be deposited in the trenches at both ends, but only the gate electrode can be deposited, so that the gate electrode can be directly drawn out from both ends of the trench unit, thereby saving the area for forming the connection hole for the gate electrode and improving the power. Effective area utilization of semiconductor devices.

In a method for manufacturing a power semiconductor device provided by the present invention, the openings at both ends of the trench have gates but no sources, so that connecting holes can be directly provided at both ends of the trench to connect the above-mentioned The gate is drawn out, and there is no need to set a connection space in a special area, thereby saving the area where the connection hole is specially set, and improving the effective area utilization rate of the power semiconductor device. At the same time, since the openings at both ends of the trench have gates but not sources, the risk of bridging the gates and the sources is reduced, so holes can be connected there, thereby saving the need to define connections The mask of the region where the hole is connected to the gate also reduces the number of processes and reduces the process cost.

A power semiconductor device, a manufacturing method thereof, and a trench layout structure of the present invention will be further described in detail below. The present invention will be described in more detail below with reference to the accompanying drawings, in which preferred embodiments of the invention are shown, and it should be understood that those skilled in the art can modify the invention described herein and still achieve the advantageous effects of the invention. Therefore, the following description should be construed as widely known to those skilled in the art and not as a limitation of the present invention.

In the interest of clarity, not all features of an actual embodiment are described. In the following description, well-known functions or constructions are not described in detail since they would obscure the invention with unnecessary detail. It should be recognized that in the development of any actual embodiment, a number of implementation details must be made to achieve the developer's specific goals, such as changing from one embodiment to another in accordance with system-related or business-related constraints. Additionally, it should be appreciated that such a development effort may be complex and time consuming, but would be merely routine for those skilled in the art.

In order to make the objects and features of the present invention more clearly understood, the specific embodiments of the present invention will be further described below with reference to the accompanying drawings. It should be noted that, the accompanying drawings are all in a very simplified form and use imprecise ratios, and are only used to facilitate and clearly assist the purpose of explaining the embodiments of the present invention.

FIG. 3 is a schematic structural diagram of the trench layout structure of the present embodiment. As shown in FIG. 3 , this embodiment provides a trench layout structure, and the trench layout structure is, for example, a shielded gate trench (SGT, Split gate trench) layout structure. The trench layout structure includes several adjacent trench units 100, each of the trench units 100 includes, for example, a first portion 110, a second portion 120 and a third portion 130, the first portion 110 and the third portion The parts 130 are arranged on both sides of the second part 120 . Specifically, the second part 120 is, for example, a long strip, and the first part 110 and the third part 130 are along the extending direction of the second part 120 . are arranged on both sides of the second part 120, and the first part 110 and the third part 130 are, for example, the same shape, for example, both are regular two-dimensional figures, such as rectangles, circles, polygons, etc. same. Of course, the first part 110 and the third part 130 may also have different shapes and sizes. In this embodiment, the first part 110 and the third part 130 are, for example, rectangular. The lengths of the first part 110 and the third part 130 in the extension direction perpendicular to the second part 120 are smaller than the length of the second part 120 in the extension direction perpendicular thereto, so that the trench unit 100 is The two ends in the extending direction (that is, the first part 110 and the third part 130 ) are narrower than the width of the middle part (that is, the second part 120 ), so that when the power semiconductor device is subsequently formed, the two ends are The source electrode cannot be deposited in the trench, but only the gate electrode can be deposited, so that the gate electrode can be directly drawn out from both ends of the trench unit 100, thereby saving the area where the connection hole for the gate electrode is specially formed, and improving the power semiconductor device. effective area utilization.

FIG. 4 is a schematic flowchart of a method for fabricating a power semiconductor device according to the present embodiment. As shown in FIG. 4 , this embodiment also provides a method for fabricating a power semiconductor device, including the following steps:

Step S1: forming a plurality of trenches on the semiconductor substrate by using the reticle having the trench layout structure as a mask;

Step S2: forming a first oxide layer and a source electrode in sequence in the trench, the first oxide layer covers the inner wall of the trench, the source electrode fills the trench, and the first oxide layer covers the inner wall of the trench, and the source electrode fills the trench. The height of the oxide layer is lower than the height of the source electrode, and has an opening above the first oxide layer;

Step S3: forming a second oxide layer on the semiconductor substrate, the second oxide layer wraps the source electrode, and exposes the first oxide layer, so that there is an opening above the first oxide layer;

Step S4: forming a polysilicon layer at the opening, and using the second oxide layer as a mask to etch the polysilicon layer to form a gate, thereby forming a power semiconductor device.

The method for fabricating a power semiconductor device provided in this embodiment will be described in detail below with reference to FIGS. 4-5f.

As shown in FIG. 5a and FIG. 5b, step S1 is first performed, and a plurality of trenches 100' are formed on the semiconductor substrate 200 by using the mask having the trench layout structure as a mask. Specifically, several trenches 100' are formed on the semiconductor substrate 200 by using a mask having a plurality of the trench units 100 as a mask. The length in the extending direction of the groove 100') is narrower than the width in the middle position. Specifically, as shown in Fig. 5a, the width of both ends of the trench 100' in the extending direction thereof is less than twice the thickness of the first oxide layer. As shown in FIG. 5b, the width of the trench 100' between two ends in the extending direction (the middle position of the trench 100') is greater than twice the thickness of the first oxide layer. In this embodiment, the trench 100' is, for example, a shielded gate trench.

As shown in FIGS. 5 c to 5 d , step S2 is performed next, and a first oxide layer 310 and a source electrode 410 are sequentially formed in the trench 100 ′, and the first oxide layer 310 covers the inner wall of the trench 100 ′. , the source electrode 410 fills the trench 100 ′, and the height of the first oxide layer 310 is lower than the height of the source electrode 410 .

This step specifically includes the following steps:

First, a first oxide layer 310 is deposited in the trench 100 ′, and the first oxide layer 310 covers the inner wall of the trench 100 ′. At this time, as shown in FIG. 5 c , since the trench 100 ' the width of both ends in the extending direction is less than twice the thickness of the first oxide layer 310, so that the opening of the trench 100' is blocked by the first oxide layer 310 on the sidewall of the opening of the trench 100' , so that when the source electrode is subsequently formed in the trench, the source electrode cannot be formed at both ends of the trench 100 ′ in the extending direction thereof. As shown in FIG. 5d, in the trench 100' at the middle position of the trench 100', the first oxide layer 310 covers the inner wall of the trench 100', and its cross section is U-shaped. The first oxide layer 310 also covers the semiconductor substrate 200 .

Next, a first polysilicon layer is formed in the trench 100', the first polysilicon layer fills the trench 100' and covers the first oxide layer 310 on the semiconductor substrate 200. At this time, as shown in FIG. 5d , only the middle position of the trench 100 ′ is filled with the first polysilicon layer, and as shown in FIG. 5 c , the two ends of the trench 100 ′ are not filled with the first polysilicon layer. the first polysilicon layer.

Next, the first polysilicon layer on the semiconductor substrate 200 is etched, and the first polysilicon layer in the trench 100' is retained to form a source electrode 410. In this step, since the source electrode is formed only in the middle position of the trench 100'.

Next, the first oxide layer 310 on the semiconductor substrate 200 is etched, and the first oxide layer 310 at a partial depth in the trench 100 ′ is etched, so that the first oxide layer 310 There is an opening at the top. In this step, since the trenches in this region are filled with the first oxide layer 310 at both ends of the trench 100 ′, as shown in FIG. There is no source electrode 410 at both ends of the trench 100', and only an opening with a shape similar to the two ends of the trench 100' is formed here, so that in the subsequent process, the trench 100' Only the gate electrode 420 is formed on the first oxide layer at both ends of the trench 100 ; as shown in FIG. 5d , there is a source electrode at the middle position of the trench 100 ′, and the first oxide layer 310 surrounds the source electrode 410, when the first oxide layer 310 is etched at a partial depth, the opening here is annular, so that in the subsequent process, a gate electrode 420 and a source electrode are formed at the middle position of the trench 100' 410 , the gate electrode 420 surrounds the source electrode 410 in a ring shape.

Next, step S3 is performed to form a second oxide layer 320 on the semiconductor substrate 200, the second oxide layer 320 wraps the exposed source electrode 410, and exposes the first oxide layer 310, so that There is an opening above the first oxide layer 310. At this time, the second oxide layer 320 serves as an isolation layer between the source electrode 410 and the gate electrode 410 formed later, and is also formed on the silicon sidewall of the opening. The gate oxide layer, that is, the second oxide layer 320 also covers the silicon sidewall of the opening.

As shown in FIG. 5e and FIG. 5f, step S4 is performed next, a second polysilicon layer is formed at the opening, and the second polysilicon layer is etched using the second oxide layer 320 as a mask , to form the gate 420, thereby forming a power semiconductor device.

In this step, as shown in Figure 5e, the openings at both ends of the trench 100' have gate polysilicon layers, but no source, so that connections can be made directly at both ends of the trench 100' Holes are used to lead out the gates, and there is no need to set connection holes in a special area, thereby saving the area where the connection holes are specially arranged, and improving the effective area utilization rate of the power semiconductor device. At the same time, since the openings at both ends of the trench have gates but not sources, the risk of bridging the gates and the sources is reduced, so holes can be connected there, thereby saving the need to define connections The mask of the region where the hole is connected to the gate also reduces the number of processes and reduces the process cost. As shown in FIG. 5f, at the middle position of the trench 100', the gate electrode 420 and the source electrode 410 are isolated by the second oxide layer 320.

This embodiment also provides a power semiconductor device prepared by the above method. As shown in FIG. 5e , two ends of the trench of the power semiconductor device only include the first oxide layer 310 , the second oxide layer 320 and the gate electrode 420 from bottom to top. As shown in FIG. 5f, a first oxide layer 310 covering the trench is included in the middle of the trench, and a source electrode 410, a second oxide layer 320 and a gate electrode 420 are included in sequence from bottom to top, the first oxide layer 310 wraps the sidewall of the source electrode 410 . The gate 420 and source 410 are in the shape of an airplane in the trench.

In summary, the present invention provides a power semiconductor device, a manufacturing method thereof, and a trench layout structure, wherein the trench layout structure includes a plurality of adjacently disposed trench units, and the trench unit includes a first part and a second part and a third part, the first part and the third part are arranged on both sides of the second part, and the length of the first part and the third part in the extension direction perpendicular to the second part is smaller than the length of the second part The length of the two parts perpendicular to the direction of their extension. According to the present invention, the length of the first part and the third part in the extension direction perpendicular to the second part is smaller than the length of the second part in the extension direction perpendicular to the extension direction, so that when the power semiconductor device is subsequently formed The source electrode cannot be deposited in the trenches at both ends, but only the gate electrode can be deposited, so that the gate electrode can be directly drawn out from both ends of the trench unit, thereby saving the area for forming the connection hole for the gate electrode and improving the power. Effective area utilization of semiconductor devices.

In a method for manufacturing a power semiconductor device provided by the present invention, the openings at both ends of the trench have gates but no sources, so that connecting holes can be directly provided at both ends of the trench to connect the above-mentioned The gate is drawn out, and there is no need to set a connection space in a special area, thereby saving the area where the connection hole is specially set, and improving the effective area utilization rate of the power semiconductor device. At the same time, since the openings at both ends of the trench have gates but not sources, the risk of bridging the gates and the sources is reduced, so holes can be connected there, thereby saving the need to define connections The mask of the region where the hole is connected to the gate also reduces the number of processes and reduces the process cost.

In addition, it should be noted that, unless otherwise specified or pointed out, the descriptions of the terms "first", "second", etc. in the specification are only used to distinguish various components, elements, steps, etc. in the specification, rather than to indicate The logical relationship or sequence relationship between various components, elements, steps, etc.

It should be understood that, although the present invention has been disclosed above with preferred embodiments, the above embodiments are not intended to limit the present invention. For any person skilled in the art, without departing from the scope of the technical solution of the present invention, many possible changes and modifications can be made to the technical solution of the present invention by using the technical content disclosed above, or modified into equivalents of equivalent changes Example. Therefore, any simple modifications, equivalent changes and modifications made to the above embodiments according to the technical essence of the present invention without departing from the content of the technical solutions of the present invention still fall within the protection scope of the technical solutions of the present invention.

Claims (10)

1. A groove layout structure, characterized in that it comprises a plurality of adjacently arranged groove units, the groove units include a first part, a second part and a third part, and the first part and the third part are arranged on the On both sides of the second part along its extension direction, the lengths of the first part and the third part in the extension direction perpendicular to the second part are smaller than the length of the second part in the extension direction perpendicular to the second part . 2 . The groove layout structure according to claim 1 , wherein the second part is in the shape of a long strip, and the first part and the third part have the same shape and are both regular two-dimensional patterns. 3 . 3 . The trench layout structure of claim 1 , wherein the first part and the third part are both rectangular and have the same size. 4 . 4. A method for making a power semiconductor device, comprising the following steps: Step S1: forming a plurality of trenches on the semiconductor substrate by using the mask having the trench layout structure according to any one of claims 1-3 as a mask; Step S2: forming a first oxide layer and a source electrode in sequence in the trench, the first oxide layer covers the inner wall of the trench, the source electrode fills the trench, and the first oxide layer covers the inner wall of the trench, and the source electrode fills the trench. The height of the oxide layer is lower than the height of the source electrode, and has an opening above the first oxide layer; Step S3: forming a second oxide layer on the semiconductor substrate, the second oxide layer wraps the source electrode, and exposes the first oxide layer, so that there is an opening above the first oxide layer; Step S4: forming a polysilicon layer at the opening, and using the second oxide layer as a mask to etch the polysilicon layer to form a gate, thereby forming a power semiconductor device. 5. The method for manufacturing a power semiconductor device according to claim 4, wherein step S1 specifically comprises: Several trenches are formed on the semiconductor substrate by using a mask having several trench units as a mask, and the widths of both ends of the trenches in the extending direction thereof are narrower than those along the extending direction of the trenches. the width in the middle of the . 6 . The method for fabricating a power semiconductor device according to claim 5 , wherein the width of both ends of the trench in the extending direction thereof is less than twice the thickness of the first oxide layer. 7 . 7. The method for manufacturing a power semiconductor device according to claim 4, wherein step S2 specifically comprises the following steps: A first oxide layer is deposited in the trench, and at an intermediate position of the trench along its extending direction, the first oxide layer covers the inner wall of the trench, in the extending direction of the trench At both ends of the upper part, the first oxide layer fills the trench; forming a first polysilicon layer in the trench, the first polysilicon layer filling the middle of the trench and covering the first oxide layer on the semiconductor substrate; etching the first polysilicon layer on the semiconductor substrate and leaving the first polysilicon layer in the middle of the trench to form a source electrode; Etching the first oxide layer on the semiconductor substrate, and etching the first oxide layer at a partial depth in the trench, so that the height of the first oxide layer is lower than the source electrode , and has an opening above the first oxide layer. 8 . The method for fabricating a power semiconductor device according to claim 7 , wherein a source electrode exists at an intermediate position along the extending direction of the trench, and a source electrode is present at two positions along the extending direction of the trench. 9 . There is no source at the end. 9 . A power semiconductor device, characterized in that it is prepared by the method for manufacturing a power semiconductor device according to any one of claims 4 to 8 , and comprises a trench. 10 . 10 . The power semiconductor device of claim 9 , wherein at both ends of the trench, the power semiconductor device comprises a first oxide layer, a second oxide layer and a gate from bottom to top. 11 .

Images