CN107946232B

CN107946232B - Shallow trench isolation structure array, semiconductor device structure and preparation method

Info

Publication number: CN107946232B
Application number: CN201711246346.XA
Authority: CN
Inventors: 请求不公布姓名
Original assignee: Changxin Memory Technologies Inc
Current assignee: Changxin Memory Technologies Inc
Priority date: 2017-12-01
Filing date: 2017-12-01
Publication date: 2023-05-26
Anticipated expiration: 2037-12-01
Also published as: CN107946232A

Abstract

The invention provides a shallow trench isolation structure, a semiconductor device and a preparation method thereof, wherein the preparation of the shallow trench isolation structure comprises the following steps: providing a semiconductor substrate, defining a transverse direction and a longitudinal direction which are mutually perpendicular, and forming a first mask layer, wherein the first mask layer comprises a plurality of first mask units which are arranged in parallel and form a first inclination angle relative to the longitudinal direction; forming a second mask layer, wherein the second mask layer comprises a plurality of auxiliary windows which are arranged in an array manner, and each row of auxiliary windows are arranged at a second inclination angle with respect to the longitudinal direction at equal intervals; transferring the patterns of the first mask layer and the second mask layer into the semiconductor substrate to form a first shallow trench and a second shallow trench; forming a barrier layer, and continuing etching to form a first shallow trench isolation structure and a second shallow trench isolation structure. Through the scheme, the asymmetry of the FIN structure is improved, the device structure has the same depth when formed between the adjacent shallow trench isolation structures, the problem of difference of electric field intensity is solved, and the phenomenon that filling holes occur in the filling layer when filling materials is improved.

Description

Shallow trench isolation structure array, semiconductor device structure and preparation method

Technical Field

The invention belongs to the technical field of semiconductor device manufacturing, and particularly relates to a shallow trench isolation structure array, a semiconductor device structure and a preparation method.

Background

Dynamic Random Access Memory (DRAM) is a commonly used semiconductor memory device. Consisting of a number of repeated memory cells. Each memory cell typically includes a capacitor and a transistor; the grid electrode of the transistor is connected with the word line, the drain electrode of the transistor is connected with the bit line, and the source electrode of the transistor is connected with the capacitor; the voltage information number on the word line can control the transistor to be turned on or off, thereby reading the data information in the capacitor through the bit line or writing the data information into the capacitor through the bit line for storage. Data is stored in the capacitor in the form of a charge, typically representing a "0" with no charge and a "1" with a charge, or vice versa. In order to reduce the size of the device, crisscrossed word lines and bit lines are arranged in the active area of the array arrangement, and a plurality of node contacts are arranged to connect the storage capacitor of each storage unit.

In the preparation of the existing shallow trench isolation structure, the preparation method generally comprises the following steps: etching to manufacture a contact window by using a mask; transferring the pattern of the pattern cover to the hard mask pattern by etching with high selectivity, transferring to the substrate, and forming a groove on the substrate; filling dielectric material in the trench; performing ion implantation of the source, drain and LDD of the buried transistor on the existing pattern; the trenches for the buried word lines are completed over the existing pattern and filled with gate oxide, work function and metal. However, the existing shallow trench isolation structure often has the phenomenon of asymmetric FIN structure, and the depths of word lines prepared in adjacent different shallow trench isolation structures are inconsistent, so that the electric field intensities at two asymmetric positions are different, which affects the critical voltage of a device.

Therefore, it is necessary to provide a shallow trench isolation structure array, a semiconductor device structure and a method for manufacturing the same to solve the above-mentioned problems in the prior art.

Disclosure of Invention

In view of the above-mentioned drawbacks of the prior art, an object of the present invention is to provide a shallow trench isolation structure array, a semiconductor device structure and a method for manufacturing the same, which are used for solving the problems of asymmetric FIN structure, different electric field strength caused by inconsistent word line depth between adjacent different shallow trench isolation structures, small trench bottom size, and easy occurrence of holes due to filling.

To achieve the above and other related objects, the present invention provides a method for manufacturing a shallow trench isolation structure array, comprising the steps of:

1) Providing a semiconductor substrate, wherein a transverse direction and a longitudinal direction which are perpendicular to each other are defined in a plane where the surface of the semiconductor substrate is located, a first mask layer is formed on the semiconductor substrate, the first mask layer comprises a plurality of first mask units which are arranged in parallel and have a first inclination angle relative to the longitudinal direction, and a first gap is formed between every two adjacent first mask units;

2) Forming a second mask layer on the semiconductor substrate, wherein the second mask layer is filled in the first gap and extends to cover the first mask layer, a plurality of auxiliary windows which are arranged in an array manner are formed on the second mask layer, each row of auxiliary windows is arranged at a second inclination angle in an equidistant manner relative to the longitudinal direction, a second gap is formed between every two adjacent auxiliary windows on the same row, the auxiliary windows expose the top of the first mask unit, the width of the second gap is matched with the width of the first gap in size, and the second inclination angle and the first inclination angle have different rotation angles;

3) Transferring the patterns on the first mask layer and the second mask layer into the semiconductor substrate, and reserving the rest first mask layer to form a first groove defined by the first gap and a second groove defined by the auxiliary window, and defining a plurality of active areas by adjacent second grooves along the extending direction of the first mask unit, wherein the second groove and the first grooves adjacent on two sides form a first shallow groove together along the longitudinal direction, and a second shallow groove formed by the first groove is arranged between the two adjacent first shallow grooves; and

4) And forming a blocking layer on the top and the side wall of the rest first mask layer and part of the side wall extending to the first shallow trench and the second shallow trench, and continuing etching the semiconductor substrate by taking the blocking layer as a mask so as to continue etching along the first shallow trench and form a first shallow trench isolation structure and continue etching along the second shallow trench and form a second shallow trench isolation structure.

In a preferred embodiment of the present invention, in step 1), the first inclination angle forms an acute rotation angle of an inverse clock with respect to the longitudinal direction, and in step 2), the second inclination angle forms an acute rotation angle of a clockwise clock with respect to the longitudinal direction.

In a preferred embodiment of the present invention, in step 3), the step of transferring the patterns on the first mask layer and the second mask layer into the semiconductor substrate includes: and etching the first mask layer by taking the second mask layer as a mask, removing the rest of the second mask layer, and continuing to etch the semiconductor substrate by taking the etched first mask layer as the mask.

In a preferred embodiment of the present invention, in step 3), the depth of the first shallow trench is greater than the depth of the second shallow trench, and the cross-sectional shapes of the first shallow trench and the second shallow trench in the longitudinal direction each include an inverted trapezoid.

In a preferred embodiment of the present invention, in step 3), a plurality of circulation units are formed in the semiconductor substrate along the longitudinal direction, and each of the circulation units includes a first shallow trench, an active region, a second shallow trench, and an active region in this order.

In a preferred embodiment of the present invention, in step 4), the barrier layer is formed by an atomic layer deposition process, and a material of the barrier layer includes alumina.

As a preferable scheme of the invention, the heights of the exposed side walls of the first shallow trench and the second shallow trench respectively occupy 20% -70% of the height from the bottom of the first shallow trench to the surface of the barrier layer and the height from the bottom of the second shallow trench to the surface of the barrier layer.

In step 4), the first shallow trench is etched to a first depth to form the first shallow trench isolation structure, and the second shallow trench is etched to a second depth to form the second shallow trench isolation structure, wherein the first depth is greater than the second depth, and the difference between the first depth and the second depth is 30-70 nm; and the obtuse angles formed by the side walls of the cross section shapes of the structures formed by continuing etching and the vertical direction along the longitudinal direction are respectively larger than the obtuse angles formed by the side walls of the cross section shapes of the first shallow grooves and the second shallow grooves and the vertical direction.

In a preferred embodiment of the present invention, in step 4), bottoms of cross-sectional shapes of the first shallow trench isolation structure and the second shallow trench isolation structure in the longitudinal direction each include a rectangle, and a top opening size of the cross-sectional shape is larger than a bottom side length of the corresponding rectangle, wherein a depth of the first shallow trench isolation structure is larger than a depth of the second shallow trench isolation structure.

As a preferable scheme of the invention, the top shape of the cross-sectional shape is defined by the first shallow groove and the second shallow groove, each of the cross-sectional shape and the second shallow groove comprises an inverted trapezoid, and the rectangular connection is positioned below the inverted trapezoid, wherein an obtuse angle range formed between the side wall of the inverted trapezoid defined by the first shallow groove and the vertical direction comprises 160-179.9 degrees; the obtuse angle range formed between the side wall of the inverted trapezoid defined by the second shallow groove and the vertical direction comprises 160-179.9 degrees.

The invention also provides a preparation method of the semiconductor device structure, which comprises the following steps:

1) Preparing a shallow trench isolation structure array by adopting the preparation method according to any one of the schemes;

2) Removing the rest barrier layer, and filling isolation medium layers in the first shallow trench isolation structure and the second shallow trench isolation structure; and

3) And preparing an embedded word line structure in the active region and the isolation medium layer.

As a preferred embodiment of the present invention, step 3) specifically includes:

3-1) performing a first ion implantation into the active region to form a channel region;

3-2) continuing to perform second ion implantation and third ion implantation into the active region so as to sequentially form a lightly doped drain region and a shallow junction region above the channel region;

3-3) preparing a plurality of device groove structures which are arranged in parallel at intervals along the transverse direction and pass through the active region, the first shallow groove isolation structure and the second shallow groove isolation structure, wherein the bottoms of the device groove structures extend to the channel region; and

3-4) depositing a gate oxide layer and a word line entity layer on the surface of the device groove structure in sequence to obtain a buried word line structure, and filling an insulating medium layer covering the gate oxide layer and the word line entity layer in the device groove structure.

As a preferred embodiment of the present invention, in step 3-4), the method further comprises the steps of: and forming a word line surface layer between the gate oxide layer and the word line entity layer, wherein the word line surface layer is used for defining an effective working area of the embedded word line structure.

As a preferred aspect of the present invention, the material of the word line surface layer includes titanium nitride; the material of the word line physical layer comprises tungsten; the material of the insulating medium layer comprises silicon nitride.

In a preferred embodiment of the present invention, in step 3-3), the device trench structure includes a first portion located in the first shallow trench isolation structure and the second shallow trench isolation structure, and a second portion located in the active region, wherein a depth of the first portion is greater than a depth of the second portion.

In step 3-3), two device trench structures pass through the same active region, and the same device trench structure passes through the first shallow trench isolation structure, the active region, the second trench isolation structure and the active region in turn.

As a preferred aspect of the present invention, in step 3-3), the depth of the device trench structure is smaller than the depth of the second shallow trench isolation structure; the height range of the device groove structure comprises 100-300 nanometers, the height range of the second shallow groove isolation structure comprises 200-600 nanometers, and the height range of the first shallow groove isolation structure comprises 200-700 nanometers.

As a preferred aspect of the present invention, the implanted ions of the first ion implantation in step 3-1) include boron; the second ion implanted implant in step 3-2) comprises phosphorus and the third ion implanted implant comprises arsenic.

In a preferred embodiment of the present invention, in step 2), the dielectric constant value range of the material of the isolation dielectric layer includes 0 to 3, and the material of the isolation dielectric layer includes silicon oxide.

As a preferred embodiment of the present invention, the buried word line structure in the first shallow trench isolation structure and the buried word line structure in the second shallow trench isolation structure have the same depth.

The invention also provides a shallow trench isolation structure array, comprising: a semiconductor substrate, wherein a transverse direction and a longitudinal direction which are perpendicular to each other are defined in a plane where the surface of the semiconductor substrate is located; the semiconductor substrate is provided with a plurality of first grooves which are arranged in parallel at equal intervals and a plurality of second grooves which are arranged in an array manner, and the first grooves have a first inclination angle relative to the longitudinal direction; the semiconductor substrate comprises a plurality of active areas which are arranged in an array manner, each active area has the same outline, and each row of active areas and the first grooves are alternately arranged at intervals; each second groove has the same outer contour, each row of second grooves is distributed at equal intervals relative to the longitudinal direction at a second inclination angle, the second grooves are positioned between gaps formed by adjacent active areas of each row, and the second inclination angles and the first inclination angles have different rotation angles; the semiconductor substrate is also provided with a first auxiliary groove and a second auxiliary groove, wherein the first auxiliary groove is positioned below the second groove and the first grooves adjacent to the two sides of the second groove, and forms a first shallow groove isolation structure together with the corresponding first grooves and second grooves; the second auxiliary grooves are correspondingly positioned below the first grooves between two adjacent first auxiliary grooves along the longitudinal direction, and form a second shallow groove isolation structure with the corresponding first grooves.

As a preferable mode of the invention, the first auxiliary groove has a first depth, the second auxiliary groove has a second depth, wherein the first depth is larger than the second depth, and the difference between the first depth and the second depth is 30-70 nanometers; and in the longitudinal direction, the obtuse angle between the side wall of the cross section of the first auxiliary groove and the vertical direction is larger than the obtuse angle between the side wall of the cross section of the first shallow groove formed by the second groove and the first groove above the first auxiliary groove and the vertical direction, and the obtuse angle between the side wall of the cross section of the second auxiliary groove and the vertical direction is larger than the obtuse angle between the side wall of the cross section of the second shallow groove formed by the first groove above the second auxiliary groove and the vertical direction.

As a preferable mode of the present invention, in the longitudinal direction, the cross-sectional shapes of the first auxiliary groove and the second auxiliary groove each include a rectangle, and the top opening sizes of the cross-sectional shapes of the first shallow trench isolation structure and the second shallow trench isolation structure are both larger than the bottom side length of the corresponding rectangle, wherein the depth of the first shallow trench isolation structure is larger than the depth of the second shallow trench isolation structure.

As a preferred solution of the present invention, the top shapes of the cross-sectional shapes of the first shallow trench isolation structure and the second shallow trench isolation structure are respectively defined by a first shallow trench formed by a second trench above the first auxiliary trench and a first trench above the second auxiliary trench, and a second shallow trench formed by a first trench above the second auxiliary trench, each of which comprises an inverted trapezoid, and the rectangular connection is located below the inverted trapezoid, wherein an obtuse angle range formed between a sidewall of the inverted trapezoid defined by the first shallow trench and a vertical direction comprises 160 ° to 179.9 °; the obtuse angle range formed between the side wall of the inverted trapezoid defined by the second shallow groove and the vertical direction comprises 160-179.9 degrees.

The invention also provides a semiconductor device structure, comprising:

the shallow trench isolation structure array according to any one of the above schemes;

the isolation medium layer is filled in the first shallow trench isolation structure and the first shallow trench isolation structure; and

the embedded word line structures are located in the active area and the isolation medium layer and are arranged in parallel at intervals along the transverse direction.

As a preferred embodiment of the present invention, the buried word line includes:

The device groove structures are arranged in parallel at intervals along the transverse direction and penetrate through the active region, the first groove isolation structure and the second groove isolation structure;

the grid oxide layer is positioned at the bottom and part of the side wall of the device groove structure; and

the word line surface layer is positioned on the surface of the gate oxide layer, and the word line entity layer is positioned on the surface of the word line surface layer.

As a preferred scheme of the invention, the depth of the device groove structure is smaller than that of the second shallow groove isolation structure; the height range of the device groove structure comprises 100-300 nanometers, the height range of the second shallow groove isolation structure comprises 200-600 nanometers, and the height range of the first shallow groove isolation structure comprises 200-700 nanometers.

As a preferred embodiment of the present invention, two buried word line structures pass through the same active region, and the same buried word line structure circulates and sequentially passes through the first shallow trench isolation structure, the active region, the second trench isolation structure and the active region.

As described above, the shallow trench isolation structure array, the semiconductor device structure and the preparation method of the invention have the following beneficial effects:

the shallow trench isolation structures prepared by adopting a quantitative atomic layer deposition process and a plurality of etching processes enable the shallow trench isolation structures with different sizes to be not symmetrical due to size differences and the like, and enable the prepared structures, such as embedded word lines, to have the same depth when formed between the adjacent shallow trench isolation structures, so that the problem of difference of electric field intensity caused by inconsistent depths is solved, and the critical voltage of a device is improved; meanwhile, through reasonable structural design, the invention improves the defects of transistor manufacture caused by larger difference between the bottom opening width and the upper opening size of the shallow trench isolation structure, and relieves the phenomenon that filling holes (void) appear in metal when internal filling is carried out, such as when embedded word line filling word line metal (such as TiN/W) is prepared.

Drawings

FIG. 1 is a flow chart of a process for manufacturing an array of shallow trench isolation structures according to the present invention.

FIG. 2 is a schematic diagram showing the formation of a patterned first photoresist layer in the fabrication of a shallow trench isolation structure array according to the present invention.

Fig. 3 shows a cross-sectional view along a-B in fig. 2.

Fig. 4 is a schematic diagram illustrating etching to form a first mask layer in the preparation of the shallow trench isolation structure array according to the present invention.

Fig. 5 shows a cross-sectional view along a-B in fig. 4.

Fig. 6 is a schematic diagram showing the arrangement of the first mask unit in the preparation of the shallow trench isolation structure array according to the present invention.

Fig. 7 is a cross-sectional view taken along a-B in fig. 6.

FIG. 8 is a schematic diagram of forming a patterned second photoresist layer in the fabrication of a shallow trench isolation structure array according to the present invention.

Fig. 9 is a cross-sectional view taken along a-B in fig. 8.

Fig. 10 is a cross-sectional view taken along the direction C-D in fig. 8.

FIG. 11 is a schematic diagram illustrating the etching of a second mask layer in the fabrication of the shallow trench isolation structure array according to the present invention.

Fig. 12 is a cross-sectional view taken along a-B in fig. 11.

Fig. 13 is a sectional view taken along the direction C-D in fig. 11.

FIG. 14 is a schematic diagram showing pattern transfer on the first and second mask layers in the fabrication of the array of shallow trench isolation structures according to the present invention.

Fig. 15 is a cross-sectional view taken along a-B in fig. 14.

Fig. 16 is a sectional view taken along the direction C-D in fig. 14.

FIG. 17 is a schematic diagram of a structure for forming a barrier layer in the fabrication of a shallow trench isolation structure array according to the present invention.

Fig. 18 is a sectional view taken along the direction a-B in fig. 17.

Fig. 19 is a sectional view taken along the direction C-D in fig. 17.

Fig. 20 is a schematic diagram of an array of shallow trench isolation structures according to the present invention after etching using a barrier layer as a mask.

Fig. 21 is a sectional view taken along a-B in fig. 20.

Fig. 22 is a cross-sectional view taken along the direction C-D in fig. 20.

FIG. 23 is a schematic diagram of the shallow trench isolation structure array according to the present invention after removing the barrier layer.

Fig. 24 is a sectional view taken along the direction a-B in fig. 23.

Fig. 25 is a sectional view taken along the direction C-D in fig. 23.

FIG. 26 is a schematic diagram of forming an isolation dielectric layer in the fabrication of a shallow trench isolation structure array according to the present invention.

Fig. 27 is a cross-sectional view taken along a-B in fig. 26.

Fig. 28 is a cross-sectional view taken along the direction C-D in fig. 26.

Fig. 29 is a schematic diagram of a shallow trench isolation structure array according to the present invention after removing a portion of the isolation dielectric layer.

Fig. 30 is a cross-sectional view taken along a-B in fig. 29.

Fig. 31 is a cross-sectional view taken along the direction C-D in fig. 29.

FIG. 32 is a schematic diagram of forming a channel region, a doped drain region and a shallow junction region in the fabrication of a shallow trench isolation structure array according to the present invention.

FIG. 33 is a schematic diagram of a buried word line structure formed in the fabrication of a shallow trench isolation array according to the present invention.

Fig. 34 is a sectional view taken along a-B in fig. 33.

Fig. 35 is a sectional view taken along the direction C-D in fig. 33.

Fig. 36 shows a partial enlarged view of the dashed box area of fig. 35 in an example.

Fig. 37 is a schematic view showing a structure of a semiconductor device in the comparative example.

Description of element reference numerals

10. Semiconductor substrate

11. First mask layer

111. First mask unit

12. First photoresist layer

121. First photoresist unit

13. Second mask layer

131. Auxiliary window

14. Second photoresist layer

141. Photoresist auxiliary window

15. First groove

16. Second groove

161. Active region

17. First shallow trench

18. Second shallow trench

19. Barrier layer

20. First auxiliary groove

21. Second auxiliary groove

22. First shallow trench isolation structure

23. Second shallow trench isolation structure

24. Isolation dielectric layer

25. Device trench structure

251. First part

252. Second part

26. Gate oxide layer

27. Word line surface layer

28. Word line physical layer

29. Insulating dielectric layer

30. Channel region

31. Shallow doped drain region

32. Shallow junction region

33. Substrate and method for manufacturing the same

34. Active region

35. Isolation structure

36. Surface metal layer

37. Filling metal layer

39. Filling the holes

S1-S4 steps 1) to 4)

Detailed Description

Other advantages and effects of the present invention will become apparent to those skilled in the art from the following disclosure, which describes the embodiments of the present invention with reference to specific examples. The invention may be practiced or carried out in other embodiments that depart from the specific details, and the details of the present description may be modified or varied from the spirit and scope of the present invention.

Please refer to fig. 1 to 37. It should be noted that, the illustrations provided in the present embodiment are merely schematic illustrations of the basic concepts of the present invention, and only the components related to the present invention are shown in the illustrations, rather than being drawn according to the number, shape and size of the components in actual implementation, and the form, number and proportion of each component in actual implementation may be arbitrarily changed, and the layout of the components may be more complex.

Embodiment one:

as shown in fig. 1, the invention provides a method for preparing a shallow trench isolation structure array, which comprises the following steps:

2) Forming a second mask layer on the semiconductor substrate, wherein the second mask layer is filled in the first gap and extends to cover the first mask layer, a plurality of auxiliary windows which are arranged in an array manner are formed on the second mask layer, each row of auxiliary windows is arranged at a second inclination angle in an equidistant manner relative to the longitudinal direction, a second gap is formed between every two adjacent auxiliary windows on the same row, the auxiliary windows expose the top of the first mask unit, the width of the second gap is matched with the width of the first gap, and the second inclination angle and the first inclination angle have different rotation angles;

The method for preparing the shallow trench isolation structure of the present invention will be described in detail with reference to the accompanying drawings.

First, step 1) is performed, as shown in S1 of fig. 1 and fig. 2 to 7, a semiconductor substrate 10 is provided, and a transverse direction (X-axis) and a longitudinal direction (Y-axis) perpendicular to each other are defined in a plane on which a surface of the semiconductor substrate 10 is located, and a first mask layer 11 is formed on the semiconductor substrate 10, where the first mask layer 11 includes a plurality of first mask units 111 arranged in parallel and having a first inclination angle with respect to the longitudinal direction, and a first gap d1 is provided between adjacent first mask units 111.

Specifically, the present embodiment first provides a semiconductor substrate 10, where the material of the semiconductor substrate 10 includes but is not limited to a monocrystalline or polycrystalline semiconductor material, and in addition, the semiconductor substrate 10 may be an intrinsic monocrystalline silicon substrate or a lightly doped silicon substrate, and further, may be an N-type polycrystalline silicon substrate or a P-type polycrystalline silicon substrate, and in this embodiment, the semiconductor substrate 10 is a substrate of polycrystalline silicon material. In addition, a lateral direction (X axis) and a longitudinal direction (Y axis) perpendicular to each other are defined in a plane on the surface of the semiconductor substrate 10, for example, the longitudinal Y axis is defined to be the same as the extending direction of the word line, the lateral X axis is defined to be the same as the extending direction of the bit line, and the longitudinal Y and the lateral X intersect perpendicularly. In addition, the term "plurality" as used herein means a plurality of first mask units 111 arranged in parallel and having a first inclination angle with respect to the longitudinal direction, and a plurality of first mask units 111 arranged in parallel and having a first inclination angle with respect to the longitudinal direction.

Specifically, a first mask layer 11 is prepared on the surface of the semiconductor substrate 10, to define a pattern for etching the semiconductor substrate, wherein a method for forming the first mask layer 11 by plasma etching is shown in fig. 2 to 7, a first photoresist layer 12 with a pattern is formed first, the first photoresist layer 12 has a plurality of first photoresist units 121 arranged in parallel at intervals, the first photoresist layer 12 is used as a mask to transfer the pattern onto the first mask layer 11, a plurality of first mask units 111 arranged in parallel at intervals are formed, and finally, photoresist is removed by ashing or the like. The first inclination angle may form an acute rotation angle of the inverted clock with respect to the longitudinal direction (Y-axis direction), and may, of course, also be an obtuse rotation angle of the inverted clock, or even a right rotation angle, which is selected according to practical requirements. In addition, the material of the first mask layer 11 includes, but is not limited to, silicon nitride, silicon oxide, carbon, and the like, which have a high selectivity to the material of the semiconductor substrate 10.

Next, step 2) is performed, as shown in S2 in fig. 1 and fig. 8 to 13, a second mask layer 13 is formed on the semiconductor substrate 10, the second mask layer 13 is filled in the first gap d1 and extends to cover the first mask layer 11, a plurality of auxiliary windows 131 arranged in an array are formed on the second mask layer 13, each row of the auxiliary windows 131 is arranged at a second inclination angle with respect to the longitudinal direction at equal intervals, a second gap d2 is formed between adjacent auxiliary windows 131 on the same row, the auxiliary windows 131 expose the top of the first mask unit 111, the width of the second gap is matched with the width of the first gap d1, and the second inclination angle and the first inclination angle have different rotation angles.

Specifically, a second mask layer 13 is formed on the structure obtained in step 1), where the second mask layer 13 is also used to define, through the auxiliary window 131, a pattern finally formed in the semiconductor substrate 10, and the patterns on the first mask layer 11 are combined, so as to combine the patterns to be obtained in the invention in the semiconductor substrate 10. Wherein the material of the second mask layer 13 includes, but is not limited to, silicon nitride, silicon oxide, carbon, etc., but the material is selected such that a high selectivity between the material and the material of the first mask layer 11 is required.

In addition, this example also provides a method for forming the second mask layer 13 by plasma etching, as shown in fig. 8 to 13, a layer of material for preparing the second mask layer is deposited first, the layer of material fills the first gap d1 formed between the first mask units 111, and uniformly covers the first mask layer 11 and forms a certain thickness, then a second photoresist layer 141 with patterns is formed on the layer of material, a photoresist auxiliary window 141 corresponding to the required auxiliary window 131 is prepared in the second photoresist layer, finally the material layer is etched based on the photoresist auxiliary window 141, and the first mask layer 11 is used as an etching stop layer, and the photoresist is removed to finally obtain the second mask layer 13 with the auxiliary window 131.

The auxiliary windows 131 are arranged in an array, the outer contour of the auxiliary windows 131 may have a parallelogram, a rectangle or other suitable shapes, in this embodiment, the outer contour of the auxiliary windows 131 adopts a parallelogram, the auxiliary windows 131 are correspondingly formed on the second mask layer 13 directly above the top of the first mask unit 111, the size of the auxiliary windows 131 just corresponds to the top size of the first mask unit 111, and a uniform second mask layer is formed in the first gap and above the first gap at a position exceeding the height of the first mask layer.

In addition, for the design of the array arrangement of the auxiliary windows 131, the design is selected according to actual requirements, in this example, each row of auxiliary windows 131 is arranged at a second inclination angle with equal spacing with respect to the longitudinal direction, based on this, the second inclination angle and the setting of the first inclination angle can control the arrangement of the active area and the shallow trench isolation structure formed subsequently, the first inclination angle can form an acute angle rotation angle of an inverse clock with respect to the longitudinal direction (Y-axis direction), and of course, an obtuse angle or even a right angle rotation angle of the inverse clock can also be formed, where, in this application, the first inclination angle and the second inclination angle are selected to form acute angle rotation angles in different directions of the inverse clock with respect to the longitudinal direction respectively, in addition, the second gap d2 is matched with the size of the first gap d1, as an example, the first gap d1 is equal to the second gap d2, and the purpose is that after etching, both the first gap d2 and the required positions can be communicated to form a required pattern.

As an example, in step 1), the first inclination angle is formed with an acute rotation angle of an inverse clock with respect to the longitudinal direction, and in step 2), the second inclination angle is formed with an acute rotation angle of a clockwise clock with respect to the longitudinal direction.

Specifically, the first inclination angle and the second inclination angle in this example are controlled such that, in the longitudinal direction, three first gaps d1 are sandwiched between the two auxiliary windows 131, the two auxiliary windows are respectively in contact with the two first gaps, and the three first gaps uniformly and symmetrically sandwich the two first mask units, which are respectively in contact one by one, and thereby circulate in the longitudinal direction (a-B direction). In addition, since the auxiliary windows 131 are arranged at equal intervals in each row, in the direction C-D of fig. 11, two adjacent auxiliary windows 131 have the same interval therebetween, and the interval ultimately defines the size and the position of the active region 161 to be formed subsequently.

Continuing with step 3), as shown in S3 of fig. 1 and fig. 14 to 16, transferring the patterns on the first mask layer 11 and the second mask layer 13 into the semiconductor substrate 10 while leaving the remaining first mask layer 11 to form a first trench 15 defined by the first gap and a second trench 16 defined by the auxiliary window 131, and defining a plurality of active regions by adjacent second trenches 16 along the extending direction of the first mask unit 111, wherein, along the longitudinal direction, the second trench 16 and the first trenches 15 adjacent on both sides together form a first shallow trench 17, and a second shallow trench 18 formed by the first trench 15 is located between two adjacent first shallow trenches 17.

As an example, in step 3), the step of transferring the patterns on the first mask layer 11 and the second mask layer 13 into the semiconductor substrate 10 includes: the second mask layer 12 is used as a mask to etch the first mask layer 11, then the remaining second mask layer 12 is removed, and the etched first mask layer 11 is used as a mask to etch the semiconductor substrate 10.

Specifically, the pattern defined by the first mask layer 11 and the second mask layer is formed on the semiconductor substrate 10 through this step, and the etched first mask layer 11 is preferably kept for subsequent processing, so that the subsequent barrier layer 19 can be better formed.

As an example, in step 3), the depth of the first shallow trench 17 is greater than the depth of the second shallow trench 18, and the cross-sectional shapes of the first shallow trench 17 and the second shallow trench 18 in the longitudinal direction each include an inverted trapezoid.

Specifically, as shown in fig. 14, the second trench 16 and the first trenches 15 on both sides together form a large shallow trench structure, the first shallow trenches 17 are adjacent on both sides of the large shallow trench structure as active area portions, and in the longitudinal direction, a small shallow trench structure, that is, the second shallow trench 18, formed by a portion of the formed first trenches 15 is included between adjacent first trenches 17 in addition to the adjacent active area.

As an example, in step 3), a plurality of circulation units are formed in the semiconductor substrate 10 in the longitudinal direction, each of the circulation units including a first shallow trench 17, an active region 161, a second shallow trench 18, and an active region 161 in this order.

Specifically, in the present example, there is provided an arrangement array of shallow trench isolation structures and active regions formed in a semiconductor substrate, wherein, in the direction C-D in fig. 14, one structure is a first trench 15, which is arranged in parallel at equal intervals, and one structure is a second trench 16 and active regions, which are arranged at intervals to form a row of structures, each row of structures being arranged alternately at intervals with the first trench 15; in the longitudinal direction, the circulation units formed by the first shallow trenches 17, the active regions 161, the second shallow trenches 18, and the active regions 161 are arranged in a circulation manner, and each active region is positioned such that two such circulation units pass through and are arranged at equal intervals in the lateral direction (X-axis direction). In addition, the cross-sectional shapes of the first shallow trench 17 and the second shallow trench 18 may be any shapes, such as a shape in which the side wall is a discontinuous straight line, and the like, and the present example is selected to be an inverted trapezoid.

Finally, step 4) is performed, as shown in S4 in fig. 1 and fig. 17 to 25, a barrier layer 19 is formed on the top, the side wall and the part of the side wall extending to the first shallow trench 17 and the second shallow trench 18 of the remaining first mask layer 11, and the semiconductor substrate 10 is continuously etched with the barrier layer 19 as a mask, so as to continuously etch along the first shallow trench 17 and form a first shallow trench isolation structure 22, and continuously etch along the second shallow trench 18 to form a second shallow trench isolation structure 23.

Specifically, the purpose of this step is to continue etching the semiconductor substrate 10 based on the formed barrier layer 19, so as to improve the shapes of the first shallow trench 17 and the second shallow trench 18 formed in the above step, form the corresponding first auxiliary trench 20 and the second auxiliary trench 21 under the two, and finally form the first shallow trench isolation structure 22 required by the first shallow trench 17 and the first auxiliary trench 20, and form the second shallow trench isolation structure 23 by the second shallow trench 18 and the second auxiliary trench 21, preferably, the cross-sectional shapes of the first auxiliary trench and the second auxiliary trench are rectangular, but not limited thereto, and are set according to the actual requirements.

As an example, in step 4), the barrier layer 19 is formed by an atomic layer deposition process (ALD), and the material of the barrier layer 19 includes aluminum oxide.

In particular, the barrier layer is preferably formed using a quantitative atomic layer deposition process, including but not limited to aluminum oxide (Al ₂ O ₃ ). Wherein, in the Reaction support, TMA (trimethylalumimum) Reaction is expressed as: al-OH+Al (CH 3) 3→Al-O-Al-CH 3+CH 4; al-CH3 +H2O→Al-OH +CH4. Thereby ALD process preparing Al ₂ O ₃ When the equivalent of the pre-cursor is required to be provided is as follows: s= (2x1+2y1) ×h1+z1+ (2x2+2y2) ×h2×z2+ (zs-x1y1z1-x2y2z2), wherein assuming that the wafer surface area is zs, the height covered by the procursor in the trench is h1 (let the total height be h 2), the width in the STI trench (trench described in fig. 6 and 7) is x1, the length is y1, the number of STI trenches is z1, the width in the STI hole (hole formed in fig. 8 to 10) is x2, the length is y2, and the number of STI holes is z2. Assuming d is the pre-cursor required for the unit area ALD process, the dose of pre-cursor required for the process is: d=s×d. Of course, the required dosage of the alumina is obtained based on the calculation, and can be correspondingly adjusted according to the actual situation, so that the barrier layer is quantitatively deposited.

As an example, the heights of the exposed sidewalls of the first shallow trench 17 and the second shallow trench 18 respectively occupy 20% -70% of the height from the bottom of the first shallow trench 17 to the surface of the barrier layer 19 and the height from the bottom of the second shallow trench 18 to the surface of the barrier layer 19.

Specifically, in this example, a ratio of the barrier layer height formed when the barrier layer 19 is deposited, that is, a ratio of h1 to h2 in fig. 18, that is, a distance from the bottom of the barrier layer 19 to the top of the barrier layer in the first shallow trench is 30% to 80%, preferably 40% to 70%, of the distance from the bottom of the first shallow trench 17 to the top of the barrier layer, in this example, 60%; in the second shallow trench, the distance from the bottom of the barrier layer 19 to the top of the barrier layer is 30% -80%, preferably 40% -70%, in this example 60% of the distance from the bottom of the second shallow trench 18 to the top of the barrier layer.

As an example, the first shallow trench 17 is further etched to a first depth t1 to form the first shallow trench isolation structure 22, and the second shallow trench 18 is further etched to a second depth t2 to form the second shallow trench isolation structure 23, wherein the first depth t1 is greater than the second depth t2, and a difference between the first depth t1 and the second depth t2 ranges from 30 nm to 70 nm; and the obtuse angles between the side walls of the cross section of the structure formed by continuing etching and the vertical direction are larger than those between the side walls of the cross section of the first shallow trench 17 and the second shallow trench 18.

Specifically, after the etching is continued, since the first shallow trench 17 is larger than the second shallow trench 18, the range between 30 nm and 70nm is floating based on the depth of the etching continued of the first shallow trench 17 compared with the range between 50nm based on the depth of the etching continued of the second shallow trench 18, which is set in this example. The first shallow trench 17 is etched towards the inside of the semiconductor substrate 10 by using the barrier layer 19 as a mask, a first depth t1 is etched, after the etching is continued, the etching is performed to form a trench structure, namely a first auxiliary trench, an obtuse angle between a side wall of the first auxiliary trench and a vertical direction in the cross-sectional shape along the longitudinal direction is larger than an obtuse angle between a side wall of the original first shallow trench 17 along the longitudinal cross-sectional shape and the vertical direction, so that the bottom length of the shape formed by etching with the barrier layer 19 as the mask is larger than the bottom length of the original first shallow trench 17 when the side wall continues to extend to the same depth, the bottom length of the first shallow trench is widened while the depth of the shallow trench isolation structure is increased, and similarly, the second shallow trench isolation structure is also provided with similar conditions.

In addition, the depth range of the first shallow trench isolation structure 22 formed includes 200-700 nm, and the depth range of the first shallow trench 17 includes 200-600 nm; the depth of the second shallow trench isolation structure 23 is formed to be in the range of 200 to 600nm, and the depth of the second shallow trench 18 is formed to be in the range of 200 to 500nm.

As an example, in step 4), in the longitudinal direction, the bottoms of the cross-sectional shapes of the first shallow trench isolation structure 22 and the second shallow trench isolation structure 23 each include a rectangle, and the opening sizes of the tops of the cross-sectional shapes are each larger than the bottom side length of the corresponding rectangle, wherein the depth of the first shallow trench isolation structure 22 is larger than the depth 23 of the second shallow trench isolation structure.

As an example, the tops of the cross-sectional shapes each comprise an inverted trapezoid defined by the first shallow trench 17 and the second shallow trench 18, the rectangular connection being located below the inverted trapezoid, wherein the side wall of the inverted trapezoid defined by the first shallow trench 17 forms an obtuse angle with the vertical ranging from 160 ° to 179.9 °, preferably from 165 ° to 175 °, in this example 170 °; the second shallow trench 18 defines an obtuse angle with the vertical of the inverted trapezoidal sidewall ranging from 160 ° to 179.9 °, preferably from 165 ° to 175 °, in this example 170 °, as shown by θ in fig. 15.

In addition, the removal of the barrier layer 19 for subsequent device fabrication is included in this example.

In the conventional semiconductor device structure preparation, in order to increase the transistor channel region (channel) current when the buried word line BW (buried wordline) is grooved, siO2 is selectively etched to form FIN structure (FIN structure having a certain angle with respect to the vertical direction) between STI (shallow trench isolation structure) and Substrate active region in the last step of BW trench, that is, the speed is increased by increasing the surface area, so that a FIN structure is formed at the STI and AA to increase the surface area, and the electron concentration degree is higher as FIN is higher, but since STI having a larger size difference in DRAM (Dynamic Random Access Memory) structure, there is a difference in space size formed at STI, asymmetry occurs in FIN, existence of electric field in an asymmetric region is caused, and critical voltage of transistor is affected. In addition, when BW is filled, the difference between the bottom opening width and the upper opening size of some shallow trench isolation structures is larger, so that filling materials such as TiN/W are easy to cause, gap filling is incomplete, filling holes (void) appear, and the performance and stability of the device are affected.

Therefore, the depth and profile of the large and small trenches are improved, and when the word line etching is performed, the depth difference etched in the large and small trenches is reduced and even tends to be uniform, so that the asymmetry of the FIN structure is reduced, the change of the depth of the WL trench in the large and small STI is improved by the change of the STI, meanwhile, the formation of filling holes in the material filling process is improved, and the influence on the device performance caused by the filling of the holes is improved.

As shown in fig. 23 to 25, the present invention further provides an array of shallow trench isolation structures, where the shallow trench isolation array structure provided by the present invention is preferably prepared by the preparation method provided by the present invention, but is not limited thereto, and includes: a semiconductor substrate 10, wherein a transverse direction and a longitudinal direction which are perpendicular to each other are defined in a plane on which the surface of the semiconductor substrate 10 is located; a plurality of first grooves 15 arranged in parallel and at equal intervals and a plurality of second grooves 16 arranged in an array, wherein the first grooves 15 have a first inclination angle relative to the longitudinal direction; the semiconductor substrate 10 includes a plurality of active regions 161 arranged in an array, each active region 161 having the same outer contour, and each row of active regions 161 and the first trenches 15 are alternately arranged at intervals; each second groove 16 has the same outer contour, each row of the second grooves is arranged at a second inclination angle with respect to the longitudinal direction at equal intervals, the second grooves 16 are positioned between gaps formed by adjacent active regions of each row, and the second inclination angles and the first inclination angles have different rotation angles; the semiconductor substrate 10 further has a first auxiliary groove 20 and a second auxiliary groove 21, wherein the first auxiliary groove 20 is located below the second groove 16 and the first groove 15 adjacent to two sides of the second groove 16, and forms a first shallow groove isolation structure 22 together with the corresponding first groove 15 and second groove 16; and the second auxiliary grooves 21 are located below the first grooves 15 between two adjacent first auxiliary grooves 20 along the longitudinal direction, and form second shallow trench isolation structures 23 with the corresponding first grooves 15.

Specifically, the material of the semiconductor substrate 10 includes, but is not limited to, a monocrystalline or polycrystalline semiconductor material, and in addition, may be an intrinsic monocrystalline silicon substrate or a lightly doped silicon substrate, and further, may be an N-type polycrystalline silicon substrate or a P-type polycrystalline silicon substrate, and in this embodiment, the semiconductor substrate 10 is a substrate of polycrystalline silicon material. In addition, a lateral direction (X axis) and a longitudinal direction (Y axis) perpendicular to each other are defined in a plane on the surface of the semiconductor substrate 10, for example, the longitudinal Y axis is defined to be the same as the extending direction of the word line, the lateral X axis is defined to be the same as the extending direction of the bit line, and the longitudinal Y and the lateral X intersect perpendicularly.

Specifically, the first inclination angle forms an acute rotation angle of an inverse clock relative to the longitudinal direction, and the second inclination angle forms an acute rotation angle of a clockwise clock relative to the longitudinal direction.

Specifically, the "the second trench 16 and the first trenches 15 adjacent to both sides of the second trench 16" means that the second trench 16 and the first trenches 15 along the longitudinal direction, which are in contact with the second trench 16 and are located on both sides thereof, together form a structure, which may be defined as a first shallow trench; "the first trenches 15 located between two adjacent first auxiliary recesses 20 in the longitudinal direction" means that portions of the first trenches located between two adjacent first auxiliary recesses in the longitudinal direction, but not in contact with the first auxiliary recesses, are separated by an active region 161, and this portions of the first trenches constitute a structure, which may be defined as second shallow trenches.

In addition, referring to fig. 14, the second trench 16 and the first trenches 15 on both sides together form a large shallow trench structure, the first shallow trenches 17 are adjacent on both sides of the large shallow trench structure as active region portions, and a small shallow trench structure, that is, a second shallow trench 18, is formed by a portion of the formed first trenches 15 in addition to the adjacent active regions between the adjacent first trenches 17 in the longitudinal direction. The first auxiliary groove 20 and the second auxiliary groove 21 respectively form the first trench isolation structure 22 and the second trench isolation structure 23 with the first auxiliary groove and the second auxiliary groove.

As an example, the first auxiliary groove 20 has a first depth, the second auxiliary groove 21 has a second depth, wherein the first depth is greater than the second depth, and a difference range of the first depth and the second depth includes 30 to 70 nanometers; and in the longitudinal direction, the obtuse angle between the side wall of the cross section of the first auxiliary groove 20 and the vertical direction is larger than the obtuse angle between the side wall of the cross section of the first shallow groove formed by the second groove and the first groove above the first auxiliary groove and the vertical direction, and the obtuse angle between the side wall of the cross section of the second auxiliary groove 21 and the vertical direction is larger than the obtuse angle between the side wall of the cross section of the second shallow groove formed by the first groove above the second auxiliary groove and the vertical direction.

Specifically, in the cross-sectional shape of the first auxiliary groove 20 along the longitudinal direction, the obtuse angle between the side wall and the vertical direction is larger than the obtuse angle between the side wall of the first shallow groove formed by the second groove and the first groove above the original first auxiliary groove 20 along the cross-sectional shape of the longitudinal direction and the vertical direction, so that the bottom length of the first auxiliary groove 20 is larger than the length of the bottom of the original first shallow groove when the first shallow groove continues to extend to the same depth along the side wall, the bottom length of the shallow groove is widened while the depth of the shallow groove isolation structure is increased, and the second shallow groove isolation structure also has similar conditions.

As an example, in the longitudinal direction, the cross-sectional shapes of the first auxiliary groove 20 and the second auxiliary groove 21 each include a rectangle, and the opening sizes of the tops of the cross-sectional shapes of the first shallow trench isolation structure 22 and the second shallow trench isolation structure 23 are each larger than the bottom side length of the corresponding rectangle, wherein the depth of the first shallow trench isolation structure 22 is larger than the depth of the second shallow trench isolation structure 23.

As an example, the top shapes of the cross-sectional shapes of the first shallow trench isolation structure 22 and the second shallow trench isolation structure 23 are respectively defined by a first shallow trench formed by a second trench above the first auxiliary trench and a first trench above the second auxiliary trench, and the second shallow trench formed by the first trench above the second auxiliary trench, each of which includes an inverted trapezoid, and the rectangular connection is located below the inverted trapezoid, wherein an obtuse angle range between a side wall of the inverted trapezoid defined by the first shallow trench 17 and a vertical direction includes 160 ° to 179.9 °, preferably 165 ° to 175 °, and in this example, 170 °; the second shallow trench 18 defines the inverted trapezoidal sidewall at an obtuse angle with respect to vertical ranging from 160 deg. to 179.9 deg., preferably from 165 deg. to 175 deg., and in this example is selected to be 170 deg..

Embodiment two:

as shown in fig. 23 to 36, the present invention provides a method for manufacturing a semiconductor device structure, comprising the steps of:

1) Preparing a shallow trench isolation structure array by adopting the preparation method according to any scheme of the first embodiment;

2) Removing the rest of the barrier layer 19, and filling the first shallow trench isolation structure 22 and the second shallow trench isolation structure 23 with an isolation medium layer 24; and

3) Buried word line structures are fabricated within the active region 161 and the isolation dielectric layer 24.

The method for fabricating the semiconductor device structure of the present invention will be described in detail with reference to the accompanying drawings.

First, step 1) is performed to prepare a shallow trench isolation structure array.

Next, step 2) is performed, as shown in fig. 23 to 32, the remaining barrier layer 19 is removed, and the isolation dielectric layer 24 is filled in the first shallow trench isolation structure 22 and the second shallow trench isolation structure 23.

As an example, in step 2), the dielectric constant value range of the material of the isolation dielectric layer 24 includes 0 to 3, and the material of the isolation dielectric layer 24 includes silicon oxide.

Specifically, the method further includes a step of densification treatment of the isolation dielectric layer 24 (such as silicon oxide) in the trench by annealing or the like, so that a transistor with good performance can be manufactured based on the shallow trench isolation structure array of the present application.

Finally, step 3) is performed to produce buried word line structures in the active region and the isolation dielectric layer 24, as shown in fig. 33-36.

As an example, step 3) specifically includes:

3-1) performing a first ion implantation into the active region to form a channel region 30;

3-2) continuing the second ion implantation and the third ion implantation into the active region to form a lightly doped drain region 31 and a shallow junction region 32 above the channel region 30 in sequence;

3-3) preparing a plurality of device trench structures 25 which are arranged in parallel at intervals along the transverse direction and pass through the active region 161 and the first and second shallow

trench isolation structures

22 and 23, and the bottoms of the device trench structures extend to the channel region 30; and

3-4) depositing a gate oxide layer 26 and a word line physical layer 28 on the surface of the device trench structure in sequence to obtain a buried word line structure, and filling the device trench structure with an insulating medium layer 29 covering the gate oxide layer 26 and the word line physical layer 28.

As an example, the implanted ions of the first ion implantation in step 3-1) include boron; the second ion implanted implant in step 3-2) comprises phosphorus and the third ion implanted implant comprises arsenic.

As an example, in step 3-4), the method further comprises the steps of: a word line surface layer 27 is formed between the gate oxide layer 26 and the word line physical layer 28, the word line surface layer 27 being used to define an active working area of the buried word line structure.

Specifically, since the word line surface layer 27 is directly in contact with the gate oxide layer, the effective operating area can be defined by designing the size of the word line surface layer, the word line entity layer 28 is responsible for conduction, and in addition, the word line surface layer 27 may have a different distance from the word line entity layer 28 to the surface of the semiconductor substrate 10, and the word line surface layer 27 may be set to be larger, thereby improving device performance.

As an example, the material of the word line surface layer 27 includes, but is not limited to, titanium nitride; materials of the word line physical layer 28 include, but are not limited to, tungsten; the material of the insulating dielectric layer 29 includes, but is not limited to, silicon nitride.

As an example, in step 3-3), the device trench structure 25 includes a first portion 251 located within the first shallow trench isolation structure 22 and the second shallow trench isolation structure 23, and a second portion 252 located within the active region 161, wherein a depth of the first portion 251 is greater than a depth of the second portion 252.

Specifically, during the process of preparing the device structure trench 25, that is, during the process of preparing the word line trench, more Silicon oxide than Silicon substrate is consumed in the post-etching stage by controlling the etching gas, the flow rate thereof, and the like, but preferably, both are controlled to be approximately equal.

As an example, in step 3-3), two device trench structures 25 pass through the same active region 161, and the same device trench structure 25 circulates and sequentially passes through the first shallow trench isolation structure 22, the active region 161, the second trench isolation structure 23, and the active region 161.

In particular, the "circulating and passing through in sequence" means that the structures listed later in sequence constitute a circulating unit through which the device trench structure 25 circulates. In this example, there is provided an array of shallow trench isolation structures and active regions formed in a semiconductor substrate, wherein in the direction C-D in fig. 14, one structure is a first trench 15, arranged in parallel at equal intervals, and one structure is a second trench 16 and active regions arranged at intervals to form a row of structures, each row of structures being alternately arranged at intervals with the first trench 15; in the longitudinal direction, the circulation units composed of the first shallow trench 17, the active region, the second shallow trench 18 and the active region are arranged in a circulation manner, and two such circulation units pass at the position of each active region and are arranged at equal intervals in the transverse direction (X-axis direction).

As an example, in step 3-3), the depth of the device trench structure 25 is smaller than the depth of the second shallow trench isolation structure 23; the device trench structure 25 has a height range of 100-300 nm, the second shallow trench isolation structure 23 has a height range of 200-600 nm, and the first shallow trench isolation structure has a height range of 200-700 nm.

As an example, the buried word line structure within the first shallow trench isolation structure 22 has the same depth as the buried word line structure within the second shallow trench isolation structure 23.

Specifically, the depth and profile of the large and small trenches are improved, when the word line etching is performed, the depth difference etched in the large and small trenches is reduced and even tends to be uniform, so that asymmetry of the FIN structure is reduced, the change of the depth of the WL trench in the large and small STI is improved by using the change of the STI, meanwhile, the formation of filling holes in the material filling process is improved, and the influence on the device performance caused by filling the holes is improved.

The invention also provides a semiconductor device structure, wherein the semiconductor device structure is preferably prepared by the preparation method of the invention, but is not limited to the method, and the semiconductor device structure comprises:

An array of shallow trench isolation structures according to any of the embodiments;

an isolation dielectric layer 24 filled in the first shallow trench isolation structure 22 and the first shallow trench isolation structure 23;

the plurality of buried word line structures are located in the active region and the isolation medium layer 24, and the buried word line structures are arranged at intervals in parallel along the lateral direction.

As an example, the buried word line includes:

device trench structures 25 arranged in parallel at intervals along the lateral direction and passing through the active region and the first trench isolation structure 22 and the second trench isolation structure 23;

a gate oxide layer 26 located at the bottom and part of the sidewall of the device trench structure 25; and

a word line surface layer 27 and a word line physical layer 28, wherein the word line surface layer 27 is positioned on the surface of the gate oxide layer 26, and the word line physical layer 28 is positioned on the surface of the word line surface layer 27.

As an example, the depth of the device trench structure 25 is smaller than the depth of the second shallow trench isolation structure 23; the device trench structure 25 has a height range of 100-300 nm, the second shallow trench isolation structure 23 has a height range of 200-600 nm, and the first shallow trench isolation structure has a height range of 200-700 nm.

As an example, two buried word line structures pass within the same active region, and the same buried word line structure loops through the first shallow trench isolation structure 22, the active region 161, the second trench isolation structure 23, and the active region in this order.

In addition, as shown in fig. 37, a comparative example is provided, which includes a substrate 33, an active region 34, an isolation structure 35, a surface metal layer 36 and a filling metal layer 37, and it can be seen that two adjacent different trench structures 35 have different sizes, resulting in a FIN structure having an asymmetry of D distance, and at the same time, the filling holes 38 in the filling metal layer 37 occur due to the larger difference between the upper and lower dimensions.

In summary, the present invention provides a shallow trench isolation structure, a semiconductor device and a preparation method thereof, wherein the preparation of the shallow trench isolation structure includes: providing a semiconductor substrate, wherein a transverse direction and a longitudinal direction which are perpendicular to each other are defined in a plane where the surface of the semiconductor substrate is located, a first mask layer is formed on the semiconductor substrate, the first mask layer comprises a plurality of first mask units which are arranged in parallel and have a first inclination angle relative to the longitudinal direction, and a first gap is formed between every two adjacent first mask units; forming a second mask layer on the semiconductor substrate, wherein the second mask layer is filled in the first gap and extends to cover the first mask layer, a plurality of auxiliary windows which are arranged in an array manner are formed on the second mask layer, each row of auxiliary windows is arranged at a second inclination angle in an equidistant manner relative to the longitudinal direction, a second gap is formed between every two adjacent auxiliary windows on the same row, the auxiliary windows expose the top of the first mask unit, the width of the second gap is matched with the width of the first gap, and the second inclination angle and the first inclination angle have different rotation angles; transferring the patterns on the first mask layer and the second mask layer into the semiconductor substrate, and reserving the rest first mask layer to form a first groove defined by the first gap and a second groove defined by the auxiliary window, and defining a plurality of active areas by adjacent second grooves along the extending direction of the first mask unit, wherein the second groove and the first grooves adjacent on two sides form a first shallow groove together along the longitudinal direction, and a second shallow groove formed by the first groove is arranged between the two adjacent first shallow grooves; and forming a blocking layer on the top and the side wall of the rest first mask layer and part of the side wall extending to the first shallow trench and the second shallow trench, and continuing etching the semiconductor substrate by taking the blocking layer as a mask, so that the first shallow trench is etched to a first depth to form a first shallow trench isolation structure, and the second shallow trench is etched to a second depth to form a second shallow trench isolation structure. By the scheme, the shallow trench isolation structures prepared by adopting the quantitative atomic layer deposition process and the multiple etching process are adopted, so that the asymmetry of the FIN structure caused by the difference of the sizes and the like between the adjacent shallow trench isolation structures is avoided, and the prepared structure, such as the buried word line, has the same depth when formed between the adjacent shallow trench isolation structures, thereby improving the problem of the difference of electric field intensity caused by the inconsistent depths and improving the critical voltage of devices; meanwhile, through reasonable structural design, the invention improves the defects of transistor manufacture caused by larger difference between the bottom opening width and the upper opening size of the shallow trench isolation structure, and relieves the phenomenon that filling holes (void) appear in metal when internal filling is carried out, such as when embedded word line filling word line metal (such as TiN/W) is prepared. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.

The above embodiments are merely illustrative of the principles of the present invention and its effectiveness, and are not intended to limit the invention. Modifications and variations may be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the invention. Accordingly, it is intended that all equivalent modifications and variations of the invention be covered by the claims, which are within the ordinary skill of the art, be within the spirit and scope of the present disclosure.

Claims

1. The preparation method of the shallow trench isolation structure array is characterized by comprising the following steps of:

2. The method according to claim 1, wherein in step 1), the first inclination angle forms an acute rotation angle of an inverse clock with respect to the longitudinal direction, and in step 2), the second inclination angle forms an acute rotation angle of a clockwise clock with respect to the longitudinal direction.

3. The method of claim 1, wherein in step 3), the step of transferring the patterns on the first mask layer and the second mask layer into the semiconductor substrate comprises: and etching the first mask layer by taking the second mask layer as a mask, removing the rest of the second mask layer, and continuing to etch the semiconductor substrate by taking the etched first mask layer as the mask.

4. The method of claim 1, wherein in the step 3), the depth of the first shallow trench is greater than the depth of the second shallow trench, and the cross-sectional shapes of the first shallow trench and the second shallow trench in the longitudinal direction each comprise an inverted trapezoid.

5. The method of claim 1, wherein in step 3), a plurality of circulation units are formed in the semiconductor substrate along the longitudinal direction, and each circulation unit includes a first shallow trench, an active region, a second shallow trench, and an active region in sequence.

6. The method of claim 1, wherein in step 4), the barrier layer is formed by an atomic layer deposition process, and the material of the barrier layer comprises aluminum oxide.

7. The method of claim 6, wherein the exposed sidewalls of the first and second shallow trenches have heights that respectively occupy 20% -70% of the height from the bottom of the first shallow trench to the surface of the barrier layer and the height from the bottom of the second shallow trench to the surface of the barrier layer.

8. The method of claim 1, wherein in step 4), the first shallow trench is etched to a first depth to form the first shallow trench isolation structure, the second shallow trench is etched to a second depth to form the second shallow trench isolation structure, wherein the first depth is greater than the second depth, and the difference between the first depth and the second depth is 30-70 nm; and the obtuse angles formed by the side walls of the cross section shapes of the structures formed by continuing etching and the vertical direction along the longitudinal direction are respectively larger than the obtuse angles formed by the side walls of the cross section shapes of the first shallow grooves and the second shallow grooves and the vertical direction.

9. The method according to any one of claims 1 to 8, wherein in the step 4), the bottoms of the cross-sectional shapes of the first and second shallow trench isolation structures each include a rectangle in the longitudinal direction, and the top opening sizes of the cross-sectional shapes are each larger than the bottom side length of the corresponding rectangle, and wherein the depth of the first shallow trench isolation structure is larger than the depth of the second shallow trench isolation structure.

10. The method of claim 9, wherein the top shape of the cross-sectional shape is defined by the first shallow trench and the second shallow trench, each of which comprises an inverted trapezoid, and the rectangular connection is located below the inverted trapezoid, wherein an obtuse angle range between a sidewall of the inverted trapezoid defined by the first shallow trench and a vertical direction comprises 160 ° -179.9 °; the obtuse angle range formed between the side wall of the inverted trapezoid defined by the second shallow groove and the vertical direction comprises 160-179.9 degrees.

11. The preparation method of the semiconductor device structure is characterized by comprising the following steps:

1) Preparing a shallow trench isolation structure array by adopting the preparation method as claimed in claim 1;

12. The method of fabricating a semiconductor device structure of claim 11, wherein step 3) specifically comprises: 3-1) performing a first ion implantation into the active region to form a channel region;

13. The method of fabricating a semiconductor device structure of claim 12, wherein in step 3-4), further comprising the steps of: and forming a word line surface layer between the gate oxide layer and the word line entity layer, wherein the word line surface layer is used for defining an effective working area of the embedded word line structure.

14. The method of claim 12, wherein in step 3-3), the device trench structure comprises a first portion within the first shallow trench isolation structure and the second shallow trench isolation structure and a second portion within the active region, the first portion having a depth greater than a depth of the second portion.

15. The method of claim 12, wherein in step 3-3), two device trench structures pass through the same active region, and the same device trench structure circulates and sequentially passes through the first shallow trench isolation structure, the active region, the second trench isolation structure, and the active region.

16. The method of fabricating a semiconductor device structure of claim 12, wherein in step 3-3), the depth of the device trench structure is less than the depth of the second shallow trench isolation structure; the height range of the device groove structure comprises 100-300 nanometers, the height range of the second shallow groove isolation structure comprises 200-600 nanometers, and the height range of the first shallow groove isolation structure comprises 200-700 nanometers.

17. The method of fabricating a semiconductor device structure of claim 12, wherein the first ion implanted implant of step 3-1) comprises boron; the second ion implanted implant in step 3-2) comprises phosphorus and the third ion implanted implant comprises arsenic.

18. The method of claim 11, wherein in step 2), the dielectric constant of the material of the isolation dielectric layer ranges from 0 to 3, and the material of the isolation dielectric layer comprises silicon oxide.

19. The method of any of claims 11-18, wherein the buried word line structure within the first shallow trench isolation structure has the same depth as the buried word line structure within the second shallow trench isolation structure.

20. An array of shallow trench isolation structures, comprising:

a semiconductor substrate, wherein the surface of the semiconductor substrate is defined with a transverse direction and a longitudinal direction which are perpendicular to each other in a plane, and the material of the semiconductor substrate comprises monocrystalline or polycrystalline semiconductor material;

the semiconductor substrate is provided with a plurality of first grooves which are arranged in parallel at equal intervals and a plurality of second grooves which are arranged in an array manner, and the first grooves have a first inclination angle relative to the longitudinal direction;

the semiconductor substrate comprises a plurality of active areas which are arranged in an array manner, each active area has the same outline, and each row of active areas and the first grooves are alternately arranged at intervals;

each second groove has the same outer contour, each row of second grooves is distributed at equal intervals relative to the longitudinal direction at a second inclination angle, the second grooves are positioned between gaps formed by adjacent active areas of each row, and the second inclination angles and the first inclination angles have different rotation angles; and the semiconductor substrate further has

The first auxiliary groove is positioned below the second groove and the first grooves adjacent to the two sides of the second groove, and forms a first shallow groove isolation structure together with the corresponding first grooves and second grooves;

the second auxiliary grooves are correspondingly positioned below the first grooves between two adjacent first auxiliary grooves along the longitudinal direction, and form a second shallow groove isolation structure with the corresponding first grooves.

21. The array of shallow trench isolation structures of claim 20, wherein the first auxiliary groove has a first depth and the second auxiliary groove has a second depth, wherein the first depth is greater than the second depth and the range of difference between the first depth and the second depth comprises 30-70 nanometers; and in the longitudinal direction, the obtuse angle between the side wall of the cross section of the first auxiliary groove and the vertical direction is larger than the obtuse angle between the side wall of the cross section of the first shallow groove formed by the second groove and the first groove above the first auxiliary groove and the vertical direction, and the obtuse angle between the side wall of the cross section of the second auxiliary groove and the vertical direction is larger than the obtuse angle between the side wall of the cross section of the second shallow groove formed by the first groove above the second auxiliary groove and the vertical direction.

22. The array of claim 20 or 21, wherein in the longitudinal direction, the cross-sectional shapes of the first and second auxiliary grooves each comprise a rectangle, and the top opening sizes of the cross-sectional shapes of the first and second shallow trench isolation structures are each greater than the bottom side length of the corresponding rectangle, wherein the depth of the first shallow trench isolation structure is greater than the depth of the second shallow trench isolation structure.

23. The array of claim 22, wherein the top shapes of the cross-sectional shapes of the first and second shallow trench isolation structures are respectively defined by a first shallow trench formed by a second trench above the first auxiliary trench and a first trench above the second auxiliary trench, and a second shallow trench formed by a first trench above the second auxiliary trench, each comprising an inverted trapezoid, and the rectangular connection is located below the inverted trapezoid, wherein an obtuse angle range between a sidewall of the inverted trapezoid defined by the first shallow trench and a vertical direction comprises 160 ° -179.9 °; the obtuse angle range formed between the side wall of the inverted trapezoid defined by the second shallow groove and the vertical direction comprises 160-179.9 degrees.

24. A semiconductor device structure, comprising:

the shallow trench isolation structure array of claim 20;

25. The semiconductor device structure of claim 24, wherein the buried word line comprises:

26. The semiconductor device structure of claim 25, wherein a depth of the device trench structure is less than a depth of the second shallow trench isolation structure; the height range of the device groove structure comprises 100-300 nanometers, the height range of the second shallow groove isolation structure comprises 200-600 nanometers, and the height range of the first shallow groove isolation structure comprises 200-700 nanometers.

27. The semiconductor device structure of claim 24, wherein two of the buried word line structures pass within a same active region, and the same buried word line structure loops and sequentially passes through the first shallow trench isolation structure, the active region, the second trench isolation structure, and the active region.

28. The semiconductor device structure of any of claims 24-27, wherein the buried word line structure within the first shallow trench isolation structure has the same depth as the buried word line structure within the second shallow trench isolation structure.