CN111613148A - Pixel arrangement structure of display screen - Google Patents
Pixel arrangement structure of display screen Download PDFInfo
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- CN111613148A CN111613148A CN202010489756.2A CN202010489756A CN111613148A CN 111613148 A CN111613148 A CN 111613148A CN 202010489756 A CN202010489756 A CN 202010489756A CN 111613148 A CN111613148 A CN 111613148A
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
- G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
- G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
- G09F9/302—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements characterised by the form or geometrical disposition of the individual elements
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/2003—Display of colours
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2300/00—Aspects of the constitution of display devices
- G09G2300/04—Structural and physical details of display devices
- G09G2300/0439—Pixel structures
- G09G2300/0443—Pixel structures with several sub-pixels for the same colour in a pixel, not specifically used to display gradations
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Abstract
The invention relates to the technical field of display screen pixel arrangement, in particular to a pixel arrangement structure of a display screen, which comprises four pixel groups which are sequentially arranged along the vertical direction, wherein the four pixel groups are sequentially arranged along the vertical direction, each pixel group comprises three element groups which are sequentially arranged along the vertical direction and have different types, and each four element groups which are sequentially arranged along the vertical direction form a pixel unit.
Description
Technical Field
The invention relates to the technical field of display screen pixel arrangement, in particular to a pixel arrangement structure of a display screen.
Background
With the high-speed development of display screens, the display screens with four narrow sides have become a dominant development trend, and the high screen ratio gives people a good visual effect; however, the number of the source wiring and the number of the driving circuits in the existing display screen are both large, so that not only can the frame of the display screen be increased, but also the power consumption of the IC chip in the display screen is increased.
Disclosure of Invention
The technical problem to be solved by the invention is as follows: provided is a pixel arrangement structure of a display panel capable of reducing a frame of the display panel.
In order to solve the technical problems, the invention adopts the technical scheme that:
the utility model provides a pixel arrangement structure of display screen, includes four pixel groups that arrange in proper order along vertical direction, every pixel group all includes that three arrange in proper order and the different element group of type along vertical direction, and every four arrange in proper order along vertical direction the element group constitutes a pixel cell, every the pixel cell is equallyd divide and is do not walked the line electricity with the first source electrode of peripheral hardware and is connected with the line electricity of second source electrode, every the pixel cell is all walked the line through five adjacent levels's grid and is connected with three drive circuit electricity respectively.
The invention has the beneficial effects that:
through setting up four pixel groups of arranging in proper order along vertical direction, every pixel group all includes that three arranges in proper order and the different element group of type along vertical direction, every four element groups of arranging in proper order along vertical direction constitute a pixel unit, make the quantity that the display screen source electrode walked the line greatly reduce like this, compare with ordinary display screen, the quantity that the source electrode walked the line of the display screen of this scheme design only is ordinary 2/9, so not only can reduce the lower frame of display screen, and the inside IC chip's of display screen consumption has still been reduced, the cost of manufacture has been reduced, the screen occupation of accounts for the ratio has been improved, the display effect is also preferred simultaneously.
Drawings
FIG. 1 is a schematic structural diagram of a pixel arrangement structure of a display panel according to the present invention;
FIG. 2 is a schematic structural diagram of a pixel arrangement structure of a display panel according to the present invention;
FIG. 3 is a waveform diagram of a first driving circuit, a second driving circuit and a third driving circuit of a pixel arrangement structure of a display panel according to the present invention;
description of reference numerals:
1. a first source line; 2. a second source line; 3. first-level grid routing; 4. second-level grid routing; 5. third-level grid routing; 6. fourth-level grid routing; 7. and a fifth level gate trace.
Detailed Description
In order to explain technical contents, achieved objects, and effects of the present invention in detail, the following description is made with reference to the accompanying drawings in combination with the embodiments.
Referring to fig. 1, the technical solution provided by the present invention is:
the utility model provides a pixel arrangement structure of display screen, includes four pixel groups that arrange in proper order along vertical direction, every pixel group all includes that three arrange in proper order and the different element group of type along vertical direction, and every four arrange in proper order along vertical direction the element group constitutes a pixel cell, every the pixel cell is equallyd divide and is do not walked the line electricity with the first source electrode of peripheral hardware and is connected with the line electricity of second source electrode, every the pixel cell is all walked the line through five adjacent levels's grid and is connected with three drive circuit electricity respectively.
From the above description, the beneficial effects of the present invention are:
through setting up four pixel groups of arranging in proper order along vertical direction, every pixel group all includes that three arranges in proper order and the different element group of type along vertical direction, every four element groups of arranging in proper order along vertical direction constitute a pixel unit, make the quantity that the display screen source electrode walked the line greatly reduce like this, compare with ordinary display screen, the quantity that the source electrode walked the line of the display screen of this scheme design only is ordinary 2/9, so not only can reduce the lower frame of display screen, and the inside IC chip's of display screen consumption has still been reduced, the cost of manufacture has been reduced, the screen occupation of accounts for the ratio has been improved, the display effect is also preferred simultaneously.
Furthermore, each element group comprises three elements which are sequentially arranged along the horizontal direction, and the three elements in the element group in the first row in the pixel unit are respectively and electrically connected with the peripheral first-level gate wire and the first source wire;
the elements of the first column in the element group of the second row in the pixel unit are respectively electrically connected with the elements of the second column in the element group of the first row in the same pixel unit, the peripheral second-level gate wire and the peripheral first source wire, the elements of the second column in the element group of the second row in the pixel unit are respectively electrically connected with the elements of the third column in the element group of the first row in the same pixel unit, the elements of the first column in the element group of the third row in the same pixel unit and the second-level gate wire, and the elements of the third column in the element group of the second row in the pixel unit are respectively electrically connected with the elements of the second column in the element group of the third row in the same pixel unit, the peripheral third-level gate wire and the peripheral second source wire;
the elements of the first column in the element group of the third row in the pixel unit are respectively and electrically connected with the peripheral third-level gate wiring and the peripheral first source wiring, the elements of the second column in the element group of the third row in the pixel unit are respectively and electrically connected with the elements of the first column in the element group of the fourth row in the same pixel unit and the peripheral fourth-level gate wiring, and the elements of the third column in the element group of the third row in the pixel unit are respectively and electrically connected with the elements of the second column in the element group of the fourth row in the same pixel unit, the peripheral fourth-level gate wiring and the peripheral second source wiring;
three elements in an element group of a fourth row in the pixel unit are electrically connected with a fifth-level peripheral gate wire, and elements of a third column in the element group of the fourth row in the pixel unit are electrically connected with a second peripheral source wire;
the first-level grid wire and the fifth-level grid wire are electrically connected and are electrically connected with the first driving circuit, the second-level grid wire and the fourth-level grid wire are electrically connected and are electrically connected with the second driving circuit, and the fourth-level grid wire and the third driving circuit are electrically connected.
Further, an element group of a first row in the pixel unit includes a first R element, a second R element, a third R element, a transistor T1, a transistor T2, and a transistor T3, an element group of a second row in the pixel unit includes a first G element, a second G element, a third G element, a transistor T4, a transistor T5, and a transistor T6, an element group of a third row in the pixel unit includes a first B element, a second B element, a third B element, a transistor T7, a transistor T8, and a transistor T9, and an element group of a fourth row in the pixel unit includes a fourth R element, a fifth R element, a sixth R element, a transistor T10, a transistor T11, and a transistor T12;
the first G element is electrically connected to a drain of the transistor T4 and a source of the transistor T2, respectively, the second G element is electrically connected to a drain of the transistor T5 and a source of the transistor T3, respectively, the third G element is electrically connected to a drain of the transistor T6 and a source of the transistor T8, respectively, the first B element is electrically connected to a drain of the transistor T7 and a source of the transistor T5, respectively, the second B element is electrically connected to a drain of the transistor T8 and a source of the transistor T10, respectively, the third B element is electrically connected to a drain of the transistor T9 and a source of the transistor T12, respectively, the first R element is electrically connected to a drain of the transistor T1, the second R element is electrically connected to a drain of the transistor T2, the third R element is electrically connected to a drain of the transistor T3, the fourth R element is electrically connected to a drain of the transistor T10, and the fifth R element is electrically connected to a drain of the transistor T11, the sixth R element is electrically connected with the drain electrode of the transistor T12, the source electrode of the transistor T1, the source electrode of the transistor T4 and the source electrode of the transistor T7 are all electrically connected with the first peripheral source wire, the gate of the transistor T1, the gate of the transistor T2 and the gate of the transistor T3 are all electrically connected to the peripheral first-level gate trace, the gate of the transistor T4 and the gate of the transistor T5 are both electrically connected to an external second level gate trace, the gate of the transistor T7 and the gate of the transistor T6 are both electrically connected to an external third level gate trace, the gate of the transistor T8 and the gate of the transistor T9 are both electrically connected to an external fourth-level gate trace, the gate of the transistor T10, the gate of the transistor T11 and the gate of the transistor T12 are all electrically connected to the peripheral fifth-level gate trace, the source of the transistor T6, the source of the transistor T9 and the source of the transistor T12 are all electrically connected to a second source trace of the peripheral.
Further, the first R element, the second R element, the third R element, the fourth R element, the fifth R element, and the sixth R element are all elements with the same type, the first G element, the second G element, and the third G element are all elements with the same type, and the first B element, the second B element, and the third B element are all elements with the same type.
Furthermore, the display colors of a first R element, a second R element, a third R element, a fourth R element, a fifth R element and a sixth R element in the pixel unit in the first row are all red, the display colors of a first G element, a second G element and a third G element are all green, and the display colors of a first B element, a second B element and a third B element are all blue.
Furthermore, the first source wire and the second source wire are parallel, two adjacent levels of the gate wires are parallel to each other, and the first source wire and the second source wire are perpendicular to the five levels of the gate wires respectively.
According to the description, the first source electrode wiring and the second source electrode wiring are parallel, the adjacent two-level grid electrode wiring is parallel, the first source electrode wiring and the second source electrode wiring are respectively perpendicular to the five-level grid electrode wiring, therefore, the wiring space inside the display screen can be effectively utilized, the screen occupation ratio of the display screen is favorably improved, and the display effect is better.
Referring to fig. 1 to fig. 3, a first embodiment of the present invention is:
referring to fig. 1, a pixel arrangement structure of a display screen includes four pixel groups sequentially arranged along a vertical direction, each pixel group includes three element groups sequentially arranged along the vertical direction and having different types, each four element groups sequentially arranged along the vertical direction form a pixel unit, each pixel unit is electrically connected to a first source trace 1 and a second source trace 2, which are externally arranged, and each pixel unit is electrically connected to three driving circuits through five adjacent gate traces.
Each element group comprises three elements which are sequentially arranged along the horizontal direction, and the three elements in the element group in the first row in the pixel unit are respectively and electrically connected with a first-level gate wire 3 and a first source wire 1 which are arranged externally;
the elements of the first column in the element group of the second row in the pixel unit are respectively electrically connected with the elements of the second column in the element group of the first row in the same pixel unit, the peripheral second-level gate wire 4 and the peripheral first source wire 1, the elements of the second column in the element group of the second row in the pixel unit are respectively electrically connected with the elements of the third column in the element group of the first row in the same pixel unit, the elements of the first column in the element group of the third row in the same pixel unit and the second-level gate wire 4, and the elements of the third column in the element group of the second row in the pixel unit are respectively electrically connected with the elements of the second column in the element group of the third row in the same pixel unit, the peripheral third-level gate5 and the peripheral second-level source wire 2;
the elements in the first column in the element group in the third row in the pixel unit are electrically connected with the peripheral third-level gate wire 5 and the peripheral first source wire 1 respectively, the elements in the second column in the element group in the third row in the pixel unit are electrically connected with the elements in the first column in the element group in the fourth row in the same pixel unit and the peripheral fourth-level gate wire 6 respectively, and the elements in the third column in the element group in the third row in the pixel unit are electrically connected with the elements in the second column in the element group in the fourth row in the same pixel unit, the peripheral fourth-level gate wire 6 and the peripheral second source wire 2 respectively;
three elements in the element group of the fourth row in the pixel unit are electrically connected with a peripheral fifth-level gate wire 7, and the elements of the third column in the element group of the fourth row in the pixel unit are electrically connected with a peripheral second source wire 2;
the first-level gate wire 3 is electrically connected with the fifth-level gate wire 7 and is electrically connected with the first driving circuit, the second-level gate wire 4 is electrically connected with the fourth-level gate wire 6 and is electrically connected with the second driving circuit, and the fourth-level gate wire 6 is electrically connected with the third driving circuit.
The first driving circuit, the second driving circuit and the third driving circuit have the same structure, and the specific circuit structures of the first driving circuit, the second driving circuit and the third driving circuit are all conventional GIP driving circuits.
A group of elements of a first row in the pixel unit includes a first R element, a second R element, a third R element, a transistor T1, a transistor T2, and a transistor T3, a group of elements of a second row in the pixel unit includes a first G element, a second G element, a third G element, a transistor T4, a transistor T5, and a transistor T6, a group of elements of a third row in the pixel unit includes a first B element, a second B element, a third B element, a transistor T7, a transistor T8, and a transistor T9, and a group of elements of a fourth row in the pixel unit includes a fourth R element, a fifth R element, a sixth R element, a transistor T10, a transistor T11, and a transistor T12;
the first G element is electrically connected to a drain of the transistor T4 and a source of the transistor T2, respectively, the second G element is electrically connected to a drain of the transistor T5 and a source of the transistor T3, respectively, the third G element is electrically connected to a drain of the transistor T6 and a source of the transistor T8, respectively, the first B element is electrically connected to a drain of the transistor T7 and a source of the transistor T5, respectively, the second B element is electrically connected to a drain of the transistor T8 and a source of the transistor T10, respectively, the third B element is electrically connected to a drain of the transistor T9 and a source of the transistor T12, respectively, the first R element is electrically connected to a drain of the transistor T1, the second R element is electrically connected to a drain of the transistor T2, the third R element is electrically connected to a drain of the transistor T3, the fourth R element is electrically connected to a drain of the transistor T10, and the fifth R element is electrically connected to a drain of the transistor T11, the sixth R element is electrically connected to the drain of the transistor T12, the source of the transistor T1, the source of the transistor T4, and the source of the transistor T7 are all electrically connected to the first peripheral source trace 1, the gate of the transistor T1, the gate of the transistor T2 and the gate of the transistor T3 are all electrically connected to the peripheral first-level gate trace 3, the gate of the transistor T4 and the gate of the transistor T5 are both electrically connected to the peripheral second level gate trace 4, the gate of the transistor T7 and the gate of the transistor T6 are both electrically connected to the peripheral third level gate trace 5, the gate of the transistor T8 and the gate of the transistor T9 are both electrically connected to the peripheral fourth stage gate trace 6, the gate of the transistor T10, the gate of the transistor T11 and the gate of the transistor T12 are all electrically connected to the peripheral fifth-level gate trace 7, the source of the transistor T6, the source of the transistor T9 and the source of the transistor T12 are all electrically connected to the peripheral second source trace 2.
The first R element, the second R element, the third R element, the fourth R element, the fifth R element and the sixth R element are all elements with the same type, the first G element, the second G element and the third G element are all elements with the same type, and the first B element, the second B element and the third B element are all elements with the same type.
The display colors of a first R element, a second R element, a third R element, a fourth R element, a fifth R element and a sixth R element in the pixel unit in the first row are all red, the display colors of a first G element, a second G element and a third G element are all green, and the display colors of a first B element, a second B element and a third B element are all blue.
The first source electrode wire 1 is parallel to the second source electrode wire 2, two adjacent levels of the grid electrode wires are parallel to each other, and the first source electrode wire 1 and the second source electrode wire 2 are respectively perpendicular to the five levels of the grid electrode wires.
The pixel arrangement structure of the display screen is implemented as follows:
the pixel arrangement shown in fig. 1 is a basic unit, and the pixel structures at other positions of the display screen will repeatedly appear according to the basic unit;
the display color of each row of elements (also called sub-pixels) is the same, and the colors of the sub-pixels adjacent to each other up and down in the column direction are different;
referring to fig. 2, the R1 sub-pixel (hereinafter directly denoted by R1) is connected to the drain of the transistor T1 (hereinafter directly denoted by T1), and the Source of T1 is connected to the first Source trace 1 (in the figure, Source1 is denoted by S1, and first Source trace 1 is denoted by S3583); a source of a transistor T2 (hereinafter, directly denoted by T2) connected to an R2 sub-pixel (hereinafter, directly denoted by R2) is connected to a pixel electrode of a G1 sub-pixel (hereinafter, directly denoted by G1), and a source of a transistor T4 (hereinafter, directly denoted by T4) connected to G1 is connected to S1, at which time S1 transmits data required for R2 to R2 by controlling T4 of G1; a source of a transistor T3 (hereinafter, directly denoted by T3) connected to an R3 sub-pixel (hereinafter, directly denoted by R3) is connected to a pixel electrode of a G2 sub-pixel (hereinafter, directly denoted by G2), a source of a transistor T5 (hereinafter, directly denoted by T5) connected to G2 is connected to a pixel electrode of a B1 sub-pixel (hereinafter, directly denoted by B1), at this time, S1 transfers data required by G2 to G2 through a transistor T7 (hereinafter, directly denoted by T7) controlling B1, and R3 requires S1 to transfer data of R3 to G2, and G2 is transferred to R3 through control T3, so that R3 and G2 sub-pixels obtain corresponding data; a Source of T6 (hereinafter, directly denoted by T6) connected to a G3 sub-pixel (hereinafter, directly denoted by G3) is connected to a second Source trace 2 (in the figure, Source2 is denoted by S2, and second Source trace 2 is directly denoted by S2), a pixel electrode of G3 is connected to a Source of B2, a pixel electrode of B2 is connected to a Source of an R4 sub-pixel (hereinafter, directly denoted by R4), S2 transmits data required by B2 to B2 through control T6, and R4 transmits data of R4 to B2 through S1, and then B2 is transmitted to R4, so that B2 and R4 obtain corresponding data; the source of a transistor T9 (hereinafter, directly indicated by T9) connected with a B3 sub-pixel (hereinafter, directly indicated by B3) is connected with S2, the drain of another T9 is connected with the pixel electrode of B3, the pixel electrode of B3 is connected with the source of an R5 sub-pixel (hereinafter, directly indicated by R5), when the R5 needs to transmit data, S2 transmits the data required by R5 to the pixel electrode of B3, the pixel electrode of B3 transmits the data to the pixel electrode of R5 through controlling the source of a transistor T11 (hereinafter, directly indicated by T11) of R5, and R5 obtains the required voltage data; the source of the transistor T12 (hereinafter, directly denoted by T12) connected to the R6 sub-pixel (hereinafter, directly denoted by R6) is connected to S2, the drain of T12 is connected to the pixel electrode of R6, and the R6 data is directly transmitted from S2.
According to the scheme, the Gate1 (namely the first-level Gate wire 3) and the Gate5 (namely the fifth-level Gate wire 7) are pulled together, namely the Gate waveforms of the Gate1 and the Gate5 are completely the same, the Gate is opened and closed simultaneously, the Gate2 (namely the second-level Gate wire 4) and the Gate4 (namely the fourth-level Gate wire 6) are pulled together, the Gate waveforms of the Gate2 and the Gate4 are completely the same, the Gate and the Gate are opened and closed simultaneously, the Gate3 (namely the third-level Gate wire 5) is a single Gate waveform, and thus the driving circuit of the display screen is saved.
The connection manner of the transistors and the sub-pixels from the Gate6 (i.e., the sixth-level Gate trace) to the Gate10 (i.e., the tenth-level Gate trace) is the same as that from the Gate1 to the Gate5, except that the color of the sub-pixels in each row is not in one-to-one correspondence with the color of the sub-pixels between the Gate1 and the Gate5, and the connection manner of the transistors and the sub-pixels from the Gate11 (i.e., the eleventh-level Gate trace) to the Gate15 (i.e., the fifteenth-level Gate trace) is the same as that from the Gate1 to the Gate5, except that the color of the sub-pixels is not in one-to-one correspondence, and the connection manner of the other structures is completely the same as that of the sub-pixels from the Gate1 to the Gate5, which is. The sub-pixels from Gate1 to Gate15 and their special pixel connection form the basic unit of the present scheme, and the display screen will be developed based on the basic unit at other positions of the display screen, and the display screen will be composed of many basic units.
The working principle of the pixel arrangement structure of the display screen in the scheme is as follows (refer to fig. 3):
each sub-pixel is transmitted at a specific time point in cooperation with a specific time sequence;
in the period of T1, Gate 1-Gate 5 are all turned on, in S1, since Gate1, Gate2 and Gate3 are all turned on (i.e. high voltage), i.e. the transistors of B1, G2 and R3 sub-pixels (i.e. T7, T5 and T3) are controlled to be in on state, S1 transmits the data with R3 sub-pixels to R3 sub-pixels through the transistors (i.e. T7 and T5) controlling B1 and G2 sub-pixels and sub-pixel electrodes thereof; the voltage data at the sub-pixels B1, G2, G1, R1 and R2 at time T1 is also the voltage data of the sub-pixel R3, followed by accurate data transmission.
In the period T2, the Gate3 is at low voltage, the transistor (including T6 and T7) connected to the Gate3 is in off state, and the sub-pixel electrodes of B1, G2 and R3 are at the same voltage, the R3 sub-pixel obtains the desired data, the voltage data of R3 sub-pixel is present on the B1 and G2 sub-pixel electrodes, and the sub-pixel data of B1 and G2 are correctly transmitted in the subsequent time sequence; the Gate1 and Gate2 are still at high voltage, the corresponding transistors (i.e. T1, T2 and T3) are turned on, S1 transmits the data of R2 to the source of R2 through T4 and its pixel electrode, since T2 is controlled to be turned on, the source of T2 directly transmits the voltage data required by R2 to the pixel electrode of R2, the voltage of the electrode of the R2 sub-pixel is changed from the voltage of the R3 data at the time of T1 to the correct data voltage of the R2 sub-pixel, the voltage of the data of the sub-pixel on R1 is changed from the voltage of the sub-pixel on R3 to the voltage of the sub-pixel on R2, and the voltage of the sub-pixel on G1 is the voltage of the sub-pixel on R2.
In the period of T3, Gate2 and Gate3 are at low voltage, the transistors (T4, T5, T6 and T7) on the corresponding Gate2 and Gate3 are in off state, the voltages of G1 and R2 sub-pixels are kept consistent, the R2 sub-pixel obtains the required voltage, only the Gate1 is in on state, the transistors (i.e., T1, T2 and T3) on the Gate1 are in on state, and S1 directly transmits the sub-pixel data of R1 by controlling T1.
In the period of T4, Gate1 is completely turned off, the potentials on the R1, R2 and R3 sub-pixels maintain the correct voltage required by the sub-pixels, Gate2 and Gate3 are high potentials, the voltage data of the G2 sub-pixels are on the B1, G1 and G2 sub-pixels, and the G2 sub-pixel obtains the required voltage data; the sub-pixel voltage of G1 changes from R2 at T3 to G2.
In the period of T5, Gate3 is turned off, and the sub-pixel voltages of G2 and B1 are kept as the sub-pixel voltage data of G2, since only Gate2 is turned on at the time of T5, S1 directly transmits the sub-pixel data of G1 to the sub-pixel electrode of G1; the sub-pixel voltage of G1 is changed from the sub-pixel voltage data of G2 at time T4 to the correct sub-pixel voltage data of G1.
During the period T6, Gate1, Gate2 and Gate3 are at low voltage, the corresponding transistors (i.e., T1, T2, T3, T4, T5, T6 and T7) are in off state, and S1 directly transmits the sub-pixel voltage data of B1 to B1.
The above timing is the sub-pixel voltage data transmission timing corresponding to S1, and the transmission principle in S2 is similar to that in S1, and the sub-pixel data transmission in S2 is described as follows:
in the period of T1, Gate 1-Gate 5 are all turned on, in S2, since Gate3, Gate4 and Gate5 are all turned on (i.e. high voltage), i.e. transistors of G3, B2 and R4 sub-pixels (i.e. T6, T8 and T10) are controlled to be in on-state, S1 transmits data with R4 sub-pixels to R4 sub-pixels through transistors of G3 and B2 sub-pixels and sub-pixel electrodes thereof; at time T1, the voltage data for the G3, B2, B3, R5 and R6 subpixels are also the voltage data for the R4 subpixel, followed by accurate data transmission.
In the period T2, the Gate3 is at low voltage, the transistors (i.e., T6 and T7) on the Gate3 are in off state, and the sub-pixel electrodes of G3, B2 and R4 are at the same voltage, the R4 sub-pixel obtains the desired data, the voltage data of the R4 sub-pixel is present on the G3 and B2 sub-pixel electrodes, and the sub-pixel data of G3 and B2 are correctly transmitted in the subsequent timing; at time T2, Gate4 and Gate5 are still at high voltage, the corresponding transistors are turned on, S2 transmits data of R5 to the source of T11 through T9 and the pixel electrode thereof, since T11 is controlled to be on, the source of T11 directly transmits voltage data required by R5 to the pixel electrode of R5, at this time, the electrode voltage of R5 sub-pixel is changed from the data voltage of R4 at time T1 to the correct sub-pixel data voltage of R5, the sub-pixel data voltage on R6 is changed from the sub-pixel voltage of R4 to the sub-pixel voltage of R5, and the sub-pixel voltage of R5 is applied to B3.
In the period of T3, Gate3 and Gate4 are at low voltage, the transistors on the corresponding Gate3 and Gate4 (i.e., T6, T7, T8 and T9) are in off state, the potentials of the B3 and R5 sub-pixels are kept consistent, the R5 sub-pixel obtains the required voltage, only the Gate5 is in on state, the transistors on the Gate5 (i.e., T10, T11 and T12) are in on state, and S2 directly transmits the sub-pixel data of R6 by controlling T12.
In the period of T4, the Gate5 is completely turned off, the potentials on the R4, R5 and R6 sub-pixels maintain the correct voltage required by the sub-pixels, the gates 3 and 4 are high potentials, the voltage data of the B2 sub-pixels are on the B2, B3 and G3 sub-pixels, and the B2 sub-pixel obtains the required voltage data; the sub-pixel voltage of B3 is changed from R5 at T3 to B2, and the sub-pixel voltage of G3 is changed from R4 at T1 to B2.
In the period of T5, both Gate3 and Gate4 are turned off (i.e. low voltage), the G3 sub-pixel voltage is kept as the voltage data of B2 sub-pixel, since only Gate4 is turned on at the time of T5, S2 directly transmits the sub-pixel data of B3 to the sub-pixel electrode of B3, and the sub-pixel voltage of B3 is changed from the sub-pixel voltage data of B2 at the time of T4 to the correct sub-pixel voltage data of B3 as required.
In the period T6, Gate4 and Gate5 are at low voltage, the transistors (i.e., T8, T9, T10, T11 and T12) on the corresponding Gate4 and Gate5 are all in off state, S2 directly transmits the voltage data of the G3 sub-pixel to the sub-pixel electrode of G3, and G3 sub-pixel is changed from the sub-pixel voltage data of B2 at the time T4 to the sub-pixel voltage data of G3 required correctly.
In summary, according to the pixel arrangement structure of the display screen provided by the invention, four pixel groups are arranged in sequence along the vertical direction, each pixel group includes three element groups which are arranged in sequence along the vertical direction and have different types, and each four element groups which are arranged in sequence along the vertical direction form a pixel unit, so that the number of source electrode wires of the display screen is greatly reduced.
The above description is only an embodiment of the present invention, and not intended to limit the scope of the present invention, and all equivalent changes made by using the contents of the present specification and the drawings, or applied directly or indirectly to the related technical fields, are included in the scope of the present invention.
Claims (6)
1. The utility model provides a pixel arrangement structure of display screen, its characterized in that includes four pixel groups that arrange in proper order along vertical direction, every pixel group all includes three element group that arrange in proper order and the type is different along vertical direction, and every four arrange in proper order along vertical direction the element group constitutes a pixel cell, every pixel cell equallys divide and walks to walk line electricity with the first source electrode of peripheral hardware and walk line electricity with the second source electrode and be connected, every pixel cell all walks to be connected with three drive circuit electricity respectively through five adjacent grade gate.
2. The pixel arrangement structure of the display screen according to claim 1, wherein each of the element groups includes three elements sequentially arranged in a horizontal direction, and three elements in the element group in the first row in the pixel unit are electrically connected to the peripheral first-level gate trace and the first source trace, respectively;
the elements of the first column in the element group of the second row in the pixel unit are respectively electrically connected with the elements of the second column in the element group of the first row in the same pixel unit, the peripheral second-level gate wire and the peripheral first source wire, the elements of the second column in the element group of the second row in the pixel unit are respectively electrically connected with the elements of the third column in the element group of the first row in the same pixel unit, the elements of the first column in the element group of the third row in the same pixel unit and the second-level gate wire, and the elements of the third column in the element group of the second row in the pixel unit are respectively electrically connected with the elements of the second column in the element group of the third row in the same pixel unit, the peripheral third-level gate wire and the peripheral second source wire;
the elements of the first column in the element group of the third row in the pixel unit are respectively and electrically connected with the peripheral third-level gate wiring and the peripheral first source wiring, the elements of the second column in the element group of the third row in the pixel unit are respectively and electrically connected with the elements of the first column in the element group of the fourth row in the same pixel unit and the peripheral fourth-level gate wiring, and the elements of the third column in the element group of the third row in the pixel unit are respectively and electrically connected with the elements of the second column in the element group of the fourth row in the same pixel unit, the peripheral fourth-level gate wiring and the peripheral second source wiring;
three elements in an element group of a fourth row in the pixel unit are electrically connected with a fifth-level peripheral gate wire, and elements of a third column in the element group of the fourth row in the pixel unit are electrically connected with a second peripheral source wire;
the first-level grid wire and the fifth-level grid wire are electrically connected and are electrically connected with the first driving circuit, the second-level grid wire and the fourth-level grid wire are electrically connected and are electrically connected with the second driving circuit, and the fourth-level grid wire and the third driving circuit are electrically connected.
3. The pixel arrangement structure of a display panel according to claim 2, wherein an element group of a first row in the pixel unit includes a first R element, a second R element, a third R element, a transistor T1, a transistor T2, and a transistor T3, an element group of a second row in the pixel unit includes a first G element, a second G element, a third G element, a transistor T4, a transistor T5, and a transistor T6, an element group of a third row in the pixel unit includes a first B element, a second B element, a third B element, a transistor T7, a transistor T8, and a transistor T9, and an element group of a fourth row in the pixel unit includes a fourth R element, a fifth R element, a sixth R element, a transistor T10, a transistor T11, and a transistor T12;
the first G element is electrically connected to a drain of the transistor T4 and a source of the transistor T2, respectively, the second G element is electrically connected to a drain of the transistor T5 and a source of the transistor T3, respectively, the third G element is electrically connected to a drain of the transistor T6 and a source of the transistor T8, respectively, the first B element is electrically connected to a drain of the transistor T7 and a source of the transistor T5, respectively, the second B element is electrically connected to a drain of the transistor T8 and a source of the transistor T10, respectively, the third B element is electrically connected to a drain of the transistor T9 and a source of the transistor T12, respectively, the first R element is electrically connected to a drain of the transistor T1, the second R element is electrically connected to a drain of the transistor T2, the third R element is electrically connected to a drain of the transistor T3, the fourth R element is electrically connected to a drain of the transistor T10, and the fifth R element is electrically connected to a drain of the transistor T11, the sixth R element is electrically connected with the drain electrode of the transistor T12, the source electrode of the transistor T1, the source electrode of the transistor T4 and the source electrode of the transistor T7 are all electrically connected with the first peripheral source wire, the gate of the transistor T1, the gate of the transistor T2 and the gate of the transistor T3 are all electrically connected to the peripheral first-level gate trace, the gate of the transistor T4 and the gate of the transistor T5 are both electrically connected to an external second level gate trace, the gate of the transistor T7 and the gate of the transistor T6 are both electrically connected to an external third level gate trace, the gate of the transistor T8 and the gate of the transistor T9 are both electrically connected to an external fourth-level gate trace, the gate of the transistor T10, the gate of the transistor T11 and the gate of the transistor T12 are all electrically connected to the peripheral fifth-level gate trace, the source of the transistor T6, the source of the transistor T9 and the source of the transistor T12 are all electrically connected to a second source trace of the peripheral.
4. The pixel arrangement structure of the display screen according to claim 3, wherein the first R element, the second R element, the third R element, the fourth R element, the fifth R element, and the sixth R element are all elements of the same type, the first G element, the second G element, and the third G element are all elements of the same type, and the first B element, the second B element, and the third B element are all elements of the same type.
5. The pixel arrangement structure of the display screen according to claim 4, wherein display colors of a first R element, a second R element, a third R element, a fourth R element, a fifth R element, and a sixth R element in the pixel unit of the first row are all red, display colors of a first G element, a second G element, and a third G element are all green, and display colors of a first B element, a second B element, and a third B element are all blue.
6. The pixel arrangement structure of the display screen according to claim 1, wherein the first source trace and the second source trace are parallel, two adjacent levels of the gate traces are parallel to each other, and the first source trace and the second source trace are perpendicular to the five levels of the gate traces respectively.
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Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006106062A (en) * | 2004-09-30 | 2006-04-20 | Sharp Corp | Active matrix type liquid crystal display device and liquid crystal display panel used for same |
| CN103149762A (en) * | 2013-02-28 | 2013-06-12 | 北京京东方光电科技有限公司 | Array substrate, display unit and control method thereof |
| CN103185976A (en) * | 2011-12-31 | 2013-07-03 | 上海中航光电子有限公司 | Liquid crystal display device and drive method thereof |
| CN104485084A (en) * | 2014-11-28 | 2015-04-01 | 友达光电股份有限公司 | Display panel |
| CN107611156A (en) * | 2016-07-12 | 2018-01-19 | 株式会社日本显示器 | Display device |
| CN108630105A (en) * | 2018-05-10 | 2018-10-09 | 京东方科技集团股份有限公司 | A kind of array substrate, display panel and display device |
| CN212322558U (en) * | 2020-06-02 | 2021-01-08 | 福建华佳彩有限公司 | Pixel arrangement structure of display screen |
-
2020
- 2020-06-02 CN CN202010489756.2A patent/CN111613148A/en not_active Withdrawn
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006106062A (en) * | 2004-09-30 | 2006-04-20 | Sharp Corp | Active matrix type liquid crystal display device and liquid crystal display panel used for same |
| CN103185976A (en) * | 2011-12-31 | 2013-07-03 | 上海中航光电子有限公司 | Liquid crystal display device and drive method thereof |
| CN103149762A (en) * | 2013-02-28 | 2013-06-12 | 北京京东方光电科技有限公司 | Array substrate, display unit and control method thereof |
| CN104485084A (en) * | 2014-11-28 | 2015-04-01 | 友达光电股份有限公司 | Display panel |
| CN107611156A (en) * | 2016-07-12 | 2018-01-19 | 株式会社日本显示器 | Display device |
| CN108630105A (en) * | 2018-05-10 | 2018-10-09 | 京东方科技集团股份有限公司 | A kind of array substrate, display panel and display device |
| CN212322558U (en) * | 2020-06-02 | 2021-01-08 | 福建华佳彩有限公司 | Pixel arrangement structure of display screen |
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