CN111599861A - Semiconductor structure and manufacturing method thereof - Google Patents
Semiconductor structure and manufacturing method thereof Download PDFInfo
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- CN111599861A CN111599861A CN201910853606.2A CN201910853606A CN111599861A CN 111599861 A CN111599861 A CN 111599861A CN 201910853606 A CN201910853606 A CN 201910853606A CN 111599861 A CN111599861 A CN 111599861A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 52
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 17
- 239000000758 substrate Substances 0.000 claims abstract description 38
- 230000005669 field effect Effects 0.000 claims description 30
- 238000000034 method Methods 0.000 claims description 16
- 238000002955 isolation Methods 0.000 description 56
- 239000000463 material Substances 0.000 description 8
- -1 phosphorus ions Chemical class 0.000 description 6
- 238000005468 ion implantation Methods 0.000 description 5
- 239000000203 mixture Substances 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 229910052785 arsenic Inorganic materials 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- 239000002800 charge carrier Substances 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 229910001449 indium ion Inorganic materials 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 230000004075 alteration Effects 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
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Abstract
The invention provides a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes: the semiconductor device comprises a substrate, a first conductive type trap, a second conductive type buried layer, a first conductive type trap, a first conductive type doped region, a second conductive type trap and a second conductive type doped region. The first conductive type well is disposed on the substrate. The second conductive buried layer is disposed in the first conductive well and spaced apart from the substrate by a first predetermined distance. The first and second conductive type traps are arranged in the first conductive type trap, located on the second conductive type buried layer and connected to the second conductive type buried layer. The first and second conductive type doped regions are disposed in the first and second conductive type wells. The second conductive type trap is arranged in the first conductive type trap and above the second conductive type buried layer, and is separated from the second conductive type buried layer by a second predetermined distance. The second conductive type doped region is disposed in the second conductive type well.
Description
Technical Field
The present invention relates to a semiconductor structure, and more particularly, to a semiconductor structure of junction field effect transistor with high current and low pinch-off voltage and a method for fabricating the same.
Background
In the semiconductor industry, there are two main types of Field Effect Transistors (FETs), namely Insulated Gate Field Effect Transistors (IGFETs), commonly referred to as Metal Oxide Semiconductor Field Effect Transistors (MOSFETs), and Junction Field Effect Transistors (JFETs). The structural configurations of the mosfet and the junction fet are not substantially the same. For example, a gate of a mosfet includes an insulating layer, i.e., a gate oxide layer, between the gate and other electrodes of the transistor. Thus, the channel current in the mosfet is controlled by the electric field across the channel to enhance and deplete the channel region as desired (deplate). The gate of the junction field effect transistor forms a P-N junction (P-N junction) with the other electrodes of the transistor, and the junction field effect transistor can be reverse biased by applying a predetermined gate voltage. Thus, by varying the size of the depletion region within the channel, the gate P-N junction of the junction field effect transistor can be utilized to control the channel current.
In general, junction field effect transistors may act as voltage controlled resistors or electronically controlled switches. P-junction field effect transistors have a channel of doped semiconductor material with a large number of positive charge carriers or holes, while N-junction field effect transistors have a channel of doped semiconductor material with a large number of negative charge carriers or electrons. At each end of the junction field effect transistor, a source and a drain are formed by ohmic contacts, and a current flows through a channel between the source and the drain. In addition, current flow may be impeded or turned off by applying a reverse bias to the gate, also known as "pinch-off.
Although the conventional junction field effect transistors of semiconductor structure and the manufacturing method thereof have been gradually satisfactory for their intended applications, the junction field effect transistors always have a trade-off relationship between the on-current and the pinch-off voltage, and generally, when the on-current needs to be increased, the pinch-off voltage is increased, so that the low pinch-off voltage cannot be maintained, thereby causing design difficulties.
Disclosure of Invention
In view of the foregoing, the present invention provides a semiconductor structure comprising: the semiconductor device includes a substrate, a first conductive type well, a second conductive type buried layer, a first second conductive type well, a first second conductive type doped region, a second conductive type well and a second conductive type doped region. The first conductive type well is arranged in the substrate. The second conductive buried layer is disposed in the first conductive well and spaced apart from the substrate by a first predetermined distance. The first and second conductive type wells are disposed in the first conductive type well, located above the second conductive type buried layer, and connected to the second conductive type buried layer. The first and second conductive type doped regions are disposed in the first and second conductive type wells. The second conductive type well is disposed in the first conductive type well and above the second conductive type buried layer, and is spaced apart from the second conductive type buried layer by a second predetermined distance. The second doped region of the second conductivity type is disposed in the well of the second conductivity type.
According to an embodiment of the present invention, the semiconductor structure further includes: a first conductive type doped region, a second first conductive type doped region and a third first conductive type doped region. The first conductive type doped region is disposed in the first conductive type well and between the first conductive type well and the second conductive type well. The second first-conductivity-type doped region is disposed in the first-conductivity-type well, wherein the first-conductivity-type doped region and the second first-conductivity-type doped region are disposed on two sides of the second-conductivity-type well, respectively. The third doped region of the first conductivity type is disposed in the well of the first conductivity type, wherein the doped regions of the first conductivity type and the third doped region of the first conductivity type are disposed on two sides of the well of the first and second conductivity types, respectively.
According to an embodiment of the present invention, the first and second doped regions are connected to a first electrode, wherein the first and third doped regions are connected to a second electrode, and wherein the second doped region is connected to a third electrode.
According to an embodiment of the present invention, the semiconductor structure is a junction field effect transistor of a first conductivity type, wherein the first electrode is a gate terminal, the second electrode is a source terminal, and the third electrode is a drain terminal.
According to an embodiment of the present invention, the second conductive type well has an effective length, wherein at least half of the effective length of the second conductive type well overlaps the second conductive type buried layer.
The present invention further provides a method for manufacturing a semiconductor structure, comprising: providing a substrate; forming a first conductive type well in the substrate; forming a second conductive buried layer in the first conductive type well, and at a first predetermined distance from the substrate; forming a first and second conductive type well in the first conductive type well and on the second conductive type buried layer, wherein the first and second conductive type well is connected to the second conductive type buried layer; forming a second well of a second conductivity type in the well of the first conductivity type and on the buried layer of the second conductivity type, wherein the well of the second conductivity type is spaced from the buried layer of the second conductivity type by a second predetermined distance; forming a first and second conductive type doped region in the first and second conductive type well; and forming a second conductive type doped region in the second conductive type well.
According to an embodiment of the present invention, the manufacturing method further includes: forming a first conductive type doped region in the first conductive type well and between the first conductive type well and the second conductive type well; forming a second doped region of the first conductivity type in the well, wherein the first doped region of the first conductivity type and the second doped region of the first conductivity type are respectively located at two sides of the well; and forming a third first conductive type doped region in the first conductive type well, wherein the first conductive type doped region and the third first conductive type doped region are respectively disposed on two sides of the first second conductive type well.
According to an embodiment of the present invention, the manufacturing method further includes: coupling the first and second conductive type doped regions to a first electrode; connecting the first and third first conductive type doped regions to a second electrode; and connecting the second first conductive type doped region to a third electrode.
According to an embodiment of the present invention, the semiconductor structure is a junction field effect transistor of a first conductivity type, wherein the first electrode is a gate terminal, the second electrode is a source terminal, and the third electrode is a drain terminal.
According to an embodiment of the present invention, the second conductive type well has an effective length, wherein at least half of the effective length of the second conductive type well overlaps the second conductive type buried layer.
Drawings
FIG. 1 is a cross-sectional view of a semiconductor structure according to an embodiment of the present invention;
FIG. 2 is a cross-sectional view of a semiconductor structure according to another embodiment of the present invention;
FIG. 3 is a cross-sectional view of a semiconductor structure according to another embodiment of the present invention; and
fig. 4A to 4D are schematic views illustrating a method for fabricating a semiconductor structure according to an embodiment of the invention.
Reference numerals
100 semiconductor structure
200 semiconductor structure
300 semiconductor structure
110 substrate
120 well of first conductivity type
131 buried layer of second conductivity type
132 well of first and second conductivity type
133 second conductivity type well
141 first conductive type doped region
142 second and first conductive type doped region
143 third doped region of the first conductivity type
144 doped regions of the first and second conductivity types
145 second conductive type doped region
151 first isolation structure
152 second isolation structure
153 third isolation Structure
154 fourth isolation Structure
155 fifth isolation structure
156 sixth isolation Structure
160 insulating layer
171 first interconnect structure
172 second interconnect structure
173 third interconnect structure
174 fourth interconnect structure
175 fifth interconnect structure
S1 first electrode
S2 second electrode
S3 third electrode
d1 first predetermined distance
d2 second predetermined distance
L133 effective length
E edge
S interface surface
Detailed Description
The following provides a detailed description of the device substrate, the semiconductor structure and the method for fabricating the semiconductor structure according to some embodiments of the present invention. It is to be understood that the following description provides many different embodiments, or examples, for implementing different aspects of embodiments of the invention. The specific elements and arrangements described below are merely illustrative of some embodiments of the invention for simplicity and clarity. These are, of course, merely examples and are not intended to be limiting. Moreover, repeated reference numerals or designations may be used in various embodiments. These iterations are merely provided for simplicity and clarity in describing some embodiments of the present invention and are not intended to represent any interrelationships between the various embodiments and/or structures discussed. Furthermore, when a first material layer is located on or above a second material layer, the first material layer and the second material layer are in direct contact. Alternatively, one or more layers of other materials may be present, in which case there may not be direct contact between the first and second layers of material.
Furthermore, relative terms, such as "lower" or "bottom" and "upper" or "top," may be used in embodiments to describe one element's relative relationship to another element of the drawings. It will be understood that if the device in the figures is turned over, elements described as being on the "lower" side would then be elements on the "upper" side if the device were turned over.
As used herein, the term "about", "about" or "substantially" generally means within 20%, preferably within 10%, and more preferably within 5%, or within 3%, or within 2%, or within 1%, or within 0.5% of a given value or range. The amounts given herein are approximate, that is, the meanings of "about", "about" and "about" may be implied without specifically stating "about", "about" or "about".
It will be understood that, although the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms, and these terms are only used to distinguish one element, component, region, layer and/or section from another element, component, region, layer and/or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of some embodiments of the present invention.
Unless defined otherwise, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and the present invention and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
Some embodiments of the invention can be understood with reference to the drawings, which are also to be considered part of the description of the embodiments of the invention. It is to be understood that the drawings of the embodiments of the present invention are not necessarily drawn to scale as actual devices or elements may be shown. The shape and thickness of the embodiments may be exaggerated in the drawings to clearly show the features of the embodiments of the present invention. In addition, the structures and devices in the drawings are shown schematically in order to clearly illustrate the features of the embodiments of the present invention.
In some embodiments of the invention, relative terms such as "lower," "upper," "horizontal," "vertical," "lower," "above," "top," "bottom," and the like are to be understood as referring to the segment and the orientation depicted in the associated drawings. These relative terms are for convenience of description only and do not imply that the described apparatus should be constructed or operated in a particular orientation. Terms concerning bonding, connecting, and the like, such as "connected," "interconnected," and the like, may refer to two structures as being in direct contact, or may also refer to two structures as not being in direct contact, unless otherwise specified, with another structure being interposed between the two structures. And the terms coupled and connected should also be construed to include both structures being movable or both structures being fixed.
FIG. 1 is a cross-sectional view of a semiconductor structure according to an embodiment of the invention. As shown in fig. 1, the semiconductor structure 100 includes a substrate 110, a first conductive type well 120, a second conductive type buried layer 131, a first second conductive type well 132, a second conductive type well 133, a first conductive type doped region 141, a second first conductive type doped region 142, a third first conductive type doped region 143, a first second conductive type doped region 144, and a second conductive type doped region 145.
The first conductive type well 120 is formed in the substrate 110 and has a first conductive type. According to an embodiment of the present invention, the substrate 110 is a silicon substrate. According to another embodiment of the present invention, the substrate 110 has a second conductivity type, wherein the first conductivity type is different from the second conductivity type. According to one embodiment of the present invention, the first conductivity type is N-type,
the second conductive type is P type. According to another embodiment of the present invention, the first conductivity type is P-type and the second conductivity type is N-type. According to other embodiments of the present invention, the substrate 110 may also be a lightly doped substrate, such as a lightly doped N-type substrate or a P-type substrate.
According to an embodiment of the present invention, the first conductive type well 120 may be formed by an ion implantation step. For example, when the first conductive type well 120 is N-type, phosphorus ions or arsenic ions may be implanted into a predetermined region where the first conductive type well 120 is to be formed to form the first conductive type well 120. However, when the first conductive type well 120 is P-type, boron ions or indium ions may be implanted into a predetermined region where the first conductive type well 120 is to be formed to form the first conductive type well 120. In some embodiments, the first conductivity type well 120 is a high voltage well.
The second-conductivity-type buried layer 131, the first-second-conductivity-type well 132, and the second-conductivity-type well 133 are formed in the first-conductivity-type well 120, wherein the second-conductivity-type buried layer 131, the first-second-conductivity-type well 132, and the second-conductivity-type well 133 have a second conductivity type. According to an embodiment of the present invention, the second-conductivity-type buried layer 131, the first-conductivity-type well 132, and the second-conductivity-type well 133 have the same conductivity type as the substrate 110.
According to an embodiment of the present invention, the second conductive type buried layer 131, the first conductive type well 132 and/or the second conductive type well 133 may also be formed by an ion implantation step. For example, when the second conductive type is N-type, phosphorus ions or arsenic ions may be implanted into a predetermined region where the second conductive type buried layer 131, the first conductive type well 132 and/or the second conductive type well 133 are to be formed to form the second conductive type buried layer 131, the first conductive type well 132 and/or the second conductive type well 133.
However, when the second conductive type is P-type, boron ions or indium ions may be implanted into the predetermined region where the second conductive type buried layer 131, the first conductive type well 132 and/or the second conductive type well 133 are to be formed to form the second conductive type buried layer 131, the first conductive type well 132 and/or the second conductive type well 133. According to an embodiment of the present invention, the doping concentration of the second-conductivity-type buried layer 131, the first-conductivity-type well 132, and/or the second-conductivity-type well 133 is higher than that of the substrate 110.
As shown in fig. 1, the substrate 110 and the first conductive type well 120 have an interface S, and the second conductive type buried layer 131 is spaced from the interface S by a first predetermined distance d 1. The first and second conductive type wells 132 are disposed in the first conductive type well 120 and on the second conductive type buried layer 131, and are connected to the second conductive type buried layer 131. The second-conductivity type well 133 is disposed in the first-conductivity type well 120 and above the second-conductivity type buried layer 131, and is spaced apart from the second-conductivity type buried layer 131 by a second predetermined distance d 2. According to an embodiment of the present invention, the first predetermined distance d1 is the same as the second predetermined distance d 2. According to another embodiment of the present invention, the first predetermined distance d1 is different from the second predetermined distance d 2.
The first doped region 141 of the first conductivity type is disposed in the well 120 of the first conductivity type and has the first conductivity type. As shown in fig. 1, the first conductive type doped region 141 is located between the first conductive type well 132 and the second conductive type well 133. According to an embodiment of the present invention, the doping concentration of the first conductive type doping region 141 is higher than the doping concentration of the first conductive type well 120.
The second doped region 142 of the first conductivity type is disposed in the well 120 of the first conductivity type and has the first conductivity type. As shown in fig. 1, the first conductive type doped region 141 and the second conductive type doped region 142 are respectively disposed on two sides of the second conductive type well 133. According to an embodiment of the present invention, the doping concentration of the second first conductive type doping region 142 is higher than the doping concentration of the first conductive type well 120.
The third doped region 143 of the first conductivity type is disposed in the well 120 of the first conductivity type and has the first conductivity type. As shown in fig. 1, the first conductive type doped region 141 and the third conductive type doped region 143 are respectively disposed on two sides of the first conductive type well 132. According to an embodiment of the present invention, the doping concentration of the third first conductive type doping region 143 is higher than the doping concentration of the first conductive type well 120.
The first and second conductive type doped region 144 is formed in the first and second conductive type well 132 and has a second conductive type. According to an embodiment of the present invention, the doping concentration of the first and second conductive type doping regions 144 is higher than the doping concentration of the first and second conductive type wells 132. The second conductive type doped region 145 is formed in the second conductive type well 133. According to an embodiment of the present invention, the doping concentration of the second conductive type doping region 145 is higher than the doping concentration of the second conductive type well 133.
According to an embodiment of the present invention, the semiconductor structure 100 further includes a first isolation structure 151, a second isolation structure 152, a third isolation structure 153, a fourth isolation structure 154, a fifth isolation structure 155, and a sixth isolation structure 156. The first isolation structure 151 contacts the third first conductive type doped region 143, but is not limited to the invention. According to other embodiments of the present invention, the first isolation structure 151 and the third first conductive type doping region 143 are spatially separated from each other.
As shown in fig. 1, the second isolation structure 152 directly contacts the third first conductive type doped region 143 and the first second conductive type doped region 144 to separate the third first conductive type doped region 143 and the first second conductive type doped region 144. According to other embodiments of the present invention, the second isolation structure 152 does not directly contact at least one of the third first conductive-type doped region 143 and the first second conductive-type doped region 144.
As shown in fig. 1, the third isolation structure 153 directly contacts the first and second conductive-type doped regions 141 and 144 to separate the first and second conductive-type doped regions 141 and 144. According to other embodiments of the present invention, the third isolation structure 153 does not directly contact at least one of the first and second conductive-type doped regions 141 and 144.
As shown in fig. 1, the fourth isolation structure 154 directly contacts the first and second conductive-type doped regions 141 and 145 to separate the first and second conductive-type doped regions 141 and 145. According to other embodiments of the present invention, the fourth isolation structure 154 does not directly contact at least one of the first and second impurity-doped regions 141 and 145.
As shown in fig. 1, the fifth isolation structure 155 directly contacts the second first conductive type doping region 142 and the second conductive type doping region 145 to separate the second first conductive type doping region 142 and the second conductive type doping region 145. According to other embodiments of the present invention, the fifth isolation structure 155 does not directly contact at least one of the second first conductive-type doped region 142 and the second conductive-type doped region 145.
As shown in fig. 1, the sixth isolation structure 156 contacts the second first conductive type doping region 142, but the invention is not limited thereto. According to other embodiments of the present invention, the sixth isolation structure 156 and the second first conductive type doping region 142 are spatially separated from each other.
According to other embodiments of the present invention, the semiconductor structure 100 further includes an insulating layer 160, a first interconnect structure 171, a second interconnect structure 172, a third interconnect structure 173, a fourth interconnect structure 174, and a fifth interconnect structure 175. According to an embodiment of the present invention, the first and second interconnection structures 171 and 172 respectively connect the first and second impurity-doped regions 144 and 145 to the first electrode S1, the third and fifth interconnection structures 173 and 175 respectively connect the first and third impurity-doped regions 141 and 143 to the second electrode S2, and the fourth interconnection structure 174 connects the second impurity-doped region 142 to the third electrode S3.
According to an embodiment of the present invention, when the first conductivity type is N-type and the second conductivity type is P-type, that is, when the first conductivity type well 120 is N-type and the first conductivity type well 132 and the second conductivity type well 133 are P-type, the semiconductor structure 100 is an N-type junction field effect transistor, wherein the first electrode S1 is a gate electrode, the second electrode S2 is a source electrode, the third electrode S3 is a drain electrode, and the effective channels of the N-type junction field effect transistor are respectively a first predetermined distance d1 and a second predetermined distance d 2.
According to another embodiment of the present invention, when the first conductivity type is P-type and the second conductivity type is N-type, that is, when the first conductivity type well 120 is P-type and the first conductivity type well 132 and the second conductivity type well 133 are N-type, the semiconductor structure 100 is a P-type junction field effect transistor, wherein the first electrode S1 is a gate terminal, the second electrode S2 is a drain terminal, the third electrode S3 is a source terminal, and the effective channels of the P-type junction field effect transistor are respectively a first predetermined distance d1 and a second predetermined distance d 2.
According to an embodiment of the present invention, the well 133 of the second conductivity type has an effective length L133. As shown in fig. 1, the second-conductivity-type buried layer 131 completely overlaps the effective length L133 of the second-conductivity-type well 133. In other words, the second-conductivity-type buried layer 131 is aligned with the edge E of the second-conductivity-type well 133.
Fig. 2 is a cross-sectional view of a semiconductor structure according to another embodiment of the invention. As shown in fig. 2, the second-conductivity-type buried layer 131 of the semiconductor structure 200 overlaps with half of the effective length L133 of the second-conductivity-type well 133. According to other embodiments of the present invention, the second-conductivity-type buried layer 131 overlaps at least half of the effective length L133 of the second-conductivity-type well 133.
FIG. 3 is a cross-sectional view of a semiconductor structure according to another embodiment of the present invention. As shown in fig. 3, the second-conductivity-type buried layer 131 of the semiconductor structure 300 exceeds the edge E of the second-conductivity-type well 133.
Fig. 4A to 4D are schematic views illustrating a method for fabricating a semiconductor structure according to an embodiment of the invention. As shown in fig. 4A, a substrate 110, such as a silicon substrate or other suitable semiconductor substrate, is provided. According to other embodiments of the present invention, the substrate 110 may also be a lightly doped substrate, such as a lightly doped P-type or N-type substrate. In the present embodiment, the substrate 110 has a second conductivity type.
Then, the first conductive well 120 may be formed in a predetermined region of the substrate 110 by a doping process (e.g., ion implantation) and thermal diffusion. According to an embodiment of the present invention, the first conductive type well 120 has a first conductive type, wherein the first conductive type is different from the second conductive type.
Then, a second conductive type buried layer 131, a first conductive type well 132 and a second conductive type well 133 may be formed in a predetermined region of the first conductive type well 120 by a doping process (e.g., ion implantation) and thermal diffusion processes, in sequence. According to an embodiment of the present invention, the second-conductivity-type buried layer 131, the first-second-conductivity-type well 132, and the second-conductivity-type well 133 have a second conductivity type. According to other embodiments of the present invention, the doping concentrations of the second-conductivity-type buried layer 131, the first-second-conductivity-type well 132, and the second-conductivity-type well 133 are higher than the doping concentration of the first-conductivity-type well 120.
According to an embodiment of the present invention, the first conductive type well 120 with the first predetermined distance d1 is formed, the second conductive type buried layer 131 is formed in the first conductive type well 120, the thickness of the first conductive type well 120 is increased on the second conductive type buried layer 131, and the first conductive type well 132 and the second conductive type well 133 are formed in the first conductive type well 120 respectively. As shown in fig. 4A, the second-conductivity type well 133 is spaced apart from the second-conductivity type buried layer 131 by a second predetermined distance d 2.
According to an embodiment of the present invention, the second-conductivity-type buried layer 131 completely overlaps the second-conductivity-type well 133. According to other embodiments of the present invention, the second-conductivity-type buried layer 131 overlaps at least half of the second-conductivity-type well 133 (as shown in fig. 2).
As shown in fig. 4B, a first isolation structure 151, a second isolation structure 152, a third isolation structure 153, a fourth isolation structure 154, a fifth isolation structure 155, and a sixth isolation structure 156 are formed on the substrate 110. The first isolation structure 151 and the sixth isolation structure 156 extend into the first conductive well 120; the second isolation structure 152 extends into the first conductive type well 120 and the first second conductive type well 132; the third isolation structure 153 extends into the first conductive type well 120 and the first second conductive type well 132; the fourth isolation structure 154 extends into the first conductive well 120 and the second conductive well 133; the fifth isolation structure 155 extends into the second conductive type well 133 and the first conductive type well 120.
According to an embodiment of the present invention, the first isolation structure 151, the second isolation structure 152, the third isolation structure 153 and the fourth isolation structure 154 are used to define a space for the first conductive type doped region 141, the second conductive type doped region 142, the third conductive type doped region 143, the first conductive type doped region 144 and the second conductive type doped region 145 to be formed.
As shown in fig. 4C, the first and second first and third first and second conductive type-doped regions 141, 142, 143, 144 and 145 may be formed by a doping process (e.g., ion implantation). According to an embodiment of the present invention, the first-conductivity-type-doped region 141 is formed in the first-conductivity-type well 120 and located between the third isolation structure 153 and the fourth isolation structure 154. The second doped region 142 of the first conductivity type is formed in the well 120 of the first conductivity type and located between the fifth isolation structure 155 and the sixth isolation structure 156.
The third doped region 143 of the first conductivity type is formed in the well 120 of the first conductivity type and located between the first isolation structure 151 and the second isolation structure 152. The first and second conductive type doped region 144 is located in the first and second conductive type well 132 and between the second isolation structure 152 and the third isolation structure 153. The second-conductivity-type doped region 145 is located in the second-conductivity-type well 133 and between the fourth isolation structure 154 and the fifth isolation structure 155.
As shown in fig. 4D, an insulating layer 160 is formed on the first isolation structure 151, the second isolation structure 152, the third isolation structure 153, the fourth isolation structure 154, the fifth isolation structure 155, the sixth isolation structure 156, the first doped region 141 of the first conductivity type, the second doped region 142 of the first conductivity type, the third doped region 143 of the first conductivity type, the first doped region 144 of the second conductivity type, and the second doped region 145 of the second conductivity type.
Next, a first interconnect structure 171, a second interconnect structure 172, a third interconnect structure 173, a fourth interconnect structure 174, and a fifth interconnect structure 175 may be formed on the insulating layer 160 by a metallization process. The first interconnection structure 171 connects the first and second conductive type doped regions 144 and 145 to the first electrode S1, the second interconnection structure 172 connects the second and second conductive type doped regions 145 and 145 to the first electrode S1, the third interconnection structure 173 connects the first and first conductive type doped regions 141 and 141 to the second electrode S2, the fourth interconnection structure 174 connects the second and first conductive type doped region 142 and 142 to the third electrode S3, and the fifth interconnection structure 175 and the third and first conductive type doped regions 143 are connected to the second electrode S2, respectively. In this way, the fabrication of the semiconductor structure 100 is completed.
According to an embodiment of the present invention, the semiconductor structure 100 is an N-junction field effect transistor. The first electrode S1 is a gate terminal, the second electrode S2 is a source terminal, the third electrode S3 is a drain terminal, and the effective channels of the N-junction field effect transistor are respectively a first predetermined distance d1 and a second predetermined distance d 2.
According to another embodiment of the present invention, the semiconductor structure 100 is a P-junction field effect transistor. The first electrode S1 is a gate terminal, the second electrode S2 is a drain terminal, the third electrode S3 is a source terminal, and the effective channels of the P-junction field effect transistor are respectively a first predetermined distance d1 and a second predetermined distance d 2.
The invention provides a semiconductor structure of junction field effect transistor and a manufacturing method thereof. Since the effective channel of the junction field effect transistor is divided into the first predetermined distance d1 and the second predetermined distance d2, the pinch-off voltage of the junction field effect transistor does not need to be increased when the on-state current is increased. Therefore, the semiconductor structure and the manufacturing method thereof provided by the invention effectively break the trade-off relationship between the on-current and the pinch-off voltage of the junction field effect transistor.
Although embodiments of the present invention and their advantages have been described above, it should be understood that various changes, substitutions and alterations can be made herein by those skilled in the art without departing from the spirit and scope of the invention. Moreover, the scope of the present application is not intended to be limited to the particular embodiments of the process, machine, manufacture, composition of matter, means, methods and steps described in the specification, but rather, the process, machine, manufacture, composition of matter, means, methods and steps described in connection with the embodiments disclosed herein will be understood to one skilled in the art to which the present application relates from the disclosure of the embodiments of the present application, and to any variations of the embodiments of the invention provided that the present application may be practiced with substantially the same function or achieve substantially the same result as the presently described embodiments. Accordingly, the scope of the present application includes the processes, machines, manufacture, compositions of matter, means, methods, and steps described in the specification. In addition, each claim constitutes a separate embodiment, and the scope of protection of the present invention also includes combinations of the respective claims and embodiments.
Claims (10)
1. A semiconductor structure, comprising:
a substrate;
a first conductive type trap arranged in the substrate;
a second conductive buried layer disposed in the first conductive well and spaced from the substrate by a first predetermined distance;
a first second conductive type well disposed in the first conductive type well and above the second conductive type buried layer, and connected to the second conductive type buried layer;
a doped region of a first and second conductivity type disposed in the well of the first and second conductivity type;
a second well of a second conductivity type disposed in the well of the first conductivity type and above the buried layer of the second conductivity type, and spaced from the buried layer of the second conductivity type by a second predetermined distance; and
and the second conductive type doped region is arranged in the second conductive type trap.
2. The semiconductor structure of claim 1, further comprising:
a doped region of a first conductivity type disposed in the well of the first conductivity type and between the well of the first conductivity type and the well of the second conductivity type;
a second doped region of the first conductivity type disposed in the well of the first conductivity type, wherein the first doped region of the first conductivity type and the second doped region of the first conductivity type are disposed on two sides of the well of the second conductivity type respectively; and
and a third doped region of the first conductivity type disposed in the well, wherein the first doped region of the first conductivity type and the third doped region of the first conductivity type are disposed on two sides of the well respectively.
3. The semiconductor structure of claim 2, wherein the first and second doped regions of the first and second conductivity types are connected to a first electrode, wherein the first and third doped regions of the first conductivity type are connected to a second electrode, and wherein the second doped region of the first conductivity type is connected to a third electrode.
4. The semiconductor structure of claim 3, wherein the semiconductor structure is a junction field effect transistor of a first conductivity type, wherein the first electrode is a gate terminal, the second electrode is a source terminal, and the third electrode is a drain terminal.
5. The semiconductor structure of claim 1, wherein the well of the second conductivity type has an effective length, wherein at least half of the effective length of the well of the second conductivity type overlaps the buried layer of the second conductivity type.
6. A method of fabricating a semiconductor structure, comprising:
providing a substrate;
forming a first conductive type well in the substrate;
forming a second conductive type buried layer in the first conductive type well, and at a first predetermined distance from the substrate;
forming a first second-conductivity-type well in the first-conductivity-type well and above the second-conductivity-type buried layer, wherein the first second-conductivity-type well is connected to the second-conductivity-type buried layer;
forming a second conductive type well in the first conductive type well and on the second conductive type buried layer, wherein the second conductive type well is spaced from the second conductive type buried layer by a second predetermined distance;
forming a first conductive type doped region in the first conductive type well; and
and forming a second conductive type doped region in the second conductive type well.
7. The method of manufacturing of claim 6, further comprising:
forming a first conductive type doped region in the first conductive type well and between the first conductive type well and the second conductive type well;
forming a second doped region of the first conductivity type in the well of the first conductivity type, wherein the first doped region of the first conductivity type and the second doped region of the first conductivity type are respectively located at two sides of the well of the second conductivity type; and
and forming a third doped region of the first conductivity type in the well of the first conductivity type, wherein the first doped region of the first conductivity type and the third doped region of the first conductivity type are respectively disposed at two sides of the well of the first conductivity type and the second conductivity type.
8. The method of manufacturing of claim 7, further comprising:
connecting the first and second conductive type doped regions to a first electrode;
connecting the first and third first-conductivity-type doped regions to a second electrode; and
connecting the second first conductive type doped region to a third electrode.
9. The method of claim 8, wherein the semiconductor structure is a junction field effect transistor of a first conductivity type, wherein the first electrode is a gate terminal, the second electrode is a source terminal, and the third electrode is a drain terminal.
10. The method of manufacturing of claim 6, wherein the second conductivity type well has an effective length, wherein at least half of the effective length of the second conductivity type well overlaps the second conductivity type buried layer.
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| CN104347683A (en) * | 2013-08-09 | 2015-02-11 | 美格纳半导体有限公司 | Semiconductor device |
| CN105185834A (en) * | 2015-10-19 | 2015-12-23 | 杭州士兰微电子股份有限公司 | Composite high voltage semiconductor device |
| CN105226101A (en) * | 2014-06-30 | 2016-01-06 | 无锡华润上华半导体有限公司 | Junction field effect transistor and manufacture method thereof |
| CN107516658A (en) * | 2016-06-16 | 2017-12-26 | 中芯国际集成电路制造(上海)有限公司 | A kind of semiconductor devices and its manufacture method and electronic installation |
| US9929283B1 (en) * | 2017-03-06 | 2018-03-27 | Vanguard International Semiconductor Corporation | Junction field effect transistor (JFET) with first and second top layer of opposite conductivity type for high driving current and low pinch-off voltage |
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| CN104347683A (en) * | 2013-08-09 | 2015-02-11 | 美格纳半导体有限公司 | Semiconductor device |
| CN105226101A (en) * | 2014-06-30 | 2016-01-06 | 无锡华润上华半导体有限公司 | Junction field effect transistor and manufacture method thereof |
| CN105185834A (en) * | 2015-10-19 | 2015-12-23 | 杭州士兰微电子股份有限公司 | Composite high voltage semiconductor device |
| CN107516658A (en) * | 2016-06-16 | 2017-12-26 | 中芯国际集成电路制造(上海)有限公司 | A kind of semiconductor devices and its manufacture method and electronic installation |
| US9929283B1 (en) * | 2017-03-06 | 2018-03-27 | Vanguard International Semiconductor Corporation | Junction field effect transistor (JFET) with first and second top layer of opposite conductivity type for high driving current and low pinch-off voltage |
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