CN111599818A - Three-dimensional memory and manufacturing method thereof - Google Patents
Three-dimensional memory and manufacturing method thereof Download PDFInfo
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- CN111599818A CN111599818A CN202010478356.1A CN202010478356A CN111599818A CN 111599818 A CN111599818 A CN 111599818A CN 202010478356 A CN202010478356 A CN 202010478356A CN 111599818 A CN111599818 A CN 111599818A
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- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
- H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
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- H—ELECTRICITY
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- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
- H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
- H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
Abstract
The invention provides a three-dimensional memory and a manufacturing method thereof. The manufacturing method comprises the following steps: s1, providing a first substrate with a gate stack structure on the surface, wherein the gate stack structure comprises gate structures and isolation layers which alternate along the direction far away from the first substrate, a channel through hole penetrating to the first substrate and a common source groove are formed in the gate stack structure, and a storage structure is arranged in the channel through hole; s2, filling amorphous silicon in the common source trench and performing spike annealing treatment to form a polycrystalline silicon shell layer by part of the amorphous silicon, wherein the polycrystalline silicon shell layer wraps the rest amorphous silicon; and S3, performing heat treatment on the structure processed in the step S2, forming a polycrystalline silicon core layer by the residual amorphous silicon, and forming a conductive channel by the polycrystalline silicon shell layer and the polycrystalline silicon core layer. The manufacturing method can relieve the increase of the stress of the substrate caused by the annealing process in the prior art, so that the substrate does not have warping degree, and the subsequent bonding with a CMOS circuit is facilitated.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a three-dimensional memory and a manufacturing method thereof.
Background
As the demand for integration and storage capacity continues to increase, 3D NAND memories have come into play. The 3D NAND memory greatly saves the area of a silicon chip, reduces the manufacturing cost and increases the storage capacity.
In the 3D NAND memory structure, a stacked 3D NAND memory structure is implemented by vertically stacking multiple layers of data storage units, however, other circuits such as a decoder (decoder), a page buffer (page buffer), a latch (latch), and the like are all formed by CMOS devices, and the processes of the CMOS devices cannot be integrated with the 3D NAND devices. In the current process, a 3D NAND memory array and peripheral circuits are formed by different processes, and then bonded together by a bonding technique.
However, the number of stacked layers of memory cells in the currently formed 3D NAND memory array increases, which increases the overall stress of the wafer having the memory array, and accordingly increases the warpage, and the wafer has a larger warpage, which increases the difficulty of bonding with peripheral circuits.
In order to solve the above technical problems, in the prior art, a stress film is usually deposited on the other surface of a wafer after a 3D NAND memory array is formed to adjust a wafer bow value, which may lead to a more complicated process and is not favorable for thinning and thinning of a device.
Disclosure of Invention
The invention mainly aims to provide a three-dimensional memory and a manufacturing method thereof, and aims to solve the problem that in the prior art, the bonding difficulty with a peripheral circuit is high due to the fact that the stress of a substrate with a memory array of the three-dimensional memory is high.
In order to achieve the above object, according to an aspect of the present invention, there is provided a method for fabricating a three-dimensional memory, including the steps of: s1, providing a first substrate with a gate stack structure on the surface, wherein the gate stack structure comprises gate structures and isolation layers, the gate structures and the isolation layers are alternately stacked along the direction far away from the first substrate, a channel through hole penetrating through the first substrate and a common source groove are formed in the gate stack structure, and a storage structure is arranged in the channel through hole; s2, filling amorphous silicon in the common source trench and performing spike annealing treatment to form a polycrystalline silicon shell layer by part of the amorphous silicon, wherein the polycrystalline silicon shell layer wraps the rest amorphous silicon; and S3, performing heat treatment on the structure processed in the step S2, forming a polycrystalline silicon core layer by the residual amorphous silicon, and forming a conductive channel by the polycrystalline silicon shell layer and the polycrystalline silicon core layer.
Further, the highest temperature of the peak annealing treatment is 950-1010 ℃.
Further, the spike annealing treatment has a first temperature rise stage and a first temperature drop stage, and the heat treatment has a second temperature rise stage, a constant temperature stage and a second temperature drop stage.
Further, the temperature increase rate in the first temperature increase stage is larger than the temperature increase rate in the second temperature increase stage.
Further, the temperature rise time of the first temperature rise stage is less than the temperature rise time of the second temperature rise stage.
Further, the cooling speed of the first cooling stage is greater than that of the second cooling stage.
Further, the step of filling amorphous silicon in the common source trench includes: back etching the grid structure to form a back etching channel communicated with the common source electrode groove; filling an insulating material in the back etching channel and the common source groove, and etching the insulating material in the common source groove to form an etching channel; amorphous silicon is filled in the etching channel.
Further, after step S3, a first substrate having a memory array is obtained, and the manufacturing method further includes the following steps: and S4, providing a second substrate with the CMOS circuit, and bonding the gate stack structure with the CMOS circuit.
Further, before the step of bonding the first substrate to the second substrate, the step S4 further includes: a tensile film is formed on a side of the first substrate away from the memory array.
Further, the thickness of the tension film is 1000-5000A.
Further, the material forming the tension film is SO2And/or SiN.
According to another aspect of the present invention, there is provided a three-dimensional memory including a first substrate having a memory array, the memory array including a gate stack structure including gate structures and spacers, the gate structures and the spacers being alternately stacked in a direction away from the first substrate, the gate stack structure having a plurality of channel vias and common source trenches formed therein penetrating to the first substrate, the memory array further including: a memory structure located in each trench via; the polycrystalline silicon core layer is positioned in the common source groove; and the polycrystalline silicon shell layer is positioned in the common source groove and wraps the polycrystalline silicon core layer, and the hardness of the polycrystalline silicon shell layer is greater than that of the polycrystalline silicon core layer.
Further, the three-dimensional memory further includes: the back etching channel is positioned between the isolation layers and is connected with the grid structure; the etch-back channel is filled with amorphous silicon.
Further, the three-dimensional memory further includes: a second substrate having a CMOS circuit; and the bonding part is used for connecting the memory structure and the CMOS circuit.
Further, the three-dimensional memory further comprises a tension film, and the tension film is positioned on the side, away from the memory array, of the first substrate.
Further, the thickness of the tension film is 1000-5000A.
Further, the material forming the tension film is SO2And/or SiN.
After a storage structure is formed in a grid stacking structure on a first substrate, a common source groove penetrating through the first substrate is formed in the grid stacking structure, a sacrificial layer is replaced by a grid structure, amorphous silicon is filled in the common source groove and subjected to spike annealing treatment to form a polycrystalline silicon shell layer by part of the amorphous silicon, the polycrystalline silicon shell layer wraps the rest amorphous silicon, and the spike annealing is directly cooled after rapid temperature rise, so that the surface layer part of the amorphous silicon becomes polycrystalline silicon, and only amorphous silicon in the surface layer part forms polycrystalline silicon, therefore, the shrinkage rate is small in the process of forming the polycrystalline silicon shell layer, the hardness is high, and then the rest amorphous silicon is subjected to heat treatment, the polycrystalline silicon shell layer can be used as a supporting layer in the heat treatment process, so that the influence of the thermal shrinkage of amorphous silicon on the substrate is relieved, the stress increase of the substrate caused by an annealing process in the prior art is relieved, the substrate cannot have warping degree, and the subsequent bonding with a CMOS circuit is facilitated.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification, illustrate exemplary embodiments of the invention and together with the description serve to explain the invention and not to limit the invention. In the drawings:
fig. 1 is a schematic diagram illustrating a cross-sectional structure of a substrate after a first substrate having a gate stack structure on a surface thereof is provided and in a common source trench of the gate stack structure in a method for fabricating a three-dimensional memory according to an embodiment of the present disclosure;
FIG. 2 is a schematic diagram showing a cross-sectional structure of a substrate after filling amorphous silicon in the common source trench shown in FIG. 1;
FIG. 3 is a schematic cross-sectional view of another substrate after filling amorphous silicon in the common source trench shown in FIG. 1;
FIG. 4 is a schematic cross-sectional view of the substrate after spike annealing the amorphous silicon of FIG. 3 to form a polysilicon crust;
FIG. 5 is a schematic cross-sectional view of the substrate after heat treating the structure of FIG. 4 to form a polysilicon core from the remaining amorphous silicon;
fig. 6 is a schematic diagram illustrating a partial cross-sectional structure of a three-dimensional memory provided in an embodiment of the present application.
Wherein the figures include the following reference numerals:
10. a first substrate; 20. a gate structure; 30. an isolation layer; 40. a storage structure; 410. a charge blocking layer; 420. a charge trapping layer; 430. a tunneling layer; 440. a channel layer; 50. a common source trench; 60. an insulating material; 70. amorphous silicon; 80. a polycrystalline silicon shell layer; 90. a polysilicon core layer.
Detailed Description
It should be noted that the embodiments and features of the embodiments may be combined with each other without conflict. The present invention will be described in detail below with reference to the embodiments with reference to the attached drawings.
In order to make the technical solutions of the present invention better understood, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
It should be noted that the terms "first," "second," and the like in the description and claims of the present invention and in the drawings described above are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged under appropriate circumstances in order to facilitate the description of the embodiments of the invention herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed, but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
As described in the background, the number of stacked layers of memory cells in the 3D NAND memory array in the prior art increases the overall stress of the wafer having the memory array, which results in a corresponding increase in warpage, and the wafer has a larger warpage, which results in an increased difficulty in bonding with peripheral circuits.
The inventor of the present invention has studied the above problem and proposed a method for manufacturing a three-dimensional memory, as shown in fig. 1 to 4, comprising the steps of: s1, providing a first substrate 10 having a gate stack structure on a surface thereof, where the gate stack structure includes gate structures 20 and isolation layers 30, the gate structures 20 and the isolation layers 30 are alternately stacked in a direction away from the first substrate 10, the gate stack structure has a channel via penetrating through the first substrate 10 and a common source trench 50, and the channel via is provided with a storage structure 40; s2, filling amorphous silicon 70 in the common source trench 50 and performing spike annealing treatment to form a polysilicon shell 80 on a part of the amorphous silicon 70, and wrapping the remaining amorphous silicon 70 with the polysilicon shell 80; s3, performing heat treatment on the structure processed in the step S2, and forming a polycrystalline silicon core layer 90 by the residual amorphous silicon 70, wherein the polycrystalline silicon shell layer 80 and the polycrystalline silicon core layer 90 form a conductive channel.
In the manufacturing method, the spike annealing is directly cooled after being rapidly heated, so that the surface layer part of the amorphous silicon becomes the polycrystalline silicon, and only the amorphous silicon of the surface layer part forms the polycrystalline silicon, so that the shrinkage rate is small in the process of forming the polycrystalline silicon shell layer, the hardness is high, the rest amorphous silicon is subjected to heat treatment to form the polycrystalline silicon core layer, the polycrystalline silicon shell layer can be used as a supporting layer in the heat treatment process, the influence of the thermal shrinkage of the amorphous silicon on the substrate is relieved, the stress increase of the substrate caused by the annealing process in the prior art is relieved, the substrate cannot have warping degree, and the subsequent bonding with a CMOS circuit is facilitated.
An exemplary embodiment of a method of fabricating a three-dimensional memory provided according to the present invention will be described in more detail below. These exemplary embodiments may, however, be embodied in many different forms and should not be construed as limited to only the embodiments set forth herein. It should be understood that these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of these exemplary embodiments to those skilled in the art.
First, step S1 is executed: providing a first substrate 10 with a gate stack structure on the surface, wherein the gate stack structure comprises gate structures 20 and isolation layers 30, the gate structures 20 and the isolation layers 30 are alternately stacked in a direction away from the first substrate 10, the gate stack structure has a channel through hole penetrating to the first substrate 10 and a common source trench 50, and the channel through hole is provided with a storage structure 40, as shown in fig. 1.
The material of the substrate may be single crystal silicon (Si), single crystal germanium (Ge), or silicon germanium (GeSi), silicon carbide (SiC); or silicon-on-insulator (SOI), germanium-on-insulator (GOI); or may be other materials such as group iii-v compounds such as gallium arsenide.
In a preferred embodiment, the step of forming the gate stack structure includes: forming a stacked structure of sacrificial layers and isolation layers 30 on a substrate, the sacrificial layers and the isolation layers 30 being alternately stacked in a direction away from the substrate; forming a channel via in the stacked structure of the sacrificial layer and the isolation layer 30, and forming a memory structure 40 in the channel via, the memory structure 40 may include sequentially forming a charge blocking layer 410, a charge trapping layer 420, a tunneling layer 430, and a channel layer 440, which are stacked, on sidewalls of the channel via, as shown in fig. 1; and forming a common source groove 50 penetrating through the substrate in the stacked structure, performing wet etching on the sacrificial layer by using etching liquid to remove the sacrificial layer, forming a gate structure 20 at the position where the sacrificial layer is removed so as to enable the gate structure 20 to be in contact with the storage structure 40, and completing replacement of the sacrificial layer and the gate structure 20 by forming the gate structure 20, so as to form a gate stacked structure with the gate structure 20 and the isolation layer 30 alternating.
In the preferred embodiment, the isolation layer 30 and the sacrificial layer can be formed by a conventional deposition process in the prior art, such as a chemical vapor deposition process. Those skilled in the art can set the number of the sacrificial layer and the isolation layer 30 reasonably according to actual requirements, and those skilled in the art can also select the type of the isolation layer 30 and the sacrificial layer reasonably according to the prior art, such as the isolation layer 30 can be SiO2The sacrificial layer may be SiN.
In the above preferred embodiment, the material of each functional layer in the memory structure 40 can be reasonably selected by one skilled in the art according to the prior art, for example, the material of the charge blocking layer 410 can be SiO2The charge trapping layer 420 may be SiN and the tunneling layer 430 may be SiO2The material of the channel layer 440 may be polysilicon. Moreover, the above-mentioned memory structure 40 can be formed by a deposition process that is conventional in the art, and will not be described herein.
In the preferred embodiment, the common source trench 50 is formed to enable the sacrificial layer to have an exposed end surface, so that the sacrificial layer can be wet-etched by using an etching solution from the exposed end surface to remove the sacrificial layer; moreover, by removing the sacrificial layer, a channel extending in the lateral direction can be formed at the position where the sacrificial layer is removed, and the gate material is deposited by using the channel as a deposition channel to obtain the gate structure 20, where the deposition process may be Atomic Layer Deposition (ALD); the material forming the gate structure 20 is typically a metal, and may be selected from one or more of W, Al, Cu, Ti, Ag, Au, Pt, and Ni.
The gate structure 20 includes a gate layer, and a high-K dielectric layer may be formed on the surface of the channel before the gate layer is formed. The K dielectric layer and the gate layer together form a gate structure 20. The material for forming the high-K dielectric layer can be selected from HfO2、TiO2、HfZrO、HfSiNO、Ta2O5、ZrO2、ZrSiO2、Al2O3、SrTiO3And one or more of BaSrTiO.
After providing the first substrate 10 having the gate stack structure on the surface, step S2 is performed: the common-source trench 50 is filled with amorphous silicon 70 and subjected to spike annealing to form a polysilicon shell 80 from a portion of the amorphous silicon 70, and the polysilicon shell 80 wraps the remaining amorphous silicon 70, as shown in fig. 2 to 4.
In one embodiment, the step of filling the amorphous silicon 70 in the common-source trench 50 includes: filling an insulating material 60 in the common source trench 50 and etching to form an etched channel penetrating to the first substrate; the etched channels are filled with amorphous silicon 70 as shown in fig. 2.
In another embodiment, the step of filling the amorphous silicon 70 in the common-source trench 50 includes: etching back the gate structure 20 to form an etching back channel communicated with the common source trench 50, filling the etching back channel and the common source trench 50 with an insulating material 60, and etching the insulating material 60 in the common source trench 50 to form an etched channel; the etched channels are filled with amorphous silicon 70 as shown in fig. 3.
In the step S2, after the common-source trench 50 is filled with the amorphous silicon 70, the spike annealing process is performed to quickly raise the temperature from room temperature to a predetermined temperature, then the temperature is directly lowered without a residence time, and the temperature is quickly lowered to room temperature, the spike annealing process enables the amorphous silicon 70 to be thermally crystallized from the surface layer, and the time of the spike annealing process is very short, so that the amorphous silicon 70 on the surface layer can be crystallized to form the polysilicon shell 80 to wrap the remaining amorphous silicon 70, as shown in fig. 4.
In order to ensure that the formed polysilicon shell layer 80 has enough hardness to relieve the thermal shrinkage of the inner amorphous silicon caused by the subsequent heat treatment, the maximum temperature of the spike annealing treatment is preferably 950-1010 ℃. In order to ensure the rapid temperature rise and rapid temperature fall of the spike annealing treatment, the annealing time is usually very short, and can be 500-1000 mus.
After obtaining the polysilicon shell layer 80, step S3 is executed: the structure processed in step S2 is subjected to a heat treatment, the remaining amorphous silicon 70 forms a polysilicon core layer 90, and the polysilicon shell layer 80 and the polysilicon core layer 90 form a conductive channel, as shown in fig. 5.
In the step S3, by heat-treating the remaining amorphous silicon 70 to form the polysilicon core layer 90, the polysilicon core layer and the polysilicon shell 80 together form a conductive channel located in the common-source trench 50, and due to the existence of the polysilicon shell 80, the thermal contraction of the amorphous silicon 70 subjected to the heat treatment subsequently does not affect the deformation of the common-source trench 50, and thus the warpage of the first substrate 10 having the common-source trench 50 is not affected.
The technicians in the field can adopt the conventional annealing treatment in the prior art, the temperature is kept constant after the temperature is raised to the preset temperature, the temperature is kept for a period of time and then is reduced, in order to ensure the complete crystallization of the residual amorphous silicon, the highest temperature of the heat treatment can be 650-900 ℃, and the heat preservation time can be 10-60 min.
In a preferred embodiment, the spike annealing treatment has a first temperature rise stage and a first temperature drop stage, the heat treatment has a second temperature rise stage, a constant temperature stage and a second temperature drop stage, and the temperature rise speed of the first temperature rise stage is greater than that of the second temperature rise stage; the temperature rise time of the first temperature rise stage is less than that of the second temperature rise stage; the cooling speed of the first cooling stage is greater than that of the second cooling stage.
After forming the conductive channel in the common-source trench 50, obtaining the first substrate 10 with the memory array, the above-mentioned manufacturing method of the present invention may further include the following steps: and S4, providing a second substrate with a CMOS circuit, and bonding the gate stack structure of the first substrate 10 with the CMOS circuit. In the process of forming the conductive channel, spike annealing treatment is performed first to crystallize the amorphous silicon 70 on the surface layer to form the polycrystalline silicon shell 80, so that when the remaining amorphous silicon 70 is subjected to subsequent heat treatment, the polycrystalline silicon shell 80 can relieve the warpage of the first substrate 10 caused by the thermal shrinkage of the amorphous silicon 70 inside, and the implementation of the bonding process is facilitated.
In a preferred embodiment, before the step of bonding the first substrate 10 to the second substrate, the step S4 further includes: a tensile film is formed on the first substrate 10 on the side away from the memory array. In the prior art, in order to alleviate the warpage of the first substrate 10 having the memory array, before the bonding process, a tensile film is usually deposited on the other side of the first substrate 10 where the memory array is not formed, and in order to alleviate the warpage of the first substrate 10, the tensile film is usually required to have a larger thickness, but the manufacturing method provided by the present invention can alleviate the warpage of the first substrate 10 through the spike annealing process, SO that the first substrate 10 having the memory array and the second substrate having the CMOS circuit can be better bonded only by forming the thinner tensile film, even without forming the tensile film, at this time, the thickness of the tensile film may be 1000 to 5000A, and the material forming the tensile film may be SO2And/or SiN.
According to another aspect of the present invention, there is also provided a three-dimensional memory, as shown in fig. 6, including a first substrate 10 having a memory array, the memory array including a gate stack structure, the gate stack structure including a gate structure 20 and spacers 30, the gate structure 20 and the spacers 30 being alternately stacked in a direction away from the first substrate 10, a channel via penetrating to the first substrate 10 and a common source trench 50 being formed in the gate stack structure, the memory array further including a storage structure 40, a polysilicon core layer 90 and a polysilicon shell layer 80, the storage structure 40 being located in the channel via; the polysilicon core layer 90 is located in the common source trench 50; the polysilicon shell layer 80 is located in the common source trench 50 and wraps the polysilicon core layer 90, and the hardness of the polysilicon shell layer 80 is greater than that of the polysilicon core layer 90.
In the three-dimensional memory, because the common source trench 50 is provided with the polysilicon shell layer 80 and the polysilicon core layer 90 at the same time, the polysilicon shell layer 80 wraps the polysilicon core layer 90, and the hardness of the polysilicon shell layer 80 is greater than that of the polysilicon core layer 90, the polysilicon shell layer 80 can be used as a support layer, thereby relieving the influence of the thermal contraction of the amorphous silicon 70 on the substrate, ensuring the influence of an annealing process in the device preparation process on the stress of the substrate, preventing the substrate from warping, and facilitating the subsequent bonding with a CMOS circuit.
In the above three-dimensional memory of the present invention, the memory structure 40 may include a charge blocking layer 410, a charge trapping layer 420, a tunneling layer 430 and a channel layer 440 sequentially stacked on the sidewall of the trench via, as shown in fig. 6, and a person skilled in the art can reasonably select the materials of the functional layers in the memory structure 40 according to the prior art, for example, the material of the charge blocking layer 410 may be SiO, and the material of the functional layers may be SiO2The charge trapping layer 420 may be SiN and the tunneling layer 430 may be SiO2The material of the channel layer 440 may be polysilicon.
The above three-dimensional memory of the present invention may further include a second substrate having CMOS circuitry and a bonding portion connecting the memory array with the CMOS circuitry. In order to further alleviate the warpage of the first substrate 10 with the memory array, the three-dimensional memory may further include a tensile film on a side of the first substrate 10 away from the memory array.
The polycrystalline silicon shell layer 80 in the three-dimensional memory provided by the invention can relieveWarping of the first substrate 10 can ensure better bonding between the first substrate 10 with the memory array and the second substrate with the CMOS circuit by forming a thin tensile film, wherein the thickness of the tensile film may be 1000 to 5000A, and the material forming the tensile film may be SO2And/or SiN.
From the above description, it can be seen that the above-described embodiments of the present invention achieve the following technical effects:
according to the manufacturing method provided by the invention, spike annealing treatment is firstly carried out, and the polycrystalline silicon shell layer formed by the amorphous silicon on the surface layer can be used as a supporting layer, so that the influence of thermal shrinkage of the amorphous silicon on the substrate is relieved, further, the stress increase of the substrate caused by an annealing process in the prior art is relieved, the substrate cannot have warping degree, and the subsequent bonding with a CMOS circuit is facilitated.
The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (17)
1. A method for manufacturing a three-dimensional memory is characterized by comprising the following steps:
s1, providing a first substrate with a gate stack structure on the surface, wherein the gate stack structure comprises gate structures and isolation layers, the gate structures and the isolation layers are alternately stacked and arranged along the direction far away from the first substrate, a channel through hole penetrating to the first substrate and a common source groove are formed in the gate stack structure, and a storage structure is arranged in the channel through hole;
s2, filling amorphous silicon in the common source trench and carrying out spike annealing treatment to enable part of the amorphous silicon to form a polycrystalline silicon shell layer, wherein the polycrystalline silicon shell layer wraps the rest amorphous silicon;
and S3, performing heat treatment on the structure processed in the step S2, wherein the residual amorphous silicon forms a polycrystalline silicon core layer, and the polycrystalline silicon shell layer and the polycrystalline silicon core layer form a conductive channel.
2. The method of claim 1, wherein the peak annealing process has a maximum temperature of 950 to 1010 ℃.
3. The method of claim 1, wherein the spike anneal process has a first ramp-up phase and a first ramp-down phase, and the thermal process has a second ramp-up phase, a constant temperature phase, and a second ramp-down phase.
4. The method according to claim 3, wherein a temperature rise rate in the first temperature rise stage is larger than a temperature rise rate in the second temperature rise stage.
5. The method according to claim 3, wherein a temperature rise time of the first temperature rise stage is shorter than a temperature rise time of the second temperature rise stage.
6. The method of manufacturing according to claim 3, wherein a cooling rate of the first cooling stage is greater than a cooling rate of the second cooling stage.
7. The method according to any one of claims 1 to 6, wherein the step of filling amorphous silicon in the common source trench comprises:
etching back the gate structure to form an etching back channel communicated with the common source trench;
filling an insulating material in the back etching channel and the common source trench, and etching the insulating material in the common source trench to form an etching channel;
and filling the amorphous silicon in the etching channel.
8. The method of manufacturing according to any one of claims 1 to 6, wherein after the step S3, the first substrate having a memory array is obtained, the method further comprising the steps of:
and S4, providing a second substrate with a CMOS circuit, and bonding the gate stack structure with the CMOS circuit.
9. The method of manufacturing according to claim 8, wherein, before the step of bonding the first substrate to the second substrate, the step S4 further includes:
a tensile film is formed on a side of the first substrate away from the memory array.
10. The method according to claim 9, wherein the tensile film has a thickness of 1000 to 5000A.
11. The method of manufacturing according to claim 9, wherein a material forming the tension film is SO2And/or SiN.
12. A three-dimensional memory comprising a first substrate having a memory array, the memory array comprising a gate stack structure including gate structures and spacers stacked alternately in a direction away from the first substrate, the gate stack structure having a plurality of channel vias and common source trenches formed therein through to the first substrate, the memory array further comprising:
a memory structure located in each of the trench vias;
the polycrystalline silicon core layer is positioned in the common source groove;
and the polycrystalline silicon shell layer is positioned in the common source groove and wraps the polycrystalline silicon core layer, and the hardness of the polycrystalline silicon shell layer is greater than that of the polycrystalline silicon core layer.
13. The three-dimensional memory according to claim 13, further comprising:
the back etching channel is positioned between the isolation layers and is connected with the grid structure;
the etch-back channel is filled with amorphous silicon.
14. The three-dimensional memory according to claim 12, further comprising:
a second substrate having CMOS circuitry;
and the bonding part is used for connecting the memory structure and the CMOS circuit.
15. The three-dimensional memory according to claim 14, further comprising a tensile film on a side of the first substrate away from the memory array.
16. The three-dimensional memory according to claim 15, wherein the tensile film has a thickness of 1000 to 5000A.
17. The three-dimensional memory according to claim 15, wherein a material forming the tensile film is SO2And/or SiN.
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| CN107731833B (en) * | 2017-08-31 | 2018-12-14 | 长江存储科技有限责任公司 | A kind of array common source interstitital texture and preparation method thereof |
| CN110620040B (en) * | 2019-09-12 | 2022-04-22 | 长江存储科技有限责任公司 | Method for improving process stability in production |
| CN110828469B (en) * | 2019-10-23 | 2023-07-21 | 长江存储科技有限责任公司 | 3D memory device and method of manufacturing the same |
| CN111162087A (en) * | 2020-01-02 | 2020-05-15 | 长江存储科技有限责任公司 | 3D memory device and manufacturing method thereof |
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2020
- 2020-05-29 CN CN202010478356.1A patent/CN111599818B/en active Active
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN112234066A (en) * | 2020-10-15 | 2021-01-15 | 长江存储科技有限责任公司 | Three-dimensional memory and manufacturing method thereof |
| CN113793854A (en) * | 2021-09-14 | 2021-12-14 | 长江存储科技有限责任公司 | Three-dimensional memory and manufacturing method thereof |
| CN113793854B (en) * | 2021-09-14 | 2023-08-08 | 长江存储科技有限责任公司 | Three-dimensional memory and manufacturing method thereof |
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