CN111597096A - Benchmark test method, system and terminal equipment - Google Patents
Benchmark test method, system and terminal equipment Download PDFInfo
- Publication number
- CN111597096A CN111597096A CN202010274544.2A CN202010274544A CN111597096A CN 111597096 A CN111597096 A CN 111597096A CN 202010274544 A CN202010274544 A CN 202010274544A CN 111597096 A CN111597096 A CN 111597096A
- Authority
- CN
- China
- Prior art keywords
- data
- graph
- data storage
- model data
- model
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/30—Monitoring
- G06F11/34—Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation ; Recording or statistical evaluation of user activity, e.g. usability assessment
- G06F11/3409—Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation ; Recording or statistical evaluation of user activity, e.g. usability assessment for performance assessment
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Landscapes
- Engineering & Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Computer Hardware Design (AREA)
- Quality & Reliability (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Debugging And Monitoring (AREA)
- Test And Diagnosis Of Digital Computers (AREA)
Abstract
The application is applicable to the field of computer testing and provides a benchmark testing method, a benchmark testing system and terminal equipment, wherein the method comprises the following steps: obtaining model data; performing bit reduction processing on the model data, wherein after the bit reduction processing is performed, the data bit number of parameters in the model data is reduced; generating a data storage graph according to the model data after the bit reduction processing, wherein the data storage graph comprises a plurality of nodes and a plurality of edges used for representing the connection relations among the nodes; and traversing the data storage graph to obtain the number of edges completing data access in unit time. The scheme improves the graph traversal speed and improves the detection accuracy of the data throughput in the detected terminal equipment.
Description
Technical Field
The present application belongs to the field of computer testing technologies, and in particular, to a benchmark testing method, system, and terminal device.
Background
The hardware equipped in the terminal device usually has an ideal operation performance, but the hardware is usually affected by various factors in the actual operation process and cannot reach the ideal operation state. Therefore, before practical application, performance testing is usually performed on the terminal device to obtain the actual operating performance condition of the terminal device in advance.
At present, the Graph500 benchmark test method can be adopted to perform performance test on the terminal equipment. The Graph500 benchmark test method specifically utilizes Graph theory to measure the data processing capacity of terminal equipment (especially a super computer) in the process of actually simulating complex problems. In a specific execution process of benchmark test software adopted by the Graph500 benchmark test method, a Graph needs to be generated as a data reading object in a performance test process, after the Graph is generated, Graph traversal operation is performed on the generated Graph, the number of edges (TEPS) in the Graph traversed per second is used as a measurement standard of data processing capacity of the terminal equipment, and the higher the TEPS value obtained through the test is, the faster the Graph traversal speed is indicated, and the higher the data processing capacity of the terminal equipment is indicated.
However, since the benchmark test is intended to measure the actual operating performance of the hardware of the terminal device, if the traversal speed of the graph in the benchmark test execution process is lower than the actual operating performance of the hardware of the terminal device, the actual operating performance of the terminal device to be tested cannot be accurately tested.
Disclosure of Invention
The embodiment of the application provides a benchmark testing method, a benchmark testing system and terminal equipment, and can solve the problem that the actual operation performance of the tested terminal equipment cannot be accurately tested due to the fact that the graph traversal speed in the benchmark testing execution process is low in the prior art.
A first aspect of an embodiment of the present application provides a benchmark testing method, which is applied to a terminal device, and includes:
obtaining model data;
performing bit reduction processing on the model data, wherein after the bit reduction processing is performed, the data bit number of parameters in the model data is reduced;
generating a data storage graph according to the model data after the bit reduction processing, wherein the data storage graph comprises a plurality of nodes and a plurality of edges used for representing the connection relations among the nodes;
and traversing the data storage graph to obtain the number of edges completing data access in unit time.
A second aspect of an embodiment of the present application provides a benchmark test system, including:
the acquisition module is used for acquiring model data;
the data processing module is used for carrying out bit reduction processing on the model data, and after the bit reduction processing is carried out, the data bit number of parameters in the model data is reduced;
the generation module is used for generating a data storage graph according to the model data after the bit reduction processing, wherein the data storage graph comprises a plurality of nodes and a plurality of edges used for representing the connection relations among the nodes;
and the graph traversal module is used for performing graph traversal on the data storage graph to obtain the number of edges completing data access in unit time.
A third aspect of embodiments of the present application provides a terminal device, which includes a memory, a processor, and a computer program stored in the memory and executable on the processor, and the processor implements the steps of the method according to the first aspect when executing the computer program.
A fourth aspect of embodiments of the present application provides a computer-readable storage medium, in which a computer program is stored, which, when executed by a processor, performs the steps of the method according to the first aspect.
A fifth aspect of the present application provides a computer program product, which, when run on a terminal device, causes the terminal device to perform the steps of the method of the first aspect described above.
As can be seen from the above, in the embodiment of the present application, the obtained model data is subjected to the bit reduction processing, the data storage map is generated according to the model data subjected to the bit reduction processing, and the map traversal is performed on the data storage map, so that the number of edges completing the data access in unit time is obtained, and the benchmark test on the actual operation performance in the terminal device is completed. In the process, the number of data bits of the parameters contained in the model data is reduced through the bit reduction processing of the model data, and further the number of data bits of data represented by each node and edge in the generated data storage graph is also reduced. Therefore, when the graph is traversed, the graph data reading amount in unit time is increased, the number of traversed edges per second can be increased, the graph traversing speed is increased, and the detection accuracy of the actual operation performance of the tested terminal equipment is improved.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the embodiments or the prior art descriptions will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without inventive exercise.
FIG. 1 is a first flowchart of a benchmark testing method provided by an embodiment of the present application;
FIG. 2 is an exemplary diagram of a two-dimensional adjacency matrix corresponding to a data storage map provided by an embodiment of the application;
FIG. 3 is a flowchart of a benchmark testing method according to an embodiment of the present application;
FIG. 4 is a block diagram of a benchmark test system provided by an embodiment of the present application;
fig. 5 is a structural diagram of a terminal device according to an embodiment of the present application.
Detailed Description
In the following description, for purposes of explanation and not limitation, specific details are set forth, such as particular system structures, techniques, etc. in order to provide a thorough understanding of the embodiments of the present application. It will be apparent, however, to one skilled in the art that the present application may be practiced in other embodiments that depart from these specific details. In other instances, detailed descriptions of well-known systems, devices, circuits, and methods are omitted so as not to obscure the description of the present application with unnecessary detail.
It will be understood that the terms "comprises" and/or "comprising," when used in this specification and the appended claims, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
It is also to be understood that the terminology used in the description of the present application herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used in the specification of the present application and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.
It should be further understood that the term "and/or" as used in this specification and the appended claims refers to and includes any and all possible combinations of one or more of the associated listed items.
As used in this specification and the appended claims, the term "if" may be interpreted contextually as "when", "upon" or "in response to a determination" or "in response to a detection". Similarly, the phrase "if it is determined" or "if a [ described condition or event ] is detected" may be interpreted contextually to mean "upon determining" or "in response to determining" or "upon detecting [ described condition or event ]" or "in response to detecting [ described condition or event ]".
It should be understood that, the sequence numbers of the steps in this embodiment do not mean the execution sequence, and the execution sequence of each process should be determined by the function and the inherent logic of the process, and should not constitute any limitation to the implementation process of the embodiment of the present application.
In order to explain the technical solution described in the present application, the following description will be given by way of specific examples.
Referring to fig. 1, fig. 1 is a first flowchart of a benchmark testing method provided in an embodiment of the present application. As shown in fig. 1, a benchmark testing method is applied to a terminal device, which may be a super computer, a server cluster, or other devices capable of implementing data processing. The method comprises the following steps:
Wherein the model data is used to generate a data storage map. More specifically, the model data may randomly generate a data storage map based on input map scale parameters. The graph scale parameter here is, for example, the number of vertices and the number of edges of the graph.
The model data corresponds to a graph generation model used for establishing a data storage graph, namely the model data is code data corresponding to the graph generation model. For example, in the benchmark test software corresponding to Graph500, the Graph generation model may be specifically a multiple recursion generator.
And 102, performing bit reduction processing on the model data, wherein after the bit reduction processing is performed, the number of data bits of the parameters in the model data is reduced.
The bit reduction processing is a processing operation for shortening the number of data bits. The pair of model data is subjected to a bit reduction process for parameters included in the data model. Typically, the model data includes variable parameters and constant parameters.
Alternatively, when performing the bit reduction processing on the model data, only the target data in the model data may be subjected to the bit reduction processing, for example, the variable parameter included in the model data is subjected to the bit reduction processing as the target data. The variable parameter is, for example, a node variable parameter used for representing node data in the data storage map, an edge variable parameter used for representing edge data in the data storage map, or another variable parameter used for generating the data storage map.
As a specific implementation manner, the performing the bit reduction processing on the model data includes: and compressing the model data according to the data type of the model data.
For example, the data type may be a character type, a floating point type, an integer type, and the like.
The terminal device can perform different compression processing on parameters of different data types in the model data. For example, the data type of the node variable parameter in the model data is int64 (that is, the data occupies 64-bit integer), and the node variable parameter occupies 64 bits when expressed, and the node variable parameter may be subjected to bit reduction processing based on the data type of the node variable parameter, and the number of occupied data bits of the node variable parameter after bit reduction may be specifically adjusted to 32 bits. So that the data bit number of the node variable parameter is shortened from 64 bits to 32 bits.
More specifically, when the model data is compressed according to the data type of the model data, the bit reduction processing may be performed on the bit occupation length of the data type of the parameter (specifically, the variable parameter) in the model data, so that the data bit number of the parameter corresponding to different data types in the model data is reduced accordingly. For other data types, the bit reduction processing is carried out in the same way. In specific implementation, specific setting may be performed according to actual data compression requirements, and the present application is not limited thereto.
It should be noted that by performing the bit reduction processing on the model data, the data amount in the data storage graph can be reduced without changing the data items (e.g., the edge variable parameters and the node variable parameters) included in the model data and ensuring that the graph size of the data storage graph is unchanged.
And 103, generating a data storage map according to the model data subjected to the bit reduction processing.
The data storage graph includes a plurality of nodes and a plurality of edges representing connection relationships between the plurality of nodes.
Here, the data storage map is a data storage structure, and particularly, a data storage structure that stores data in the form of edges and nodes.
The generation process of the data storage graph can be based on the set node number and the edge number, respectively generate random numbers (namely node data) for representing each node and random numbers (namely edge data) for representing the connection relation (namely edges) between each node through model data, and construct the data storage graph by forming a two-dimensional adjacent matrix by the random numbers.
As shown in fig. 2, each node in the plurality of nodes of the data storage map is represented by a node data (which may be a random number), and each node data is different. For example, the four nodes are represented in FIG. 2 by V0, V1, V2 and V3. Each of the plurality of sides is also represented by one side data. Here, each side data is the same, for example, the side data is 1. When the edge data is 1, indicating that a connection relation exists between the two nodes, namely an edge exists between the two nodes; when no edge exists between two nodes, the edge data is not corresponding, and 0 is used for replacing the edge data. For example, in fig. 2, the edge data between V0 and V1, V2 and V3 is 1, indicating that there are edges between V0 and V1, V2 and V3, respectively; the edge data between V1 and V0 and V2 is 1, indicating that there is an edge between V1 and V0 and V2, respectively; the edge data between V1 and V3 is 0, indicating that no edge exists between V1 and V3; and (4) analogizing by the method if the connection relation of the edges exists between other nodes in the graph.
In this step, since the data bit number of the parameter in the model data after the bit reduction processing is reduced, the data bit numbers of the edge data corresponding to different edges and the node data corresponding to different nodes in the data storage map generated according to the model data after the bit reduction processing are reduced accordingly.
Specifically, for example: the data storage graph to be generated comprises 4 nodes, and the node data corresponding to the 4 nodes is integer data 0, 1, 2 and 3. Taking the second node data 1 as an example, when the model data is not subjected to the bit reduction processing, the data type of the node variable parameter corresponding to the node data in the model data is int64, for example, if a data storage diagram is generated based on the model data which is not subjected to the bit reduction processing, the second node data 1 is stored as 0000000000000000000000000000000000000000000000000000000000000001; when the model data is subjected to bit reduction processing, the data type of the node variable parameter in the model data is adjusted from int64 to int32 (namely, the data occupies 32-bit integer), so that the data bit number of the node variable parameter limited by the data type is reduced from 64 bits to 32 bits. In the process, the data type is not changed, and the bit length of the data parameter defined by the data type is reduced, so when the data storage map is generated by the model data after the bit reduction processing, the second node data 1 is specifically stored as 00000000000000000000000000000001, and the bit number is reduced from 64 bits to 32 bits, so that the data amount contained in the generated data storage map is reduced, and less storage space is occupied.
Similarly, the process of reducing the bits of other parameters in the model data is performed in the same way.
The process realizes that the data quantity of the edge data and the node data corresponding to a plurality of edges and a plurality of nodes in the graph is reduced on the premise of not losing the number of the edges and the number of the nodes of the graph and not changing the size of the graph, so that the data quantity contained in the data storage graph under the same graph scale is changed.
And 104, performing graph traversal on the data storage graph to obtain the number of edges completing data access in unit time.
The graph traversal is a process of traversing a plurality of nodes and a plurality of edges included in the data storage graph, that is, sequentially accessing each node data and each edge data.
The number of edges for completing data access specifically refers to the number of edges for completing data access to the edge corresponding to the edge.
The graph traversal can be realized by using a Breadth-First Search (BFS) algorithm.
During the traversal of the graph, a processor in the terminal device needs to perform data access reading on the generated data storage graph. In the data storage diagram generated according to the model data after the bit reduction processing, the data amount of the node data and the edge data corresponding to the nodes and the edges is reduced, so that in the process of reading the generated data storage diagram according to the cache row data to realize diagram traversal, a processor arranges more node data and edge data corresponding to the nodes and the edges in one cache row, so that the density of the nodes and the edges arranged in the cache row is improved, the number of the nodes and the edges passing through the cache row when being read is increased, the data scanning speed of the processor when executing the diagram traversal algorithm is accelerated, and the detection accuracy of the actual operation performance of the tested terminal equipment is improved.
When the graph traversal is performed on the data storage graph, the number of edges completing the data access in unit time needs to be recorded at the same time, and the number of edges completing the data access in unit time is the graph traversal speed. The number of edges completing data access in unit time can be further output, so that related testers can obtain the detected actual operation performance of the terminal equipment based on the number of edges completing data access in unit time, and obtain a performance improvement effect brought by software optimization in the terminal equipment.
In the embodiment of the application, the obtained model data is subjected to bit reduction, a data storage graph is generated according to the model data subjected to the bit reduction, graph traversal is performed on the data storage graph, and the number of edges completing data access within unit time is output, so that the benchmark test on the actual operation performance in the terminal equipment is completed. In the process, the data bit number of parameters contained in the model data is reduced through the bit reduction processing of the model data, so that the data bit number of node data and edge data in the generated data storage graph is also reduced, the data volume contained in the graph is compressed on the premise of the same graph scale (namely the number of nodes and edges in the graph is not changed), the data arrangement density of the graph data in a cache line in the graph traversing process is increased on the premise of not losing the number of edges and the number of nodes of the graph, the graph data reading amount in unit time is increased, the number of edges traversed per second in the graph traversing process is increased, the graph traversing speed is increased, the detection accuracy of the actual operation performance of the tested terminal equipment is improved, and meanwhile, the performance improvement effect of software optimization in the terminal equipment is obtained.
The embodiment of the application also provides different implementation modes of the benchmark test method.
Referring to fig. 3, fig. 3 is a second flowchart of a benchmark testing method provided in the embodiment of the present application. As shown in fig. 3, a benchmark testing method includes the steps of:
The implementation process of this step is the same as that of step 101 in the foregoing embodiment, and is not described here again.
And 302, performing bit reduction processing on the model data, wherein after the bit reduction processing is performed, the number of data bits of the parameters in the model data is reduced.
The implementation process of this step is the same as that of step 102 in the foregoing embodiment, and is not described here again.
Wherein the scale parameter is used to indicate the number of the plurality of nodes and the plurality of edges.
Specifically, the scale parameters include, for example:
number of vertices N, N ═ 2SCALE；
The number of edges M, M ═ edgefactor × N.
Wherein, the number of the top points of the graph is a logarithm taking 2 as a base number; the SCALE represents the SCALE range of the graph and can be assigned according to actual needs; the edgefactor is an edge factor, is the ratio of the number of edges to the number of vertices, and can be assigned according to actual needs.
And 304, if the scale parameter meets a preset value taking condition, generating the data storage map according to the scale parameter and the model data after the bit reduction processing.
The data storage graph includes a plurality of nodes and a plurality of edges representing connection relationships between the plurality of nodes.
Specifically, after the scale parameter of the data storage map is obtained, the scale parameter needs to be subjected to value determination, and when the scale parameter meets the size of the storage space which can be provided in the current terminal device, the parameter value is considered to meet a value condition, and the data storage map can be generated based on the scale parameter and the model parameter after the bit reduction processing.
As an optional implementation manner, the generating the data storage map according to the scale parameter and the model data after the bit reduction processing includes:
determining a graph generation model according to the model data subjected to the bit reduction processing; inputting the scale parameters into the graph generation model for processing to obtain random numbers corresponding to the plurality of edges and the plurality of nodes respectively; and generating the data storage map according to the random number, wherein the data storage map is a kronecker map.
The Kronecker plot is a plot generated using a non-standard matrix operation Kronecker product. In the specific process of generating the data storage graph, Kronecker product operation is performed on two matrixes formed by all nodes (elements contained in the matrixes are random numbers representing the nodes), so that a Kronecker graph is obtained, and each element in the Kronecker graph is assigned to be a random number corresponding to an edge connecting two corresponding nodes.
Referring to fig. 2, each node of the plurality of nodes of the data storage graph is represented by a node data (which may be a random number), and each node data is different, and the nodes are represented by V0, V1, V2, and V3. Each of the plurality of sides is also represented by one side data. Here, each side data is the same, for example, the side data is 1. As shown in fig. 2, when the edge data is 1, it indicates that there is a connection relationship between two nodes, that is, there is an edge between two nodes; when no edge exists between two nodes, the edge data is not corresponding, and 0 is used for replacing the edge data.
Here, the random number corresponding to the edge is edge data; the random number corresponding to the node is the node data.
In the generation process of the data storage graph, random numbers used for representing nodes and random numbers used for representing connection relations (namely edges) between the nodes are respectively generated based on the set node number and edge number, and the construction of the data storage graph is realized based on the random numbers.
And 305, if the scale parameter does not meet the value taking condition, updating the scale parameter so that the updated scale parameter meets the value taking condition, and generating the data storage map according to the updated scale parameter and the model data after the bit reduction processing.
Specifically, after the scale parameter of the data storage map is obtained, the scale parameter needs to be subjected to value determination, and when the scale parameter does not conform to the size of the storage space which can be provided in the current terminal device, the scale parameter is considered not to conform to the value taking condition, and at this time, the scale parameter needs to be adjusted, and the adjusted scale parameter needs to satisfy the value taking condition.
Correspondingly, generating the data storage map according to the updated scale parameter and the model data after the bit reduction processing comprises the following steps:
determining a graph generation model according to the model data subjected to the bit reduction processing; inputting the updated scale parameters into the graph generation model for processing to obtain random numbers corresponding to the plurality of edges and the plurality of nodes respectively; and generating the data storage map according to the random number, wherein the data storage map is a kronecker map.
The process is the same as the process of generating the data storage map according to the scale parameter and the model data after the bit reduction process, and is not described again here.
And step 306, performing graph traversal on the data storage graph to obtain the number of edges completing data access in unit time.
The implementation process of this step is the same as that of step 104 in the foregoing embodiment, and is not described here again.
In the embodiment of the application, the obtained model data is subjected to bit reduction, a data storage graph is generated according to the model data subjected to the bit reduction, graph traversal is performed on the data storage graph, and the number of edges completing data access within unit time is output, so that the benchmark test on the actual operation performance in the terminal equipment is completed. In the process, the data bit number of parameters contained in the model data is reduced through the bit reduction processing of the model data, so that the data bit number of node data and edge data in the generated data storage graph is also reduced, the data volume contained in the graph is compressed on the premise of the same graph scale (namely the number of nodes and edges in the graph is not changed), the data arrangement density of the graph data in a cache line in the graph traversing process is increased on the premise of not losing the number of edges and the number of nodes of the graph, the graph data reading amount in unit time is increased, the number of edges traversed per second in the graph traversing process is increased, the graph traversing speed is increased, the detection accuracy of the actual operation performance of the tested terminal equipment is improved, and meanwhile, the performance improvement effect of software optimization in the terminal equipment is obtained.
Referring to fig. 4, fig. 4 is a structural diagram of a benchmark testing system provided in an embodiment of the present application, and for convenience of description, only a part related to the embodiment of the present application is shown.
The benchmark test system 400 includes:
an obtaining module 401, configured to obtain model data;
a data processing module 402, configured to perform bit reduction processing on the model data, where after the bit reduction processing, the number of data bits of a parameter in the model data is reduced;
a generating module 403, configured to generate a data storage graph according to the model data after the bit reduction processing, where the data storage graph includes a plurality of nodes and a plurality of edges used for representing connection relationships between the nodes;
and a graph traversal module 404, configured to perform graph traversal on the data storage graph to obtain the number of edges completing data access in unit time.
Wherein the data processing module 402 is specifically configured to: and compressing the model data according to the data type of the model data.
Wherein, this test system still includes:
a parameter obtaining module, configured to obtain a scale parameter of the data storage map, where the scale parameter is used to indicate the number of the plurality of nodes and the plurality of edges;
if the scale parameter meets a preset value condition, the generating module 403 includes: and the first generation submodule is used for generating the data storage diagram according to the scale parameter and the model data after the bit reduction processing.
Wherein the first generation submodule is specifically configured to:
determining a graph generation model according to the model data subjected to the bit reduction processing; inputting the scale parameters into the graph generation model for processing to obtain random numbers corresponding to the plurality of edges and the plurality of nodes respectively; and generating the data storage map according to the random number, wherein the data storage map is a kronecker map.
Wherein, this testing arrangement still includes:
the updating module is used for updating the scale parameter if the scale parameter does not meet the value taking condition so as to enable the updated scale parameter to meet the value taking condition; (ii) a
Accordingly, the generating module 403 includes: and the second generation submodule is used for generating the data storage diagram according to the updated scale parameter and the model data after the bit reduction processing.
Wherein the second generation submodule is specifically configured to:
determining a graph generation model according to the model data subjected to the bit reduction processing;
inputting the updated scale parameters into the graph generation model for processing to obtain random numbers corresponding to the plurality of edges and the plurality of nodes respectively;
and generating the data storage map according to the random number, wherein the data storage map is a kronecker map.
The benchmark testing system provided by the embodiment of the application can realize each process of the embodiment of the benchmark testing method, can achieve the same technical effect, and is not repeated here for avoiding repetition.
Fig. 5 is a structural diagram of a terminal device according to an embodiment of the present application. As shown in the figure, the terminal device 5 of the embodiment includes: at least one processor 50 (only one shown in fig. 5), a memory 51, and a computer program 52 stored in the memory 51 and executable on the at least one processor 50, the steps of any of the various method embodiments described above being implemented when the computer program 52 is executed by the processor 50.
The terminal device 5 may be a desktop computer, a notebook, a palm computer, a cloud server, or other computing devices. The terminal device 5 may include, but is not limited to, a processor 50 and a memory 51. Those skilled in the art will appreciate that fig. 5 is merely an example of a terminal device 5 and does not constitute a limitation of terminal device 5 and may include more or fewer components than shown, or some components may be combined, or different components, e.g., the terminal device may also include input-output devices, network access devices, buses, etc.
The Processor 50 may be a Central Processing Unit (CPU), other general purpose Processor, a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), an off-the-shelf Programmable Gate Array (FPGA) or other Programmable logic device, discrete Gate or transistor logic, discrete hardware components, etc. A general purpose processor may be a microprocessor or the processor may be any conventional processor or the like.
The memory 51 may be an internal storage unit of the terminal device 5, such as a hard disk or a memory of the terminal device 5. The memory 51 may also be an external storage device of the terminal device 5, such as a plug-in hard disk, a Smart Media Card (SMC), a Secure Digital (SD) Card, a Flash memory Card (Flash Card), and the like, which are provided on the terminal device 5. Further, the memory 51 may also include both an internal storage unit and an external storage device of the terminal device 5. The memory 51 is used for storing the computer program and other programs and data required by the terminal device. The memory 51 may also be used to temporarily store data that has been output or is to be output.
It will be apparent to those skilled in the art that, for convenience and brevity of description, only the above-mentioned division of the functional units and modules is illustrated, and in practical applications, the above-mentioned function distribution may be performed by different functional units and modules according to needs, that is, the internal structure of the apparatus is divided into different functional units or modules to perform all or part of the above-mentioned functions. Each functional unit and module in the embodiments may be integrated in one processing unit, or each unit may exist alone physically, or two or more units are integrated in one unit, and the integrated unit may be implemented in a form of hardware, or in a form of software functional unit. In addition, specific names of the functional units and modules are only for convenience of distinguishing from each other, and are not used for limiting the protection scope of the present application. The specific working processes of the units and modules in the system may refer to the corresponding processes in the foregoing method embodiments, and are not described herein again.
In the above embodiments, the descriptions of the respective embodiments have respective emphasis, and reference may be made to the related descriptions of other embodiments for parts that are not described or illustrated in a certain embodiment.
Those of ordinary skill in the art will appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware or combinations of computer software and electronic hardware. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the implementation. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present application.
In the embodiments provided in the present application, it should be understood that the disclosed system/terminal device and method may be implemented in other ways. For example, the above-described system/terminal device embodiments are merely illustrative, and for example, the division of the modules or units is only one logical division, and there may be other divisions when actually implemented, for example, multiple units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices or units, and may be in an electrical, mechanical or other form.
The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.
In addition, functional units in the embodiments of the present application may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit. The integrated unit can be realized in a form of hardware, and can also be realized in a form of a software functional unit.
The integrated modules/units, if implemented in the form of software functional units and sold or used as separate products, may be stored in a computer readable storage medium. Based on such understanding, all or part of the flow in the method of the embodiments described above can be realized by a computer program, which can be stored in a computer-readable storage medium and can realize the steps of the embodiments of the methods described above when the computer program is executed by a processor. Wherein the computer program comprises computer program code, which may be in the form of source code, object code, an executable file or some intermediate form, etc. The computer-readable medium may include: any entity or device capable of carrying the computer program code, recording medium, usb disk, removable hard disk, magnetic disk, optical disk, computer Memory, Read-Only Memory (ROM), Random Access Memory (RAM), electrical carrier wave signals, telecommunications signals, software distribution medium, and the like. It should be noted that the computer readable medium may contain content that is subject to appropriate increase or decrease as required by legislation and patent practice in jurisdictions, for example, in some jurisdictions, computer readable media does not include electrical carrier signals and telecommunications signals as is required by legislation and patent practice.
The present application realizes all or part of the processes in the method of the above embodiments, and may also be implemented by a computer program product, when the computer program product runs on a terminal device, the steps in the above method embodiments may be implemented when the terminal device executes the computer program product.
The above-mentioned embodiments are only used for illustrating the technical solutions of the present application, and not for limiting the same; although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications and substitutions do not substantially depart from the spirit and scope of the embodiments of the present application and are intended to be included within the scope of the present application.
Claims (10)
1. A benchmark test method is applied to terminal equipment and is characterized by comprising the following steps:
obtaining model data;
performing bit reduction processing on the model data, wherein after the bit reduction processing is performed, the data bit number of parameters in the model data is reduced;
generating a data storage graph according to the model data after the bit reduction processing, wherein the data storage graph comprises a plurality of nodes and a plurality of edges used for representing the connection relations among the nodes;
and traversing the data storage graph to obtain the number of edges completing data access in unit time.
2. The benchmarking method of claim 1, wherein the subjecting the model data to bit reduction processing comprises:
and compressing the model data according to the data type of the model data.
3. The benchmarking method of claim 1, wherein prior to generating the data storage map from the reduced model data, the benchmarking method further comprises:
obtaining a scale parameter of the data storage graph, wherein the scale parameter is used for indicating the number of the plurality of nodes and the plurality of edges;
if the scale parameter meets a preset value taking condition, generating a data storage diagram according to the model data after the bit reduction processing, including:
and generating the data storage diagram according to the scale parameter and the model data after the bit reduction processing.
4. The benchmarking method of claim 3, wherein the generating the data storage map from the scale parameters and the model data after the downscaling process comprises:
determining a graph generation model according to the model data subjected to the bit reduction processing;
inputting the scale parameters into the graph generation model for processing to obtain random numbers corresponding to the plurality of edges and the plurality of nodes respectively;
and generating the data storage map according to the random number, wherein the data storage map is a kronecker map.
5. The benchmarking method of claim 3, wherein after the obtaining the scale parameters of the data storage map, the benchmarking method further comprises:
if the scale parameter does not meet the value taking condition, updating the scale parameter so that the updated scale parameter meets the value taking condition;
correspondingly, the generating a data storage map according to the model data after the bit reduction processing includes:
and generating the data storage diagram according to the updated scale parameters and the model data subjected to the bit reduction processing.
6. The benchmarking method of claim 5, wherein the generating the data storage map based on the updated scale parameters and the model data after the downscaling process comprises:
determining a graph generation model according to the model data subjected to the bit reduction processing;
inputting the updated scale parameters into the graph generation model for processing to obtain random numbers corresponding to the plurality of edges and the plurality of nodes respectively;
and generating the data storage map according to the random number, wherein the data storage map is a kronecker map.
7. A benchmarking system, comprising:
the acquisition module is used for acquiring model data;
the data processing module is used for carrying out bit reduction processing on the model data, and after the bit reduction processing is carried out, the data bit number of parameters in the model data is reduced;
the generation module is used for generating a data storage graph according to the model data after the bit reduction processing, wherein the data storage graph comprises a plurality of nodes and a plurality of edges used for representing the connection relations among the nodes;
and the graph traversal module is used for performing graph traversal on the data storage graph to obtain the number of edges completing data access in unit time.
8. The benchmarking system of claim 7, wherein the data processing module is specifically configured to:
and compressing the model data according to the data type of the model data.
9. A terminal device comprising a memory, a processor and a computer program stored in the memory and executable on the processor, characterized in that the processor implements the steps of the method according to any of claims 1 to 6 when executing the computer program.
10. A computer-readable storage medium, in which a computer program is stored which, when being executed by a processor, carries out the steps of the method according to any one of claims 1 to 6.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010274544.2A CN111597096B (en) | 2020-04-09 | 2020-04-09 | Benchmark test method, system and terminal equipment |
| PCT/CN2020/139578 WO2021203741A1 (en) | 2020-04-09 | 2020-12-25 | Benchmark test method and system, and terminal device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010274544.2A CN111597096B (en) | 2020-04-09 | 2020-04-09 | Benchmark test method, system and terminal equipment |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN111597096A true CN111597096A (en) | 2020-08-28 |
| CN111597096B CN111597096B (en) | 2023-06-06 |
Family
ID=72190585
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202010274544.2A Active CN111597096B (en) | 2020-04-09 | 2020-04-09 | Benchmark test method, system and terminal equipment |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN111597096B (en) |
| WO (1) | WO2021203741A1 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2021203741A1 (en) * | 2020-04-09 | 2021-10-14 | 中国科学院深圳先进技术研究院 | Benchmark test method and system, and terminal device |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20120278261A1 (en) * | 2011-04-28 | 2012-11-01 | International Business Machines Corporation | Determining the importance of data items and their characteristics using centrality measures |
| CN104572786A (en) * | 2013-10-29 | 2015-04-29 | 华为技术有限公司 | Visualized optimization processing method and device for random forest classification model |
| CN107423330A (en) * | 2017-04-15 | 2017-12-01 | 上海地阳实业有限公司 | Flow game making method and device |
| CN108830779A (en) * | 2017-11-13 | 2018-11-16 | 哈尔滨安天科技股份有限公司 | Processing method, device, electronic equipment and the storage medium of three-dimensional modeling data |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US11604829B2 (en) * | 2016-11-01 | 2023-03-14 | Wisconsin Alumni Research Foundation | High-speed graph processor for graph searching and simultaneous frontier determination |
| CN109254909B (en) * | 2018-08-06 | 2021-11-23 | 四川蜀天梦图数据科技有限公司 | Method and system for generating large graph for test |
| CN109726314B (en) * | 2019-01-03 | 2020-09-01 | 中国人民解放军国防科技大学 | Bitmap-based sparse matrix compression storage method |
| CN109740023B (en) * | 2019-01-03 | 2020-09-29 | 中国人民解放军国防科技大学 | Sparse matrix compression storage method based on bidirectional bitmap |
| CN111597096B (en) * | 2020-04-09 | 2023-06-06 | 中国科学院深圳先进技术研究院 | Benchmark test method, system and terminal equipment |
-
2020
- 2020-04-09 CN CN202010274544.2A patent/CN111597096B/en active Active
- 2020-12-25 WO PCT/CN2020/139578 patent/WO2021203741A1/en active Application Filing
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20120278261A1 (en) * | 2011-04-28 | 2012-11-01 | International Business Machines Corporation | Determining the importance of data items and their characteristics using centrality measures |
| CN104572786A (en) * | 2013-10-29 | 2015-04-29 | 华为技术有限公司 | Visualized optimization processing method and device for random forest classification model |
| CN107423330A (en) * | 2017-04-15 | 2017-12-01 | 上海地阳实业有限公司 | Flow game making method and device |
| CN108830779A (en) * | 2017-11-13 | 2018-11-16 | 哈尔滨安天科技股份有限公司 | Processing method, device, electronic equipment and the storage medium of three-dimensional modeling data |
Non-Patent Citations (2)
| Title |
|---|
| 熊文 等: "大数据基准测试程序包构建方法研究", pages 1 - 9 * |
| 谢先招;韩华;章鹏;王海军;: "基于两轮最小生成树的股票网络模型构建", 计算机应用与软件, no. 11 * |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2021203741A1 (en) * | 2020-04-09 | 2021-10-14 | 中国科学院深圳先进技术研究院 | Benchmark test method and system, and terminal device |
Also Published As
| Publication number | Publication date |
|---|---|
| CN111597096B (en) | 2023-06-06 |
| WO2021203741A1 (en) | 2021-10-14 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US9317965B2 (en) | Uniform point cloud decimation | |
| CN110554958A (en) | Graph database testing method, system, device and storage medium | |
| CN114764768A (en) | Defect detection and classification method and device, electronic equipment and storage medium | |
| CN108415668B (en) | Chip excitation method, device, system, computer equipment and storage medium | |
| CN111491169B (en) | Digital image compression method, device, equipment and medium | |
| CN111475402B (en) | Program function testing method and related device | |
| CN114997407A (en) | Noise elimination method and device for quantum measurement equipment, electronic equipment and medium | |
| CN115841046A (en) | Accelerated degradation test data processing method and device based on wiener process | |
| CN111597096A (en) | Benchmark test method, system and terminal equipment | |
| CN114819168B (en) | Quantum comparison method and device for matrix eigenvalues | |
| CN111221827B (en) | Database table connection method and device based on graphic processor, computer equipment and storage medium | |
| US10819368B2 (en) | Method for compressing and restoring time series data | |
| Sánchez et al. | Bidimensional median filter for parallel computing architectures | |
| CN114282480B (en) | De-embedding method, device, equipment and medium based on two-port network | |
| CN115861665A (en) | Method, device, equipment and medium for matching candidate frame in target detection network training | |
| CN113609648B (en) | Dynamic load-based electric energy error metering method and device and electronic equipment | |
| CN109522565A (en) | A kind of verification method, device and computer readable storage medium | |
| CN114384541A (en) | Point cloud target detection method, terminal device and computer readable storage medium | |
| CN113376564A (en) | Smart electric meter metering correction method and device based on data analysis and terminal | |
| CN117710513B (en) | Quantum convolution neural network-based magnetic resonance imaging method and device | |
| CN117706255B (en) | Coaxial cable testing method, device and system | |
| CN112817821B (en) | Data processing method, device, equipment and storage medium | |
| CN114637474B (en) | Data block processing method and device and electronic equipment | |
| CN109344369B (en) | Certificate making method based on original value verification and terminal equipment | |
| CN117333416A (en) | Flaw detection method, electronic device, and storage medium |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |