WO2021203741A1

WO2021203741A1 - Benchmark test method and system, and terminal device

Info

Publication number: WO2021203741A1
Application number: PCT/CN2020/139578
Authority: WO
Inventors: 刘树珍; 孟金涛; 魏彦杰; 冯圣中
Original assignee: 中国科学院深圳先进技术研究院
Priority date: 2020-04-09
Filing date: 2020-12-25
Publication date: 2021-10-14
Also published as: CN111597096A; CN111597096B

Abstract

The present application is applicable to the field of computer test, and provides a benchmark test method and system, and a terminal device. Said method comprises: acquiring model data; performing bit reduction processing on the model data, the number of data bits of parameters in the model data subjected to bit reduction processing being reduced; generating a data storage graph according to the model data subjected to bit reduction processing, the data storage graph comprising a plurality of nodes and a plurality of edges used for representing connection relationships between the plurality of nodes; and traversing the data storage graph to obtain the number of edges for which data access is completed in a unit time. According to the solution, the graph traversal speed is increased, and the detection accuracy for the data throughput of a tested terminal device is increased.

Description

Benchmark test method, system and terminal equipment

Technical field

This application belongs to the technical field of computer testing, and in particular relates to a benchmark testing method, system and terminal equipment.

Background technique

The hardware equipped in the terminal equipment usually has the operating performance under the ideal state, but the hardware is usually affected by various factors in the actual operation process and cannot reach the ideal operating state. Therefore, it is usually necessary to perform a performance test on the terminal device before actual application, so as to know the actual operating performance status of the terminal device in advance.

Currently, Graph500 can be used to test the performance of terminal equipment. The Graph500 benchmark test method specifically uses graph theory to measure the data processing capabilities of terminal devices (especially supercomputers) when actually simulating complex problems. In the specific execution process of the benchmark test software used in the Graph500 benchmark test method, it is necessary to first generate a graph as the data reading object in the performance test process. After the graph is generated, the graph traversal operation is performed on the generated graph, and the traversal is performed every second The number of edges in the graph (TEPS, traversed edges per second) is used as a measure of the data processing capability of the terminal device. The larger the TEPS value obtained in the test, the faster the graph traversal speed, and the greater the data processing capability of the terminal device. high.

However, because the purpose of the benchmark test is to measure the actual operating performance of the terminal device's hardware, if the traversal speed of the graph during the execution of the benchmark test is lower than the actual operating performance of the terminal device's hardware, it will result in the inability to accurately test the terminal under test. The actual operating performance of the equipment.

Summary of the invention

The embodiments of the present application provide a benchmark test method, system, and terminal device, which can solve the problem that the traversal speed of the graph during the execution of the benchmark test in the prior art is low, resulting in the inability to accurately test the actual operating performance of the terminal device under test. .

The first aspect of the embodiments of the present application provides a benchmark test method, which is applied to a terminal device, and includes:

Obtain model data;

Perform a downgrade process on the model data, and after the downgrade process, the number of data bits of the parameters in the model data is reduced;

Generating a data storage graph according to the model data after the downgrading process, the data storage graph including a plurality of nodes and a plurality of edges for representing the connection relationship between the plurality of nodes;

Graph traversal is performed on the data storage graph to obtain the number of edges that complete data access in a unit time.

The second aspect of the embodiments of the present application provides a benchmark test system, including:

The acquisition module is used to acquire model data;

The data processing module is used to perform a downgrade processing on the model data, and after the downgrade processing, the number of data bits of the parameters in the model data is reduced;

A generating module, configured to generate a data storage graph according to the model data after the downgrading process, the data storage graph including a plurality of nodes and a plurality of edges for representing the connection relationship between the plurality of nodes;

The graph traversal module is used to perform graph traversal on the data storage graph to obtain the number of edges that complete data access in a unit time.

The third aspect of the embodiments of the present application provides a terminal device, including a memory, a processor, and a computer program stored in the memory and running on the processor. When the processor executes the computer program, The steps of the method as described in the first aspect are implemented.

The fourth aspect of the embodiments of the present application provides a computer-readable storage medium, the computer-readable storage medium stores a computer program, and the computer program implements the steps of the method described in the first aspect when the computer program is executed by a processor.

The fifth aspect of the present application provides a computer program product, which when the computer program product runs on a terminal device, causes the terminal device to execute the steps of the method described in the first aspect.

It can be seen from the above that, in the embodiment of the present application, the acquired model data is degraded, a data storage graph is generated based on the degraded model data, and the data storage graph is traversed to obtain the completion of data access in a unit time. The number of edges to complete the benchmark test of the actual operating performance of the terminal device. In this process, the number of data bits of the parameters contained in the model data is reduced through the reduction of the model data, which in turn reduces the number of data bits of the data represented by each node and edge in the generated data storage graph. Therefore, when graph traversal is performed, the amount of graph data read per unit time can be increased, the number of edges traversed per second can be increased, the graph traversal speed can be increased, and the detection accuracy of the actual operating performance of the tested terminal device can be improved. .

Description of the drawings

In order to more clearly describe the technical solutions in the embodiments of the present application, the following will briefly introduce the drawings that need to be used in the description of the embodiments or the prior art. Obviously, the drawings in the following description are only of the present application. For some embodiments, for those of ordinary skill in the art, other drawings may be obtained based on these drawings without creative labor.

FIG. 1 is a first flowchart of a benchmark test method provided by an embodiment of the present application;

FIG. 2 is an example diagram of a two-dimensional adjacency matrix corresponding to a data storage diagram provided by an embodiment of the present application; FIG.

FIG. 3 is a second flowchart of a benchmark test method provided by an embodiment of the present application;

FIG. 4 is a structural diagram of a benchmark test system provided by an embodiment of the present application;

Fig. 5 is a structural diagram of a terminal device provided by an embodiment of the present application.

Detailed ways

In the following description, for the purpose of illustration rather than limitation, specific details such as a specific system structure and technology are proposed for a thorough understanding of the embodiments of the present application. However, it should be clear to those skilled in the art that the present application can also be implemented in other embodiments without these specific details. In other cases, detailed descriptions of well-known systems, devices, circuits, and methods are omitted to avoid unnecessary details from obstructing the description of this application.

It should be understood that when used in this specification and the appended claims, the term "comprising" indicates the existence of the described features, wholes, steps, operations, elements and/or components, but does not exclude one or more other features , The existence or addition of a whole, a step, an operation, an element, a component, and/or a collection thereof.

It should also be understood that the terms used in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit the application. As used in the specification of this application and the appended claims, unless the context clearly indicates other circumstances, the singular forms "a", "an" and "the" are intended to include plural forms.

It should be further understood that the term "and/or" used in the specification and appended claims of this application refers to any combination and all possible combinations of one or more of the associated listed items, and includes these combinations .

As used in this specification and the appended claims, the term "if" can be interpreted as "when" or "once" or "in response to determination" or "in response to detection" depending on the context . Similarly, the phrase "if determined" or "if detected [described condition or event]" can be interpreted as meaning "once determined" or "in response to determination" or "once detected [described condition or event]" depending on the context ]" or "in response to detection of [condition or event described]".

It should be understood that the size of the sequence number of each step in this embodiment does not mean the order of execution, and the execution sequence of each process should be determined by its function and internal logic, and should not constitute any limitation to the implementation process of the embodiment of the present application.

In order to illustrate the technical solutions described in the present application, specific embodiments are used for description below.

Refer to Fig. 1, which is a first flowchart of a benchmark test method provided by an embodiment of the present application. As shown in Figure 1, a benchmark test method is applied to a terminal device. The terminal device can be a supercomputer, a server cluster, and other devices that can implement data processing. The method includes the following steps:

Step 101: Obtain model data.

Among them, the model data is used to generate a data storage map. More specifically, the model data can randomly generate a data storage map based on the input map scale parameter. The graph scale parameter here is, for example, the number of vertices and the number of edges of the graph.

The model data corresponds to the graph generation model needed to build the data storage graph, that is, the model data is specifically the code data corresponding to the graph generation model. For example, in the benchmark software corresponding to Graph500, the graph generation model may specifically be a multi-recursive generator.

Step 102: Perform a reduction process on the model data. After the reduction process, the number of data bits of the parameters in the model data is reduced.

This bit reduction processing is a processing operation to shorten the number of data bits. The lowering processing of the model data is the lowering processing of the parameters included in the data model. Normally, the model data includes variable parameters and constant parameters.

Optionally, when performing the downgrade processing on the model data, only the target data in the model data may be downgraded, for example, the variable parameters included in the model data are used as the target data for the downgrade processing. The variable parameter is used to represent the node variable parameter of the node data in the data storage graph, the side variable parameter used to represent the edge data of the data storage graph, or other variable parameters needed to generate the data storage graph.

As a specific implementation manner, the derating processing of the model data includes: compressing the model data according to the data type of the model data.

For example, the data type can be a character type, a floating point type, an integer type, and so on.

The terminal device can perform different compression processing on the parameters of different data types in the model data. For example, the data type of the node variable parameter in the model data is int64 (that is, the data occupies a 64-bit integer), and the node variable parameter is expressed in the data occupancy of 64 bits, which can be based on the node variable parameter The data type of the node variable parameter is lowered, and the number of bits occupied by the node variable parameter data after lowering can be specifically adjusted to 32 bits. The data bits of the variable parameter of the node are shortened from 64 bits to 32 bits.

More specifically, when compressing the model data according to the data type of the model data, the data type of the parameter (specifically, the variable parameter) in the model data can be reduced by the size of the data type, so that the model data The data bits of the parameters corresponding to different data types are reduced accordingly. For other data types, the process of lowering bit processing is the same. In specific implementation, specific settings can be made according to actual data compression requirements, which are not limited in this application.

It is worth noting that by degrading the model data, the data items contained in the model data (such as the side variable parameters and the node variable parameters) can be kept unchanged, and the premise of ensuring that the graph scale of the data storage graph remains unchanged Next, reduce the amount of data in the data storage diagram.

Step 103: Generate a data storage map based on the model data after the downgrade processing.

The data storage graph includes a plurality of nodes and a plurality of edges for representing the connection relationship between the plurality of nodes.

Here, the data storage graph is a data storage structure, specifically a data storage structure that stores data in the form of edges and nodes.

The generation process of the data storage graph can be based on the set number of nodes and edges, and the model data is used to generate random numbers (ie node data) to represent each node and to represent the connection relationship between the nodes. The random numbers (that is, the edge data) of the (that is, the edge) are composed of these random numbers to form a two-dimensional adjacency matrix to realize the construction of the data storage graph.

Among them, as shown in Figure 2, each node of the multiple nodes in the data storage diagram is represented by one node data (may be a random number), and each node has different data. For example, in Figure 2, four nodes are represented by V0, V1, V2, and V3. Each of the multiple edges is also represented by one edge data. Here, each edge data is the same, for example, the edge data is 1. When the edge data is 1, it indicates that there is a connection between the two nodes, that is, there is an edge between the two nodes; when there is no edge between the two nodes, there is no corresponding edge data, and 0 is used instead. . For example, in Figure 2, the edge data between V0 and V1, V2, and V3 is 1, which means that there are edges between V0 and V1, V2, and V3 respectively; the edge data between V1 and V0 and V2 is 1, which means V1 There are edges between V0 and V2, respectively; the edge data between V1 and V3 is 0, which means that there is no edge between V1 and V3; whether there is an edge connection relationship between other nodes in the graph is analogous to this method. Can.

In this step, since the number of data bits of the parameters in the model data after the downgrading process is reduced, the data storage graph generated according to the model data after the downgrading process has the edge data corresponding to different edges and the corresponding data of different nodes. The number of data bits of the node data decreases accordingly.

Specifically, for example, the data storage graph to be generated includes 4 nodes, and the node data corresponding to the 4 nodes are integer data 0, 1, 2, and 3. Taking the second node data 1 as an example, when the model data has not been downgraded, the data type of the node variable parameter corresponding to the node data in the model data is, for example, int64. The model data generates a data storage diagram, then the second node data 1 is stored as 0000000000 0000000000 0000000000 0000000000 0000000000 0000000000 0001; When the model data is degraded, the data type of the node variable parameter in the model data is adjusted from int64 to int32 (that is, the data occupies 32-bit integer), so that the data type is limited The number of data bits of the node variable parameters is reduced from 64 bits to 32 bits. In this process, the data type remains unchanged, and the length of the data parameter defined by the data type becomes smaller. Therefore, when the data storage diagram is generated from the model data after the downgrading process, the second node data 1 is specifically stored as 0000000000 0000000000 0000000000 01, the number of bits is reduced from 64 bits to 32 bits, which reduces the amount of data contained in the generated data storage graph and occupies less storage space.

Similarly, the process of downgrading other parameters in the model data is the same.

This process can reduce the data volume of edge data and node data corresponding to multiple edges and multiple nodes in the graph without losing the number of edges and nodes of the graph, and without changing the size of the graph, so that the size of the graph is the same The amount of data contained in the data storage diagram below has changed.

Step 104: Perform graph traversal on the data storage graph to obtain the number of edges that complete data access in a unit time.

The graph traversal is the process of traversing multiple nodes and multiple edges included in the data storage graph, that is, accessing each node data and edge data in turn.

The number of edges that complete data access specifically refers to the number of edges that complete access to edge data corresponding to the edge.

Among them, the breadth-first search (BFS-First Search, BFS) algorithm can be used to implement the graph traversal.

In the process of traversing the graph, the processor in the terminal device needs to access and read the generated data storage graph. And since the data storage graph generated from the model data after the downgrading process, the data volume of the node data and the edge data corresponding to the nodes and edges has been reduced, so the processor is storing the graph of the generated data, In the process of implementing graph traversal by reading data according to the cache line, a larger number of nodes and edges corresponding to the node data and edge data will be arranged in a cache line, so the nodes arranged in the cache line and The density of edges has been increased, which increases the number of nodes and edges that the cache line passes through when read, speeds up data scanning when the processor executes the graph traversal algorithm, and improves the detection accuracy of the actual operating performance of the tested terminal device Spend.

Among them, when performing graph traversal on the data storage graph, the number of edges that complete data access within a unit time needs to be recorded at the same time, and the number of edges that complete data access within this unit time represents the graph traversal speed. It is possible to further output the number of edges that complete data access in a unit time, so that relevant testers can obtain the actual operating performance of the detected terminal device based on the number of edges that complete data access in the unit time, and obtain the software optimization zone in the terminal device. The performance improvement effect that comes.

In the embodiment of the present application, the acquired model data is degraded, a data storage graph is generated based on the degraded model data, and the data storage graph is traversed to calculate the number of edges that complete data access in a unit time. Output to complete the benchmark test of the actual operating performance of the terminal device. In this process, the number of data bits of the parameters contained in the model data is reduced through the reduction of the model data, and the number of data bits of the node data and edge data in the generated data storage graph is also reduced to achieve Under the premise of the same graph scale (that is, the number of nodes and edges in the graph remains unchanged), the amount of data contained in the graph is compressed, so that the graph data in the graph traversal process can be increased without losing the number of edges and nodes of the graph. The data arrangement density in the cache line increases the amount of graph data read per unit time, increases the number of edges traversed per second in the graph traversal process, improves the graph traversal speed, and improves the actual operation of the tested terminal device The detection accuracy of performance is achieved, and at the same time, the performance improvement effect of software optimization in the terminal device is obtained.

The embodiments of the present application also provide different implementations of the benchmark test method.

Refer to FIG. 3, which is a second flowchart of a benchmark test method provided by an embodiment of the present application. As shown in Figure 3, a benchmark test method includes the following steps:

Step 301: Obtain model data.

The implementation process of this step is the same as the implementation process of step 101 in the foregoing embodiment, and will not be repeated here.

Step 302: Perform a reduction process on the model data. After the reduction process, the number of data bits of the parameters in the model data is reduced.

The implementation process of this step is the same as the implementation process of step 102 in the foregoing embodiment, and will not be repeated here.

Step 303: Obtain the scale parameter of the data storage map.

Wherein, the scale parameter is used to indicate the number of the multiple nodes and the multiple edges.

Specifically, the scale parameter includes, for example:

The number of vertices N, N=2 ^SCALE ;

The number of edges M, M=edgefactor*N.

Among them, the number of vertices of the graph is the logarithm of the base 2; SCALE represents the scale of the graph, which can be assigned according to actual needs; edgefactor is the edge factor, which is the ratio of the number of edges to the number of vertices, which can be assigned according to actual needs.

Step 304: If the scale parameter satisfies the preset value condition, the data storage map is generated according to the scale parameter and the model data after the downgrading process.

Specifically, after the scale parameter of the data storage map is obtained, the value of the scale parameter needs to be judged. When the scale parameter meets the size of the storage space that can be provided in the current terminal device, it is considered that the parameter value meets the Value conditions can generate a data storage map based on the scale parameter and the model parameter after downgrading.

Wherein, as an optional implementation manner, generating the data storage map according to the scale parameter and the model data after downgrading processing includes:

Determine the graph generation model according to the model data after the downgrading process; input the scale parameter into the graph generation model for processing, and obtain random numbers corresponding to the multiple edges and the multiple nodes respectively; according to the Random numbers are used to generate the data storage diagram, and the data storage diagram is a Kronecker diagram.

Kronecker diagram is a diagram generated by using non-standard matrix operation Kronecker product. In the process of generating the data storage graph, the Kronecker product operation is performed on the two matrices composed of all nodes (the elements contained in the matrix are random numbers representing the nodes), and the Kronecker diagram is obtained. Each element in the gram graph is assigned a random number corresponding to the edge connecting the corresponding two nodes.

Among them, in conjunction with Figure 2, each node of the multiple nodes in the data storage diagram is represented by a node data (can be a random number), and each node has different data. The figure uses V0. , V1, V2 and V3 represent four nodes. Each of the multiple edges is also represented by one edge data. Here, each edge data is the same, for example, the edge data is 1. As shown in Figure 2, when the edge data is 1, it indicates that there is a connection between the two nodes, that is, there is an edge between the two nodes; when there is no edge between the two nodes, there is no corresponding edge data , Use 0 instead.

Here, the random number corresponding to the edge is the edge data; the random number corresponding to the node is the node data.

The generation process of the data storage graph realizes that based on the set number of nodes and the number of edges, the random number used to represent each node and the random number used to represent the connection relationship (ie, edge) between the nodes are generated respectively, based on These random numbers realize the construction of the data storage graph.

Step 305: If the scale parameter does not satisfy the value condition, update the scale parameter so that the updated scale parameter satisfies the value condition, and perform processing according to the updated scale parameter and downgrading The subsequent model data generates the data storage map.

Specifically, after the scale parameter of the data storage map is obtained, the value of the scale parameter needs to be judged. When the scale parameter does not meet the size of the storage space that can be provided in the current terminal device, it is considered that the value does not meet the value Condition, the scale parameter needs to be adjusted at this time, and the adjusted scale parameter needs to meet the value condition.

Correspondingly, the data storage map is generated according to the updated scale parameters and the model data after downgrading processing, including:

Determine the graph generation model according to the model data after the downgrading process; input the updated scale parameters into the graph generation model for processing to obtain random numbers corresponding to the multiple edges and the multiple nodes; The random number generates the data storage diagram, and the data storage diagram is a Kronecker diagram.

This process is the same as the foregoing process of generating a data storage map based on the scale parameter and the model data after the downgrading process, and will not be repeated here.

Step 306: Perform graph traversal on the data storage graph to obtain the number of edges that complete data access in a unit time.

The implementation process of this step is the same as the implementation process of step 104 in the foregoing embodiment, and will not be repeated here.

Referring to FIG. 4, FIG. 4 is a structural diagram of a benchmark test system provided by an embodiment of the present application. For ease of description, only parts related to the embodiment of the present application are shown.

The benchmark test system 400 includes:

The obtaining module 401 is used to obtain model data;

The data processing module 402 is configured to perform a downgrade process on the model data, and after the downgrade process, the number of data bits of the parameters in the model data is reduced;

The generating module 403 is configured to generate a data storage graph according to the model data after the downgrading process, the data storage graph including a plurality of nodes and a plurality of edges for representing the connection relationship between the plurality of nodes;

The graph traversal module 404 is configured to perform graph traversal on the data storage graph to obtain the number of edges that complete data access in a unit time.

The data processing module 402 is specifically configured to compress the model data according to the data type of the model data.

Among them, the test system also includes:

A parameter acquisition module, configured to acquire a scale parameter of the data storage graph, where the scale parameter is used to indicate the number of the multiple nodes and the multiple edges;

If the scale parameter satisfies the preset value condition, the generating module 403 includes: a first generating sub-module, configured to generate the data storage map according to the scale parameter and the model data after the downgrading process.

Wherein, the first generation sub-module is specifically used for:

Among them, the test device also includes:

An update module, configured to update the scale parameter if the scale parameter does not satisfy the value condition, so that the updated scale parameter satisfies the value condition;

Correspondingly, the generating module 403 includes: a second generating sub-module, configured to generate the data storage map according to the updated scale parameter and the model data after the downgrading process.

Wherein, the second generation sub-module is specifically used for:

Determine the graph generation model according to the model data after the downgrading process;

Input the updated scale parameter into the graph generation model for processing to obtain random numbers corresponding to the multiple edges and the multiple nodes respectively;

The data storage diagram is generated according to the random number, and the data storage diagram is a Kronecker diagram.

The benchmark test system provided by the embodiment of the present application can implement the various processes of the above-mentioned benchmark test method embodiment, and can achieve the same technical effect. In order to avoid repetition, it will not be repeated here.

Fig. 5 is a structural diagram of a terminal device provided by an embodiment of the present application. As shown in the figure, the terminal device 5 of this embodiment includes: at least one processor 50 (only one is shown in FIG. 5), a memory 51, and stored in the memory 51 and can be stored in the at least one processor 50 The computer program 52 running on the processor 50 implements the steps in any of the foregoing method embodiments when the processor 50 executes the computer program 52.

The terminal device 5 may be a computing device such as a desktop computer, a notebook, a palmtop computer, and a cloud server. The terminal device 5 may include, but is not limited to, a processor 50 and a memory 51. Those skilled in the art can understand that FIG. 5 is only an example of the terminal device 5, and does not constitute a limitation on the terminal device 5. It may include more or less components than those shown in the figure, or a combination of certain components, or different components. For example, the terminal device may also include input and output devices, network access devices, buses, and so on.

The so-called processor 50 may be a central processing unit (Central Processing Unit, CPU), other general-purpose processors, digital signal processors (Digital Signal Processor, DSP), and application specific integrated circuits (Application Specific Integrated Circuits). Integrated Circuit, ASIC), ready-made programmable gate array (Field-Programmable Gate Array, FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor may be a microprocessor or the processor may also be any conventional processor or the like.

The memory 51 may be an internal storage unit of the terminal device 5, such as a hard disk or a memory of the terminal device 5. The memory 51 may also be an external storage device of the terminal device 5, such as a plug-in hard disk, a smart memory card (Smart Media Card, SMC), and a secure digital (Secure Digital, SD) equipped on the terminal device 5. Card, Flash Card, etc. Further, the memory 51 may also include both an internal storage unit of the terminal device 5 and an external storage device. The memory 51 is used to store the computer program and other programs and data required by the terminal device. The memory 51 can also be used to temporarily store data that has been output or will be output.

Those skilled in the art can clearly understand that, for the convenience and conciseness of description, only the division of the above functional units and modules is used as an example. In practical applications, the above functions can be allocated to different functional units and modules as needed. Module completion, that is, the internal structure of the device is divided into different functional units or modules to complete all or part of the functions described above. The functional units and modules in the embodiments can be integrated into one processing unit, or each unit can exist alone physically, or two or more units can be integrated into one unit. The above-mentioned integrated units can be hardware-based Formal realization can also be realized in the form of a software functional unit. In addition, the specific names of the functional units and modules are only for the convenience of distinguishing each other, and are not used to limit the protection scope of the present application. For the specific working process of the units and modules in the foregoing system, reference may be made to the corresponding process in the foregoing method embodiment, which will not be repeated here.

In the above-mentioned embodiments, the description of each embodiment has its own focus. For parts that are not described in detail or recorded in an embodiment, reference may be made to related descriptions of other embodiments.

A person of ordinary skill in the art may realize that the units and algorithm steps of the examples described in combination with the embodiments disclosed herein can be implemented by electronic hardware or a combination of computer software and electronic hardware. Whether these functions are executed by hardware or software depends on the specific application and design constraint conditions of the technical solution. Professionals and technicians can use different methods for each specific application to implement the described functions, but such implementation should not be considered beyond the scope of this application.

In the embodiments provided in this application, it should be understood that the disclosed system/terminal device and method may be implemented in other ways. For example, the system/terminal device embodiments described above are only illustrative. For example, the division of the modules or units is only a logical function division, and there may be other divisions in actual implementation, such as multiple units. Or components can be combined or integrated into another system, or some features can be omitted or not implemented. In addition, the displayed or discussed mutual coupling or direct coupling or communication connection may be indirect coupling or communication connection through some interfaces, devices or units, and may be in electrical, mechanical or other forms.

The units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the objectives of the solutions of the embodiments.

In addition, the functional units in the various embodiments of the present application may be integrated into one processing unit, or each unit may exist alone physically, or two or more units may be integrated into one unit. The above-mentioned integrated unit can be implemented in the form of hardware or software functional unit.

If the integrated module/unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer readable storage medium. Based on this understanding, the present application implements all or part of the processes in the above-mentioned embodiments and methods, and can also be completed by instructing relevant hardware through a computer program. The computer program can be stored in a computer-readable storage medium. When the program is executed by the processor, it can implement the steps of the foregoing method embodiments. Wherein, the computer program includes computer program code, and the computer program code may be in the form of source code, object code, executable file, or some intermediate forms. The computer-readable medium may include: any entity or device capable of carrying the computer program code, recording medium, U disk, mobile hard disk, magnetic disk, optical disk, computer memory, read-only memory (ROM, Read-Only Memory) , Random Access Memory (RAM, Random Access Memory), electrical carrier signal, telecommunications signal, and software distribution media, etc. It should be noted that the content contained in the computer-readable medium can be appropriately added or deleted according to the requirements of the legislation and patent practice in the jurisdiction. For example, in some jurisdictions, according to the legislation and patent practice, the computer-readable medium Does not include electrical carrier signals and telecommunication signals.

This application implements all or part of the processes in the above-mentioned embodiments and methods, and can also be implemented by computer program products. When the computer program product runs on a terminal device, the terminal device can realize the implementation of the various method embodiments described above when the terminal device is executed. A step of.

The above-mentioned embodiments are only used to illustrate the technical solutions of the present application, not to limit them; although the present application has been described in detail with reference to the foregoing embodiments, a person of ordinary skill in the art should understand that it can still implement the foregoing The technical solutions recorded in the examples are modified, or some of the technical features are equivalently replaced; these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the application, and should be included in Within the scope of protection of this application.

Claims

A benchmark test method applied to terminal equipment, which is characterized in that it includes:

Obtain model data;

Perform a downgrade process on the model data, and after the downgrade process, the number of data bits of the parameters in the model data is reduced;

Generating a data storage graph according to the model data after the downgrading process, the data storage graph including a plurality of nodes and a plurality of edges for representing the connection relationship between the plurality of nodes;

Graph traversal is performed on the data storage graph to obtain the number of edges that complete data access in a unit time.
The benchmark test method according to claim 1, wherein the downgrading of the model data comprises:

According to the data type of the model data, the model data is compressed.
The benchmark test method according to claim 1, wherein before generating a data storage map according to the model data after the downgrading process, the benchmark test method further comprises:

Acquiring a scale parameter of the data storage graph, where the scale parameter is used to indicate the number of the multiple nodes and the multiple edges;

If the scale parameter satisfies a preset value condition, generating a data storage map according to the model data after the downgrading process includes:

The data storage map is generated according to the scale parameter and the model data after the downgrading process.
The benchmark test method according to claim 3, wherein said generating said data storage map according to said scale parameter and said model data after downgrading processing comprises:

Determining a graph generation model according to the model data after the downgrading process;

Inputting the scale parameter into the graph generation model for processing to obtain random numbers corresponding to the multiple edges and the multiple nodes respectively;

The data storage diagram is generated according to the random number, and the data storage diagram is a Kronecker diagram.
The benchmark test method according to claim 3, wherein after said obtaining the scale parameter of the data storage map, the benchmark test method further comprises:

If the scale parameter does not satisfy the value condition, update the scale parameter so that the updated scale parameter satisfies the value condition;

Correspondingly, the generating a data storage map according to the model data after the downgrading process includes:

The data storage map is generated according to the updated scale parameter and the model data after the downgrading process.
The benchmark test method according to claim 5, wherein the generating the data storage map according to the updated scale parameter and the model data after the downgrading process comprises:

Determining a graph generation model according to the model data after the downgrading process;

Input the updated scale parameter into the graph generation model for processing to obtain random numbers corresponding to the multiple edges and the multiple nodes respectively;

The data storage diagram is generated according to the random number, and the data storage diagram is a Kronecker diagram.
A benchmark test system, characterized in that it comprises:

The acquisition module is used to acquire model data;

The data processing module is used to perform a downgrade processing on the model data, and after the downgrade processing, the number of data bits of the parameters in the model data is reduced;

A generating module, configured to generate a data storage graph according to the model data after the downgrading process, the data storage graph including a plurality of nodes and a plurality of edges for representing the connection relationship between the plurality of nodes;

The graph traversal module is used to perform graph traversal on the data storage graph to obtain the number of edges that complete data access in a unit time.
The benchmark test system according to claim 7, wherein the data processing module is specifically configured to:

According to the data type of the model data, the model data is compressed.
A terminal device, comprising a memory, a processor, and a computer program stored in the memory and capable of running on the processor, wherein the processor executes the computer program as claimed in claims 1 to 6. Steps of any one of the methods.
A computer-readable storage medium storing a computer program, wherein the computer program implements the steps of the method according to any one of claims 1 to 6 when the computer program is executed by a processor.