CN111586995A

CN111586995A - Multilayer organic substrate and manufacturing method thereof

Info

Publication number: CN111586995A
Application number: CN202010547064.9A
Authority: CN
Inventors: 陶克文; 罗雄科; 袁凯华
Original assignee: Shanghai Zenfocus Semi Tech Co ltd
Current assignee: Shanghai Zenfocus Semi Tech Co ltd
Priority date: 2020-06-16
Filing date: 2020-06-16
Publication date: 2020-08-25
Anticipated expiration: 2040-06-16
Also published as: CN111586995B

Abstract

The technical field of the invention is the field of semiconductor test, and provides a multilayer organic substrate and a manufacturing method thereof, wherein the method comprises the following steps: manufacturing a probe implantation layer with a first precise circuit on a bearing plate by an additive method/semi-additive method; manufacturing a functional combination layer with a second precise circuit on the probe implantation layer by an additive method/semi-additive method, wherein the circuit precision requirement of the second precise circuit is lower than that of the first precise circuit; combining the dielectric layer and the conductor layer which are manufactured in parallel to manufacture a core combination layer capable of being quickly added with layers, and covering the core combination layer on the functional combination layer; and manufacturing a fan-out circuit combination layer and a BGA PAD layer for transferring a load board on the core combination layer in an additive/semi-additive mode to form a multi-layer organic substrate. The manufacturing method of the multilayer organic substrate with low cost and short manufacturing period is realized, so that the minimum C4Pad distance of the multilayer organic substrate is reduced, the wiring density of a probe implantation layer is improved, and meanwhile, the C4Pad surface can obtain super-flatness.

Description

Multilayer organic substrate and manufacturing method thereof

Technical Field

The invention relates to the field of semiconductor testing, in particular to a multilayer organic substrate and a manufacturing method thereof.

Background

MLO is an abbreviation for Multi layered Organic substrate, chinese is a multilayer Organic carrier used to carry a vertical probe card to test uncut wafers; the size of the probe implanted on the MLO needs to match the contact (C4 Pad) on the wafer to be tested, so this requires the MLO substrate to have a high-precision circuit layer (C4Side), the probe implantation and the test require the substrate to have high rigidity and strength, which are usually required by increasing the total board thickness, the wafer test requires the probe to have good coplanarity, and this requires the MLO substrate implanted with the probe to have good surface flatness.

The conventional method for manufacturing the MLO multi-layer organic substrate is a traditional core (core) plate layer build-up process, wherein a core plate layer is firstly manufactured, functional layers are manufactured on the core layer by a SAP process build-up process, and finally a C4side layer with the most precise requirement is manufactured on the outermost layer, and the structure of the MLO multi-layer organic substrate can be described as 2+ N +2/3+ N +3/4+ N +4, for example. The middle N (representing the number of inner layers) is a core layer for supporting and increasing the thickness, the outer side is a high-density interconnection layer with more than 2 steps made by a Build up method (Build up), and the number is the order of the Build up method. Because the requirement of the MLO butt joint and the chip layer C4 on the line density is extremely high, the traditional subtractive process for PCB/BGA can not be manufactured, even the traditional mSAP process commonly used by Substrate is difficult to meet the requirement, the latest technical requirement can only use the full addition SAP process of ABF film of Japan heavy-moving-flavor, the electroplating process is mainly used for the packaging Substrate in high-performance operation fields such as high-order CPU/GPU due to high cost, the technical limit line width/line distance (15/15um), the MLO production based on the existing process needs more than 10 times of lines, pressing, drilling process, complex flow, high cost, long delivery period, technical bottleneck and continuous progression difficulty.

The embedded line process is derived from an old Damascus damascene process (damascone process), is used for high-density additive method/semi-additive method wiring in the field of semiconductor packaging, is suitable for manufacturing a single high-density wiring layer of a packaging substrate, is applied to the field of thin substrates with generally few layers, the increment generally does not exceed 3 times, the cost is higher when the number of layers is larger compared with that of a traditional double-sided layer-increasing process, the embedded line process is still lower in the field of the packaging substrate at present, and the single embedded line process cannot be suitable for MLO substrates with extremely high layer number and high thickness requirements.

Disclosure of Invention

The invention aims to provide a multilayer organic substrate and a manufacturing method thereof, which solve the problems, realize the manufacturing method of the multilayer organic substrate with low cost and short manufacturing period, further reduce the minimum distance of C4Pad of the multilayer organic substrate and improve the wiring density of a probe implantation layer, and simultaneously, the C4Pad surface can obtain the technical characteristics of ultra-flatness.

The technical scheme provided by the invention is as follows:

a method of fabricating a multilayer organic substrate, comprising the steps of:

a probe implantation layer with a first precise circuit is manufactured on a bearing plate by an additive method/semi-additive method, and the probe implantation layer is used for implanting a probe.

And manufacturing a functional combination layer with a second precise circuit on the probe implantation layer by an additive method/semi-additive method, wherein the circuit precision requirement of the second precise circuit is lower than that of the first precise circuit.

And combining the dielectric layer and the conductor layer which are manufactured in parallel to manufacture a core combination layer capable of being quickly added, and covering the core combination layer on the functional combination layer.

And manufacturing a fan-out circuit combination layer and a BGA PAD layer for switching a loader board on the core combination layer by an additive method/semi-additive method to form a multilayer organic substrate.

And the first precise circuit, the second precise circuit, the conductor in the conductor layer, the fan-out circuit in the fan-out circuit combination layer and the BGA PAD layer are mutually conducted in circuit.

Further preferably, the manufacturing of the probe implantation layer with the first fine circuit further includes the steps of:

and manufacturing a first precise circuit of the probe implantation layer on the bearing plate through a photomask aligning machine or a stepping photoetching process so as to form the probe implantation layer.

Further preferably, the fabricating of the probe implantation layer with the first fine circuit on the carrier substrate by an additive/semi-additive method specifically includes the steps of:

and pressing a photosensitive dry film on the bearing plate, and forming a circuit negative film after exposure and development.

Through electroplating the circuit negative is in order to form the first accurate circuit on layer is implanted to the probe, peels off the sensitization dry film obtains the first accurate circuit on layer is implanted to the probe is implanted in order to form the layer is implanted to the probe.

Further preferably, the fabricating a functional combination layer with a second fine circuit on the probe implantation layer by an additive/semi-additive method includes:

and forming a dielectric layer on the circuit of the probe implantation layer through pressing.

And manufacturing an interlayer conduction path and a second precise line on the dielectric layer by laser drilling.

Filling holes in the interlayer conduction path through an mSAP/SAP hole filling electroplating process to form a functional layer; the functional combination layer comprises at least one functional layer.

Further preferably, the step of fabricating a core composite layer capable of rapidly increasing layers by combining the dielectric layer and the conductor layer fabricated in parallel includes the steps of:

and manufacturing dielectric layers in parallel, and pre-drilling the dielectric layers.

And manufacturing a conductor layer in parallel, and manufacturing a circuit of the conductor layer.

And aligning and attaching the dielectric layer and the conductor layer which are pre-drilled in a rapid layer increasing mode, and plugging holes to form the core combination layer.

Further preferably, before the fan-out wiring combination layer and the BGA PAD layer for transferring a load board are manufactured by an additive/semi-additive method on the core combination layer to form the multi-layer organic substrate, the method includes the steps of:

and carrying out a heat treatment process on the core combination layer so as to conduct the upper conductor layer and the lower conductor layer of the core combination layer.

Further preferably, the manufacturing of the fan-out circuit combination layer and the BGA PAD layer for transferring a load board on the core combination layer in an additive/semi-additive method to form the multi-layer organic substrate includes:

and forming a dielectric layer on the core combination layer through pressing.

And manufacturing an interlayer conduction path on the dielectric layer by laser drilling.

And filling holes in the interlayer conduction path through an mSAP/SAP hole filling electroplating process to form the fan-out circuit combination layer and the BGA PAD layer.

Further preferably, before the probe implantation layer with the first fine circuit is manufactured on the carrier board by an additive/semi-additive method, the method comprises the following steps:

and adhering a copper foil on the upper surface of the bearing plate, wherein the rough surface of the copper foil is an adhesion surface for adhering the bearing plate, and the smooth surface of the copper foil is used as a reference surface for manufacturing the probe implantation layer.

Further preferably, the method further comprises the following steps:

and manufacturing a solder mask layer on the surface of the BGA PAD layer through a screen printing process.

And pressing a protective film on the surface of the BGA PAD layer through a dry-wet film process.

And removing the bearing plate, and carrying out rapid flash etching on the C4side surface of the probe implantation layer to obtain the circuit pattern of the probe implantation layer.

And removing the protective film on the BGA surface to obtain the multilayer organic substrate.

Carrying out surface treatment on the multilayer organic substrate; the surface treatment process comprises EPENIG or EPIG.

The invention also provides a multilayer organic substrate which is manufactured by the manufacturing method of the multilayer organic substrate.

The multilayer organic substrate and the manufacturing method provided by the invention have the following beneficial effects:

1) the invention improves the process flow of MLO manufacturing based on the traditional Substrate process, firstly manufactures the circuit layer with highest requirement precision on the bearing plate, and combines the circuit layer with the interconnection rapid thickening technology of any layer, can solve the capability requirement of MLO on the extremely high precision fine line density, can manufacture more precise circuits without expensive SAP additive process lines, can reduce the manufacturing threshold of MLO, can obtain the ultra-flatness characteristic of the C4Pad surface, and is very suitable for the development requirement of wafer test technology.

2) The requirement of MLO product to high thickness base plate can be solved in the parallel preparation of quick interconnection layer, and the parallel quick interconnection layer is more suitable for the electric interconnection design than traditional inlayer core plate layer, and the preparation cycle is short, and is with low costs, can greatly promote product competitiveness.

3) The critical C4Pad minimum spacing of MLO can be raised from 60um-80um to 40um-60um in the invention.

4) The scheme can ensure that the wiring density Line W/S of the key layer is promoted from 15um/15um to 5um/5 um.

5) The process can manufacture a more precise probe implantation layer, namely a P1 layer circuit, by using a photomask aligner or a Stepper photoetching process, the line width and line distance of the process can reach 2-10 mu m, the process can completely match the size of a metal bump C4PAD manufactured by the Fan out packaging process of the prior high-order chip, and simultaneously, the circuit manufactured on a strongly-supported carrier plate can obtain the C4Side ultra-flatness characteristic without additionally manufacturing a solder mask.

6) The parallel rapid layer increasing process has excellent electrical performance and the advantages of high lamination thickness and rapid manufacturing, and can greatly reduce the MLO manufacturing period for testing the semiconductor CP and reduce the cost.

Drawings

The above features, technical features, advantages and modes of realisation of a multi-layer organic substrate and a method of manufacturing the same will be further described in the following, in a clearly understandable manner, with reference to the accompanying drawings, which illustrate preferred embodiments.

FIG. 1 is a flow chart of one embodiment of a method of fabricating a multilayer organic substrate of the present invention;

FIG. 2 is a flow chart of one embodiment of the present invention for fabricating a probe implant layer with a first fine line;

FIG. 3 is a flow chart of one embodiment of the present invention for fabricating a functional combination layer with a second fine line;

FIG. 4 is a flow chart of another embodiment of the present invention for fabricating a functional combination layer with a second fine line;

FIG. 5 is a schematic view of one embodiment of a multilayer organic substrate of the present invention;

FIG. 6 is a flow chart of yet another embodiment of the present invention for fabricating a probe implant layer with a first fine line;

FIG. 7 is a flow chart of another embodiment of the present invention for fabricating a functional combination layer with a second fine line;

FIG. 8 is a flow chart of one embodiment of the present invention for fabricating a rapidly build-up core build-up layer in combination with a dielectric layer and a conductor layer fabricated in parallel;

FIG. 9 is a flow chart of the present invention for fabricating a fan-out wiring assembly and a BGA PAD layer for a landing board;

the reference numbers illustrate:

1. a carrier plate; 2. copper surface; 3. photosensitive dry film; 4. a conductive substance; k1, pretreating a bearing plate; k2, pressing the film on the bearing plate; k3, adding a layer body of the circuit negative film; k4, adding a layer body of the non-film-removing probe implantation layer; k5, layer body of newly added probe implantation layer; k6, adding a layer body of a key layer; k7, adding a composite layer with a key layer with holes; k8, adding a layer body of the first functional layer; k9, manufacturing a preparation layer body of the second functional layer; k10, adding two functional layer bodies; k11, adding a layer body with a porous functional combination layer; k12, a key layer and a function combination layer which are conducted; p1, probe implantation layer; p2, first functional layer; p3, second functional layer; P4-P8, conductor layer; c1, a first dielectric layer; c2, a first dielectric layer; c3, a third medium layer; C4-C8 and a dielectric layer; P9-P10 and a fan-out circuit layer; p11, BGA PDA layer.

Detailed Description

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following description will be made with reference to the accompanying drawings. It is obvious that the drawings in the following description are only some examples of the invention, and that for a person skilled in the art, other drawings and embodiments can be derived from them without inventive effort.

For the sake of simplicity, the drawings only schematically show the parts relevant to the present invention, and they do not represent the actual structure as a product. In addition, in order to make the drawings concise and understandable, components having the same structure or function in some of the drawings are only schematically illustrated or only labeled. In this document, "one" means not only "only one" but also a case of "more than one".

In one embodiment of the present invention, as shown in fig. 1, a method for fabricating a multi-layer organic substrate includes the steps of:

s100, a probe implantation layer with a first precise circuit is manufactured on a bearing plate by an additive method/semi-additive method, and the probe implantation layer is used for implanting a probe.

In particular, the carrier plate may comprise FR4, a glass or a hard metal base plate. The copper foil is adhered to the upper surface of FR4 or glass or hard metal base plate, the copper foil needs a rough surface as an adhering surface and a smooth surface facing upwards to provide a reference surface for manufacturing a probe implanting layer, and the adhesive layer has reduced bonding force under a special temperature condition for removing the bearing plate. In the scheme, the addition method is MSAP, can be translated into a semi-addition method and also can be translated into an improved addition method, and belongs to the low-cost addition method. And meanwhile, SAP can be used for manufacturing the circuit.

Illustratively, 3/18um copper foil is adhered to the surface of glass or hard metal, 3um copper foil is arranged on the surface of the glass or hard metal, 18um copper foil is arranged on the lower portion of the bearing plate, 3um copper foil serves as base copper for manufacturing a probe implantation layer, and 3/18um copper foil is combined into a glue layer for bonding so as to be used for removing the bearing plate.

Illustratively, as shown in fig. 2, a C4side fine circuit layer, i.e., a probe implantation layer P1, is formed on a base plate, i.e., a carrier plate 1, by an additive/semi-additive process. Specifically, a pretreatment bearing plate K1 is obtained after a bearing plate 1 is subjected to 3um/8um copper surface 2 treatment; the K1 comprises a bearing plate 1 and a copper surface 2. Pressing the photosensitive dry film 3 on the pretreatment bearing plate K1 to obtain a pressed bearing plate K2; the K2 includes loading board 1, copper face 2, sensitization dry film 3. Form the layer body K3 that the circuit negative film obtained newly-increased circuit negative film through exposure development, K3 includes loading board 1, copper face 2, sensitization dry film 3, circuit negative film. And obtaining a layer body K4 of the newly added non-film-removed probe implantation layer after forming a circuit by electroplating, wherein the K4 comprises a bearing plate 1, a copper surface 2, a photosensitive dry film 3 and a circuit. The photosensitive dry film 3 is stripped to obtain a probe implantation layer, namely a layer K5 of a P1 precision circuit for forming a newly added probe implantation layer, and the K5 comprises a bearing plate 1, a copper surface 2 and a fine circuit layer probe implantation layer, namely P1. The precise circuit can be coated by the dielectric layer after being finished, and a better metal interface shape can be obtained. The replacement process can also use a photomask aligning machine or a Stepper photoetching process to manufacture a more precise circuit, namely a probe implantation layer P1 layer circuit, the line width and line distance of the probe implantation layer can reach 2-10um, the size of a metal bump C4PAD manufactured by the Fan out packaging process of the current high-order chip can be completely matched, and meanwhile, the circuit manufactured on a strongly-supported bearing plate can obtain the C4Side ultra-flatness characteristic without additionally manufacturing a solder mask. Exposure development may be performed using LDI.

and manufacturing a first precise circuit of the probe implantation layer on the bearing plate through a photomask alignment machine or a Stepper photoetching process so as to form the probe implantation layer.

S200, manufacturing a functional combination layer with a second precise circuit on the probe implantation layer by an additive method/semi-additive method, wherein the circuit precision requirement of the second precise circuit is lower than that of the first precise circuit.

Specifically, the functional combination layer includes at least one functional layer, and the number of layers of the functional layer may be manufactured according to project requirements. The material of the dielectric layer may include PP or ABF.

For example, as shown in fig. 3 to 4, a layer body K6 with a newly added key layer is formed by pressing and covering a first dielectric layer C1 on a probe implantation layer, i.e., a P1 layer circuit, where the K6 includes a carrier plate 1, a copper surface 2, a probe implantation layer P1 and a first dielectric layer C1, and a hot pressing or cold pressing process may be selected according to actual media requirements to manufacture the probe implantation layer.

And forming a combined layer K7 of the newly added porous key layer on the K6 by using laser drilling, and obtaining an interlayer conduction path and a first functional layer, namely a P2 precision line by using a mSAP hole filling electroplating process to form a layer K8 of the newly added first functional layer. Based on the wiring requirement, i.e. the precision requirement of the wiring of the first functional layer P2 is lower than that of the probe implantation layer P1, so that various wiring manufacturing methods such as SAP/MSAP are available; the process of manufacturing the first functional layer P2 is repeated to obtain a plurality of fine circuit layers, i.e. the second functional layer P3, as determined by the product requirements. A second dielectric layer C2 is pressed on a first functional layer P2 to form a prepared layer K9 for manufacturing a second functional layer, laser drilling is carried out on the K9, an mSAP hole filling electroplating process is carried out to obtain an interlayer conduction path and a precision line of the second functional layer P3, and a layer K10 with two newly added functional layers is formed. And pressing a third dielectric layer C3 on the K10, drilling holes by laser to form a layer body K11 of the newly added porous function combination layer, and plugging the K11 by a conductive substance 4 to form a conductive key layer and a function combination layer K12. The conductive substance 4 may include a conductive plug agent.

S300, combining the dielectric layer and the conductor layer which are manufactured in parallel to manufacture the core combination layer capable of being quickly added with layers, and covering the core combination layer on the functional combination layer.

Specifically, the core combination layer includes at least one core layer, and the number of functional layers may be made according to the requirement for thickness in the project.

Illustratively, parallel interconnection dielectric layers C3, C4, C5, C6, C7 and C8 are manufactured and pre-drilled; the hole can be made by laser drilling or photo-induced hole forming. Parallel interconnect conductor layers P4, P5, P6, P7, and P8 are fabricated, which may be fabricated by conventional etching processes. As shown in fig. 4, the holes of the parallel interconnect dielectric layer C3 are aligned with the lines of the second functional layer P3, and then pressed against the lines of the second functional layer P3, and holes are plugged by using a conductive material; the conductive plug holes can be pre-formed in the dielectric layer. Manufacturing a P4 circuit of a core conductor layer, aligning and then pressing and attaching the circuit to a C3 layer of medium; and repeating the above steps to manufacture a P5... P9 circuit layer and a C4.. C8 dielectric layer.

Preferably, a heat treatment process is performed after the core layer manufacturing process is completed, so that the dielectric layer is fully filled and tightly combined, and the conductive hole plugging agent in the hole is fully cured and is in conductive connection with the upper copper layer and the lower copper layer.

S400, manufacturing a fan-out circuit combination layer and a BGA PAD layer for switching a load board on the core combination layer by an additive method/semi-additive method to form a multilayer organic substrate.

Illustratively, precision circuits P9, P10, P11 are fabricated using additive/semi-additive methods, where P11 is the BGA PAD side, i.e., the BGA PAD layer used to transfer the load board. The load board is also called a load board.

In another embodiment of the present invention, based on the foregoing embodiment, as shown in fig. 6, in this embodiment, regarding step S100: the method for manufacturing the probe implantation layer with the first precise circuit on the bearing plate by the additive method/semi-additive method specifically comprises the following steps:

s101, pressing a photosensitive dry film on the bearing plate, and forming a circuit negative film after exposure and development.

S102, forming a first precise circuit of the probe implantation layer by electroplating the circuit negative film, and stripping the photosensitive dry film to obtain the first precise circuit of the probe implantation layer so as to form the probe implantation layer.

In another embodiment of the present invention, based on the foregoing embodiment, as shown in fig. 7, in this embodiment, regarding step S200: the method for manufacturing the functional combination layer with the second precise circuit on the probe implantation layer by an additive method/semi-additive method comprises the following steps:

and S201, forming a dielectric layer on the circuit of the probe implantation layer through pressing.

S202, manufacturing an interlayer conduction path and a second precise line on the dielectric layer through laser drilling.

S203, filling holes in the interlayer conduction path through an mSAP/SAP hole filling electroplating process to form a functional layer; the functional combination layer comprises at least one functional layer.

In another embodiment of the present invention, based on the foregoing embodiment, as shown in fig. 8, in this embodiment, the step of fabricating a core composite layer capable of fast layer increase by combining the dielectric layer and the conductive layer fabricated in parallel in step S300 includes the steps of:

s301, a dielectric layer is manufactured in parallel, and pre-drilling is carried out on the dielectric layer.

S302, a conductor layer is manufactured in parallel, and a circuit of the conductor layer is manufactured.

S303, aligning and attaching the dielectric layer and the conductor layer which are pre-drilled in a rapid layer increasing mode, and plugging holes to form the core combination layer.

Illustratively, the conductor layer may comprise a parallel build-up conductor layer obtained by a conventional etching process, typically a copper foil with an organic carrier, by an exposure development etching process to obtain the wiring, and then dissolving away the organic carrier. Illustratively, the hole in C3 is aligned to the wiring pattern of the second functional layer, P3, based on CCD alignment.

In another embodiment of the present invention, based on the foregoing embodiment, as shown in fig. 9, in this embodiment, regarding step S400: the method for manufacturing the fan-out circuit combination layer and the BGA PAD layer for switching the load board on the core combination layer by an additive method/semi-additive method to form the multilayer organic substrate comprises the following steps:

s401, forming a dielectric layer on the core combination layer through pressing.

S402, manufacturing an interlayer conduction path on the dielectric layer through laser drilling.

S403, filling holes in the interlayer conduction path through an mSAP/SAP hole filling electroplating process to form the fan-out circuit combination layer and the BGA PAD layer.

Specifically, with FR4, glass or hard metal surface paste 3um or 18um copper foil, 3um is last, 18um is at the bearing plate face of leaning on down, the effect of 3um copper foil is for providing the base copper of preparation probe implantation layer, 3um or 18um combine to glue the layer and bond in order to get rid of the loading board usefulness.

In some embodiments of the present invention, based on the above scheme, before the fan-out line combination layer and the BGA PAD layer for transferring a load board are manufactured on the core combination layer in an additive/semi-additive manner to form a multi-layer organic substrate, the method includes the following steps:

In some embodiments of the present invention, based on the above scheme, the method further includes the steps of:

The technical field of the invention is a space transformer high-precision component for semiconductor testing, which is mainly used for an electrical performance test link probe and a motherboard of a semiconductor wafer, is different from the traditional packaging substrate or a PCB (printed Circuit Board) which is used as a component for semiconductor testing and requires extremely high rigidity and strength besides higher precision requirement, is far more complex in electrical structure than a common packaging substrate and a common PCB, and has extremely high manufacturing cost and manufacturing period 5-10 times longer than that of the common packaging substrate.

Specifically, in the practical application scenario of Wafer bonding semiconductor Wafer testing, a ProbeCard Probe Card is required, and one of the important connection interfaces between the tester (ATE) and the object to be tested (DUT) is mechanically contacted in the micrometer (um) level to achieve the purpose of transmitting electrical signals, which is divided into a cantilever Probe Card (epoxy) Probe Card and a Vertical Probe Card.

The multilayer Organic substrate is also called MLO, which is an abbreviation of Multi layered Organic substrate, and Chinese can be translated into a multilayer Organic carrier plate which is used for carrying a vertical probe card to test an uncut wafer; the size of the implanted probes on the MLO needs to match the contacts on the wafer being tested (C4 Pad), so this requires MLO substrates with high precision wiring layers (C4Side), high stiffness and strength, usually by increasing the total board thickness, and good surface flatness.

Because the probe card needs to adapt to the higher integration level of a semiconductor wafer, the C4side pad of the MLO Substrate is required to be smaller and smaller, the current integration level reaches 60um pitch, the requirement of the line width and the line distance is less than 15/15um, the minimum 20um of the micro-drilling blind hole capability is required, the total board thickness is required to be more than 2mm, the laminated layers generally exceed 20 layers, the production period can exceed several months, the production capability of the current Substrate board factory is greatly challenged, the MLO is used as a precise component for ATE CP test, the required quantity is much smaller than that of the traditional Substrate, the unit cost cannot be reduced through large-scale production, many traditional high-end PCB suppliers are unwilling to invest resources for development, only a few suppliers exist at present, and the product price is very high. Along with the rapid expansion of the semiconductor market demand brought by the popularization of 5G, the improvement of the complex diversity of products, the acceleration of the update frequency of new products, the updating of related test tools required by each iteration of the products, and the urgent need for a new scheme to solve the problems of difficulty, high cost and long period of MLO manufacturing, the invention improves the process flow of MLO manufacturing based on the traditional Substrate process, firstly manufactures the circuit layer with the highest requirement on the bearing plate, and combines the circuit layer with the interconnection rapid thickening technology of any layer, can solve the capability requirement of the MLO on the extremely high precision fine line density, can manufacture more precise lines even without expensive SAP process lines, can reduce the manufacturing threshold of the MLO, can obtain the ultra-flatness characteristic of the C4Pad surface, is very suitable for the development requirement of wafer-level CP test technology, can solve the requirement of the MLO products on high-thickness substrates by the parallel manufacturing of the rapid interconnection layers, the parallel rapid interconnection layer is more suitable for electrical interconnection design than the traditional inner core plate layer, the manufacturing period is short, the cost is low, and the product competitiveness can be greatly improved.

The present invention also provides another embodiment of a method for manufacturing a multilayer organic substrate, as shown in fig. 2 to 5, including:

s01, adhering copper foil on the upper surface of FR4 or glass or hard metal base, wherein the copper foil needs a rough surface as an adhering surface and a smooth surface facing upwards and is used as a reference surface for S02 operation, and the adhesive layer has reduced bonding force under special temperature conditions for removing the bearing plate.

S02, manufacturing a fine circuit layer with a C4side surface on the base plate by an additive method/semi-additive method; specifically, a photosensitive dry film is pressed after the 3um copper surface is processed, a circuit negative film is formed after exposure and development, the dry film is stripped after a circuit is formed by electroplating, and a probe implantation layer, namely a P1 layer precision circuit, is completed. The precise circuit can be coated by the dielectric layer after being finished, and a better metal interface shape can be obtained. The replacement process can also use a Stepper photoetching process to manufacture a more precise probe implantation layer, namely a P1 layer circuit, the line width and line distance of the capability can reach 2-10um, the size of the metal bump C4PAD manufactured by the Fan out packaging process of the prior high-order chip can be completely matched, and meanwhile, the C4Side ultra-flatness characteristic can be obtained by manufacturing the circuit on a strongly supported carrier plate without additionally manufacturing a solder mask.

S03, the first dielectric layer C1 is laminated on the P1 layer circuit, and the manufacturing method can be selected according to actual dielectric requirements through a hot pressing or cold pressing process.

S04, laser drilling is used, and an mSAP hole filling electroplating process is used to obtain an interlayer conduction path and a first functional layer P2 precise line. Based on the wiring requirement, the wiring precision requirement of the first functional layer, i.e. P2, is lower than that of the probe implantation layer, i.e. P1, so that various wiring manufacturing methods, such as SAP/MSAP; the process of S02 is repeated as determined by product requirements to obtain a multi-layered fine wiring layer, i.e., the second functional layer P3.

S05, manufacturing parallel interconnection dielectric layers C3/C4/C5/C6/C7/C8 and pre-drilling holes; the hole can be made by laser drilling or photo-induced hole forming.

S06, parallel interconnection conductor layer P4/P5/P6/P7/P8, the conductor can be made by traditional etching process.

S07, aligning and pressing the parallel interconnection dielectric layer C3 on the second functional layer, namely the P3 layer circuit, and plugging holes by using a conductive substance; the conductive plug holes can be pre-formed in the dielectric layer.

S07, making P4 circuit of the core conductor layer, aligning and pressing on the C3 layer medium.

And S08, repeating the steps S05-S07 to manufacture the P5... P9 line layer and the C4.. C8 dielectric layer.

And S09, performing a heat treatment process after the core layer manufacturing process is completed to fully fill the dielectric layer and tightly combine the dielectric layer, and fully curing the conductive hole plugging agent in the hole and connecting the upper copper layer and the lower copper layer in a conduction manner.

S10, manufacturing a precision circuit P9/P10/P11 by using an additive method/semi-additive method, wherein P11 is a BGA PAD surface.

S11, a solder mask layer of the BGA PAD surface is manufactured.

S12, pressing the protection film on the P11 surface which is the BGA PAD surface.

S13, removing the carrier plate, and rapidly flashing the probe implantation layer (P1 surface) to remove the ultrathin copper layer to obtain the probe implantation layer (P1 circuit pattern).

S14, removing the BGA PAD surface protection film.

S15, surface treatment processes EPENIG/EPIG and the like are produced.

The invention can improve the minimum distance of the critical C4Pad of the MLO from the existing 60um-80um to 40um-60um from the technical point of view.

Specifically, the pitch comprises 2 parts: the diameter of C4PAD and the isolation distance of C4PAD are limited by the manufacturing capacity of micropores 25-40 um, the diameter of C4PAD is designed at 40-60um, the isolation space is 20um traditionally, and the aperture tolerance in the wire embedding technology can be reduced, so that the diameter of C4PAD can be further reduced to 30-50 um, and the minimum isolation space capacity of the wire embedding technology can be 10um or even less than 5 um.

The invention can also increase the wiring density Line W/S of the key layer from 15um/15um to 5um/5 um. The critical layer is the probe implantation layer of the first layer, which not only includes the C4PAD spacing, but also includes the corresponding connecting circuit, and the circuit density requirements of other layers are reduced.

Meanwhile, the C4Pad surface can obtain the technical characteristics of super-flatness; the parallel rapid layer increasing process has excellent electrical performance and the advantages of high lamination thickness and rapid manufacturing, and can greatly reduce the MLO manufacturing period for the CP test of the semiconductor and reduce the cost.

Specifically, the probe implantation layer comprises a circuit layer of a C4Pad surface for testing, and is used for probe implantation. The functional combination layer comprises at least one functional layer for communicating signals or shielding signals. The core assembly layer includes at least one core layer for providing power and increasing the thickness of the multi-layered organic substrate. And the fan-out line combination layer is used for fan-out signals. The BGA PAD layer is used for switching the loadboard.

Illustratively, the multilayer organic substrate includes:

(1) the ultra-precise circuit layer of the C4Pad surface for testing is mainly used for precise probe implantation; the functional layers such as signal and shielding are attached to the substrate 2-5, and the process for manufacturing the precise circuit layer can use an embedded circuit, a semiconductor photoetching process and the like.

(2) A group of arbitrarily interconnected rapid increasing layers (6-25 layers) which are mainly used for GND/PWR layers and increasing the overall thickness; the invention provides a rapid layer increasing process based on parallel manufacturing, which can also be rapidly manufactured by using a 3D printing circuit technology.

(3) The BGA Pad layer and the attached fan-out circuit layer thereof are used for switching the load board; it can be made by conventional additive/semi-additive process.

Specifically, the pitch comprises 2 parts: the diameter of C4PAD and the isolation distance of C4Pad are limited by the manufacturing capacity of micropores of 25-40 um, the diameter of C4Pad is designed at 40-60um, the isolation space is traditionally 20um, and the tolerance of the aperture in the wire embedding technology can be reduced, so that the diameter of C4PAD can be further reduced to 30-50 um, and the minimum isolation space capacity of the wire embedding technology can be 10um or even less than 5 um.

In the scheme, the Line density Line W/S of the key layer can be increased from 15um/15um to 5um/5 um. The critical layer is the probe implantation layer of the first layer, which not only includes the C4PAD spacing, but also includes the corresponding connecting circuit, and the circuit density requirements of other layers are reduced.

It should be noted that the above embodiments can be freely combined as necessary. The foregoing is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, various modifications and decorations can be made without departing from the principle of the present invention, and these modifications and decorations should also be regarded as the protection scope of the present invention.

Claims

1. A method for fabricating a multilayer organic substrate, comprising:

manufacturing a probe implantation layer with a first precise circuit on a bearing plate by an additive method/semi-additive method, wherein the probe implantation layer is used for implanting a probe;

manufacturing a functional combination layer with a second precise circuit on the probe implantation layer by an additive method/semi-additive method, wherein the circuit precision requirement of the second precise circuit is lower than that of the first precise circuit;

combining the dielectric layer and the conductor layer which are manufactured in parallel to manufacture a core combination layer capable of being quickly added with layers, and covering the core combination layer on the functional combination layer;

manufacturing a fan-out circuit combined layer and a BGA PAD layer for switching a load board on the core combined layer by an additive method/semi-additive method to form a multilayer organic substrate;

2. The method of claim 1, wherein the step of forming a probe implant layer having a first fine line further comprises the steps of:

3. The method for fabricating the multi-layered organic substrate according to claim 2, wherein the probe implantation layer having the first fine circuit is fabricated on the carrier substrate by an additive/semi-additive process, comprising the steps of:

pressing a photosensitive dry film on the bearing plate, and forming a circuit negative film after exposure and development;

4. The method for fabricating a multi-layered organic substrate according to claim 2, wherein the fabricating a functional combination layer having a second fine line on the probe implantation layer by an additive/semi-additive method comprises:

forming a dielectric layer on the circuit of the probe implantation layer through pressing;

manufacturing an interlayer conduction path and a second precise line on the dielectric layer through laser drilling;

5. The method of claim 1, wherein the step of fabricating a core build-up layer by combining the dielectric layer and the conductive layer fabricated in parallel comprises:

manufacturing dielectric layers in parallel, and pre-drilling the dielectric layers;

manufacturing conductor layers in parallel, and manufacturing lines of the conductor layers;

6. The method of claim 1, wherein before the step of additively/semi-additively forming the fan-out line assembly layer and the BGA PAD layer for a landing board on the core assembly layer to form the multi-layered organic substrate, the method comprises the steps of:

7. The method of claim 1, wherein the fan-out wiring assembly layer and the BGA PAD layer for a landing board are formed on the core assembly layer by an additive/semi-additive method to form a multi-layer organic substrate, comprising the steps of:

forming a dielectric layer on the core combination layer through pressing;

manufacturing an interlayer conduction path on the dielectric layer through laser drilling;

8. The method of claim 1, wherein before the probe implantation layer with the first fine circuit is formed on the carrier substrate by additive/semi-additive method, the method comprises the following steps:

9. The method for fabricating a multilayer organic substrate according to any one of claims 1 to 8, further comprising the steps of:

manufacturing a solder mask layer on the surface of the BGA PAD layer through a screen printing process;

pressing a protective film on the surface of the BGA PAD layer through a dry-wet film process;

removing the bearing plate, and carrying out rapid flash etching on the C4side surface of the probe implantation layer to obtain a circuit pattern of the probe implantation layer;

removing the protective film on the BGA surface to obtain the multilayer organic substrate;

10. A multilayer organic substrate produced by the method for producing a multilayer organic substrate according to any one of claims 1 to 9.