CN111564496B - Semiconductor device and manufacturing method thereof - Google Patents
Semiconductor device and manufacturing method thereof Download PDFInfo
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- CN111564496B CN111564496B CN202010362746.2A CN202010362746A CN111564496B CN 111564496 B CN111564496 B CN 111564496B CN 202010362746 A CN202010362746 A CN 202010362746A CN 111564496 B CN111564496 B CN 111564496B
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 165
- 238000004519 manufacturing process Methods 0.000 title claims description 16
- 238000002955 isolation Methods 0.000 claims abstract description 140
- 239000000758 substrate Substances 0.000 claims abstract description 118
- 238000000034 method Methods 0.000 claims description 29
- 239000003989 dielectric material Substances 0.000 claims description 11
- 238000005530 etching Methods 0.000 claims description 10
- 239000000463 material Substances 0.000 description 13
- 230000008569 process Effects 0.000 description 10
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- 229910052710 silicon Inorganic materials 0.000 description 5
- 239000010703 silicon Substances 0.000 description 5
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 4
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- 229910052751 metal Inorganic materials 0.000 description 4
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- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 229910052814 silicon oxide Inorganic materials 0.000 description 3
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- 229910052732 germanium Inorganic materials 0.000 description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 2
- 229910000449 hafnium oxide Inorganic materials 0.000 description 2
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 description 2
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7838—Field effect transistors with field effect produced by an insulated gate without inversion channel, e.g. buried channel lateral MISFETs, normally-on lateral MISFETs, depletion-mode lateral MISFETs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0642—Isolation within the component, i.e. internal isolation
- H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/107—Substrate region of field-effect devices
- H01L29/1075—Substrate region of field-effect devices of field-effect transistors
- H01L29/1079—Substrate region of field-effect devices of field-effect transistors with insulated gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66553—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using inside spacers, permanent or not
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Abstract
The embodiment of the application discloses a semiconductor device, includes: the semiconductor device comprises a semiconductor substrate, wherein an active region, a drain region and a channel region which is connected with the source region and the drain region are formed in the semiconductor substrate; an isolation structure located within the semiconductor substrate; the isolation structure is shielded between the source region and the drain region so as to block a linear current path between the source region and the drain region; a gate structure at least over the channel region of the semiconductor substrate.
Description
Technical Field
The embodiment of the application relates to the field of semiconductor manufacturing, in particular to a semiconductor device and a manufacturing method thereof.
Background
In CMOS process, static leakage current IoffIs a very critical parameter that determines the size and power consumption of the chip. Currently, as the size of three-dimensional memory devices decreases, the static leakage current IoffBecomes more and more critical. Static leakage current IoffTypically consists of two components, reverse biased junction current and channel Drain Induced Barrier Lowering (DIBL) current. The reverse bias junction current is generally reduced by Lightly Doped Drain (LDD). The DIBL current reduction is typically achieved by reducing the source-drain junction depth and increasing the channel length (feature size).
However, in the high voltage circuit, the junction depth of the source and drain cannot be too shallow because of the requirement for high withstand voltage. Especially for depletion-type MOS transistors, the DIBL effect is more severe than that of enhancement-type MOS transistors, and therefore, a larger channel length is required to overcome the DIBL effect. Thus, the size of the three-dimensional memory device is increased.
Disclosure of Invention
In view of the above, embodiments of the present application provide a semiconductor device and a method for manufacturing the same to solve at least one problem in the prior art.
In order to achieve the above purpose, the technical solution of the embodiment of the present application is implemented as follows:
in a first aspect, an embodiment of the present application provides a semiconductor device, including:
the semiconductor device comprises a semiconductor substrate, wherein an active region, a drain region and a channel region which is connected with the source region and the drain region are formed in the semiconductor substrate;
an isolation structure located within the semiconductor substrate; the isolation structure is shielded between the source region and the drain region so as to block a linear current path between the source region and the drain region;
a gate structure at least over the channel region of the semiconductor substrate.
In an alternative embodiment, the channel region connects the source region on a side of the source region facing the isolation structure and the drain region on a side of the drain region facing the isolation structure.
In an alternative embodiment, the width of the channel region is greater than the width of the source region and the drain region in a first direction parallel to the surface direction of the semiconductor substrate; wherein the first direction is perpendicular to a line direction of the source region and the drain region.
In an alternative embodiment, the channel region surrounds the isolation structure.
In an alternative embodiment, the isolation structure comprises a plurality of separately arranged sub-isolation structures; two adjacent sub-isolation structures are at least partially overlapped along a second direction; wherein the second direction is a connecting line direction of the source region and the drain region.
In an alternative embodiment, the depth of the isolation structure is greater than the depth of the channel region in a thickness direction of the semiconductor substrate.
In an alternative embodiment, the isolation structure is formed by filling a trench in the semiconductor substrate with a dielectric material.
In a second aspect, embodiments of the present application provide a semiconductor device, including:
the semiconductor device comprises a semiconductor substrate, wherein an active region, a drain region and a channel region which is connected with the source region and the drain region are formed in the semiconductor substrate;
the channel region is of an annular structure, so that current between the source region and the drain region is transmitted along a non-linear path provided by the annular structure;
a gate structure at least over the channel region of the semiconductor substrate.
In an alternative embodiment, the source region and the drain region are connected to two opposite sides of the ring structure.
In an optional embodiment, the channel region is an annular structure, and specifically includes:
the cross section of the channel region in the direction parallel to the surface of the semiconductor substrate is annular, and the annular is symmetrical along the connecting line direction of the source region and the drain region.
In an alternative embodiment, the channel region includes a first portion and a second portion within the source and drain link regions, the first and second portions being separated by at least one isolation structure.
In an optional embodiment, the channel region further includes a third portion and a fourth portion protruding from a connection region between the source region and the drain region, and the third portion and the fourth portion respectively connect the first portion and the second portion at two opposite sides of the connection region.
In a third aspect, embodiments of the present application provide a method for manufacturing a semiconductor device, the method including:
providing a semiconductor substrate, and forming a source region, a drain region and a channel region connecting the source region and the drain region in the semiconductor substrate;
forming an isolation structure located in the semiconductor substrate, wherein the isolation structure is shielded between the source region and the drain region so as to block a linear current path between the source region and the drain region;
forming a gate structure at least over the channel region of the semiconductor substrate.
In an alternative embodiment, the channel region connects the source region on a side of the source region facing the isolation structure and the drain region on a side of the drain region facing the isolation structure.
In an alternative embodiment, the width of the channel region is greater than the width of the source region and the drain region in a first direction parallel to the surface direction of the semiconductor substrate; wherein the first direction is perpendicular to a line direction of the source region and the drain region.
In an alternative embodiment, the forming an isolation structure within the semiconductor substrate includes:
and forming the isolation structure in the channel region of the semiconductor substrate, wherein the formed isolation structure is surrounded by the channel region.
In an alternative embodiment, the forming an isolation structure within the semiconductor substrate includes:
forming a plurality of sub-isolation structures which are separately arranged in the semiconductor substrate; two adjacent sub-isolation structures are at least partially overlapped along a second direction; wherein the second direction is a connecting line direction of the source region and the drain region.
In an alternative embodiment, the etching depth of the isolation structure is greater than the depth of the channel region along the thickness direction of the semiconductor substrate.
In an alternative embodiment, the forming an isolation structure within the semiconductor substrate includes:
etching the semiconductor substrate, and forming a groove in the semiconductor substrate;
and filling a dielectric material in the groove to form the isolation structure.
The embodiment of the application provides a semiconductor device and a manufacturing method thereof, wherein the semiconductor device comprises: the semiconductor device comprises a semiconductor substrate, wherein an active region, a drain region and a channel region which is connected with the source region and the drain region are formed in the semiconductor substrate; an isolation structure located within the semiconductor substrate; the isolation structure is shielded between the source region and the drain region so as to block a linear current path between the source region and the drain region; a gate structure at least over the channel region of the semiconductor substrate. In the embodiment of the present application, an isolation structure is disposed in a semiconductor substrate, and the isolation structure is shielded between a source region and a drain region to block a linear current path between the source region and the drain region, so that a circuit path between the source region and the drain region is lengthened.
Drawings
Fig. 1 is a cross-sectional view of a semiconductor device provided in an embodiment of the present application;
fig. 2 is a top view of a semiconductor device provided in an embodiment of the present application;
FIG. 3 is a schematic diagram of one embodiment of an isolation structure provided in an embodiment of the present application;
FIG. 4 is a schematic diagram of another implementation of an isolation structure provided in an embodiment of the present application;
fig. 5 is a top view of a semiconductor device provided in an embodiment of the present application;
fig. 6 is a schematic flowchart of a method for manufacturing a semiconductor device according to an embodiment of the present application.
Detailed Description
Exemplary embodiments disclosed in the present application will be described in more detail below with reference to the accompanying drawings. While exemplary embodiments of the present application are shown in the drawings, it should be understood that the present application may be embodied in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.
In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present application. It will be apparent, however, to one skilled in the art, that the present application may be practiced without one or more of these specific details. In other instances, well-known features have not been described in order to avoid obscuring the present application; that is, not all features of an actual embodiment are described herein, and well-known functions and structures are not described in detail.
In the drawings, the size of layers, regions, elements, and relative sizes may be exaggerated for clarity. Like reference numerals refer to like elements throughout.
It will be understood that when an element or layer is referred to as being "on" … …, "adjacent to … …," "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to the other elements or layers or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on … …," "directly adjacent to … …," "directly connected to" or "directly coupled to" other elements or layers, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present application. And the discussion of a second element, component, region, layer or section does not imply that a first element, component, region, layer or section is necessarily present in the application.
Spatial relationship terms such as "under … …", "under … …", "below", "under … …", "above … …", "above", and the like, may be used herein for ease of description to describe the relationship of one element or feature to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, then elements or features described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary terms "below … …" and "below … …" can encompass both an orientation of up and down. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.
So that the manner in which the features and elements of the present embodiments can be understood in detail, a more particular description of the embodiments, briefly summarized above, may be had by reference to embodiments, some of which are illustrated in the appended drawings.
An embodiment of the present application provides a semiconductor device, and fig. 1 is a cross-sectional view of the semiconductor device provided in the embodiment of the present application, and as shown in fig. 1, the semiconductor device includes:
a semiconductor substrate 110, wherein an active region 111, a drain region 112 and a channel region 113 connecting the source region 111 and the drain region 112 are formed in the semiconductor substrate 110;
an isolation structure 120 located within the semiconductor substrate 110; the isolation structure 120 is shielded between the source region 111 and the drain region 112 to block a straight current path between the source region 111 and the drain region 112;
a gate structure 130 at least over the channel region 113 of the semiconductor substrate 110.
In the embodiment of the present application, the effective interval between the source region 111 and the drain region 112 is increased by disposing the isolation structure 120 between the source region 111 and the drain region 112, so that the effective channel length is increased without increasing the actual channel length.
In the embodiment of the present application, the source region 111, the drain region 112, and the channel region 113 constitute an active region, and the semiconductor device further includes: shallow Trench Isolation (STI) structures 140, the STI structures 140 surrounding the active area and isolating the active area from neighboring active areas.
In the embodiment of the present application, the semiconductor substrate 110 may be an elemental semiconductor material substrate (e.g., a silicon (Si) substrate, a germanium (Ge) substrate, etc.), a composite semiconductor material substrate (e.g., a silicon germanium (SiGe) substrate, etc.), or a silicon-on-insulator (SOI) substrate, a germanium-on-insulator (GeOI) substrate, etc.
The gate structure 130 includes a gate dielectric layer and a gate electrode layer on the gate dielectric layer, and the gate dielectric layer is made of at least one of the following materials: silicon oxide, silicon oxynitride, high dielectric constant material. Wherein the high dielectric constant material may be hafnium oxide. The gate electrode layer is made of conductive materials such as metal, polycrystalline silicon or metal silicide materials.
In the embodiment of the present application, the isolation structure 120 is formed by filling a dielectric material in a trench in the semiconductor substrate 110.
In the embodiment of the present application, the isolation structure 120 may be a shallow trench isolation structure STI; in some embodiments, the isolation structure 120 may also be other isolation structures, such as a Local Oxidation of Silicon (LOCOS) structure.
In this embodiment, the isolation structure 120 may be formed by a shallow trench isolation process, which specifically includes: and etching the semiconductor substrate 110, forming a trench in the semiconductor substrate 110, and filling a dielectric material in the trench to form the isolation structure 120. Wherein the dielectric material may be an insulating dielectric material. In some embodiments, other processes may be used to form the isolation structure 120, such as a local silicon oxide isolation process. It should be noted that the method for forming the trench may use an etching process. In some embodiments, the etching process may be wet etching or dry etching. Wherein, the wet etching mainly utilizes chemical reagents to perform chemical reaction with the etched material for etching; dry etching mainly utilizes reactive gases and plasma for etching. And the groove is filled with the dielectric material by adopting a deposition process. In some embodiments, the Deposition process may include Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), Plasma-Enhanced CVD (PECVD), sputtering (sputtering), Metal-Organic Chemical Vapor Deposition (MOCVD), or Atomic Layer Deposition (ALD).
In the present embodiment, an isolation structure 120 is formed within the semiconductor substrate 110. The cross-sectional shape of the isolation structure 120 in the thickness direction of the semiconductor substrate may be various regular or irregular patterns. In the semiconductor device shown in fig. 1, the cross-sectional shape of the isolation structure 120 is a trapezoid with a wide top and a narrow bottom. The Z-axis direction in fig. 1 is the thickness direction of the semiconductor substrate.
Fig. 2 is a top view of a semiconductor device according to an embodiment of the present disclosure, and as shown in fig. 2, in the embodiment of the present disclosure, the channel region 113 is connected to the source region 111 on a side of the source region 111 facing the isolation structure 120, and is connected to the drain region 112 on a side of the drain region 112 facing the isolation structure 120.
In the embodiment of the present application, the width of the channel region 113 is greater than the widths of the source region 111 and the drain region 112 along a first direction parallel to the surface direction of the semiconductor substrate 110; wherein the first direction is perpendicular to a connection line direction of the source region 111 and the drain region 112. The Y-axis direction in fig. 2 is the first direction; the X-axis direction in fig. 2 is a direction (or a second direction) along which the source region 111 and the drain region 112 are connected.
In the embodiment of the present application, as shown in fig. 2, the channel region 113 surrounds the isolation structure 120. The inner annular sidewall of the channel region 113 is in contact with the outer sidewall of the isolation structure 120. The channel region 113 is located between the source region 111 and the drain region 112; the outer ring sidewall of the channel region 113 contacts sidewalls of the source region 111 and the drain region 112, respectively.
In the embodiment of the present application, the shape of the orthographic projection of the isolation structure 120 on the semiconductor substrate 110 includes: rectangular, circular, oval, polygonal.
In the embodiment of the present application, as shown in fig. 1, the depth of the isolation structure is greater than the depth of the channel region in the thickness direction of the semiconductor substrate. So that the current between the source region 111 and the drain region 112 flows through the side of the isolation structure 120 at the surface of the channel region 113, but does not flow through the channel region under the isolation structure 120. In a specific application, the depth of the isolation structure 120 is the same as the depth of a shallow trench isolation structure used for isolating an active region in the semiconductor device. The depth of the isolation structure 120 is greater than the depth of the source region 111 and the drain region 112.
It should be noted that, a dashed line in the channel region 113 in fig. 2 is used to indicate a current path between the source region 111 and the drain region 112, as shown in fig. 2, in the semiconductor device provided in this embodiment of the present application, since the isolation structure 120 is spaced between the source region 111 and the drain region 112, the isolation structure 120 blocks a straight current path between the source region 111 and the drain region 112, so that the current path between the source region 111 and the drain region 112 is annular.
In the embodiment of the present application, the isolation structure 120 includes a plurality of sub-isolation structures separately disposed; two adjacent sub-isolation structures are at least partially overlapped along a second direction; wherein the second direction is a connection line direction of the source region 111 and the drain region 112.
Fig. 3 is a schematic diagram of an implementation manner of an isolation structure provided in an embodiment of the present application, and fig. 4 is a schematic diagram of another implementation manner of the isolation structure provided in the embodiment of the present application, it should be noted that fig. 3 illustrates that the isolation structure includes 3 sub-isolation structures, and fig. 4 illustrates that the isolation structure includes 6 sub-isolation structures. As shown in fig. 3, the isolation structure 320 includes 3 sub-isolation structures 321, 322, and 323 separately disposed, and two adjacent sub-isolation structures at least partially overlap in the second direction. It should be noted that the orthographic projection of the 3 sub-isolation structures 321, 322 and 323 on the semiconductor substrate in fig. 3 is rectangular.
As shown in fig. 4, the isolation structure 420 includes 6 sub-isolation structures 421, 422, 423, 424, 425, and 426, which are separately disposed, and the 6 sub-isolation structures 421, 422, 423, 424, 425, and 426 are overlapped two by two along the second direction. Since the sub-isolation structures shown in fig. 4 overlap each other along the second direction by a small distance, the current between the source 411 and the drain 412 can be transmitted along the periphery of the sub-isolation structures, and also along the overlapping portions of the sub-isolation structures 421, 422, 423, 424, 425, and 426, and the dotted line in fig. 4 can be regarded as the current transmission path between the source 411 and the drain 412.
An embodiment of the present application provides a semiconductor device, including: the semiconductor device comprises a semiconductor substrate, wherein an active region, a drain region and a channel region which is connected with the source region and the drain region are formed in the semiconductor substrate; an isolation structure located within the semiconductor substrate; the isolation structure is shielded between the source region and the drain region so as to block a linear current path between the source region and the drain region; a gate structure at least over the channel region of the semiconductor substrate. According to the embodiment of the application, the isolation structure is arranged in the semiconductor substrate and is shielded between the source region and the drain region to block a linear current path between the source region and the drain region, so that a circuit path between the source region and the drain region is lengthened, the effective channel length is increased by changing the current path between the source region and the drain region, namely the DIBL current is reduced on the premise of not increasing the actual channel length.
An embodiment of the present application further provides a semiconductor device, and fig. 5 is a top view of the semiconductor device provided in the embodiment of the present application, and as shown in fig. 5, the semiconductor device includes:
the semiconductor device comprises a semiconductor substrate, wherein an active region 511, a drain region 512 and a channel region 513 connected with the source region 511 and the drain region 512 are formed in the semiconductor substrate;
the channel region 513 is a ring structure, so that the current between the source region 511 and the drain region 512 is transmitted along a non-linear path provided by the ring structure;
a gate structure 520 at least over the channel region 513 of the semiconductor substrate.
In the embodiment of the present application, the source region 511, the drain region 512, and the channel region 513 connecting the source region 511 and the drain region 512 constitute an active region, and the semiconductor device further includes: and the shallow trench isolation structure 540 is positioned at the outer side of the active region and surrounds the active region.
It should be understood that the channel region is a ring-shaped structure in this embodiment, which can be implemented by forming a non-ring-shaped channel region in the semiconductor substrate, and then providing an isolation structure in the channel region to change the channel region into a ring shape; the method can also be implemented by directly forming an annular channel region in the semiconductor substrate, specifically, for example, performing ion implantation in an annular region of the semiconductor substrate to form an annular channel region; or by other possible implementations in the art.
As shown in fig. 5, in the embodiment of the present application, the source region 511 and the drain region 512 are respectively connected to two opposite sides of the ring structure.
In this embodiment, the channel region 513 has an annular structure, which specifically includes: the cross-sectional shape of the channel region 513 in a direction parallel to the surface of the semiconductor substrate 510 is a ring shape, and the ring shape is symmetrical along a line connecting the source region 511 and the drain region 512. The X-axis direction in fig. 5 is a direction of a connection line between the source region 511 and the drain region 512.
As shown in fig. 5, in the embodiment of the present application, the channel region 513 includes a first portion 5131 and a second portion 5132 located in a connection region between the source region 511 and the drain region 512, and the first portion 5131 and the second portion 5132 are spaced apart by at least one isolation structure 530.
In the present embodiment, the at least one isolation structure 530 includes a plurality of sub-isolation structures separately disposed; two adjacent sub-isolation structures at least partially overlap along a connecting line direction of the source region 511 and the drain region 512.
Note that, an outer ring of an orthographic shape of the ring-shaped structure on the semiconductor substrate 110 is a rectangle, and an inner ring of the orthographic shape of the ring-shaped structure on the semiconductor substrate 510 can be adjusted according to the shape of the isolation structure 530. Wherein the shape of the orthographic projection of the isolation structure 530 on the semiconductor substrate 510 comprises: rectangular, circular, oval, polygonal.
As shown in fig. 5, in the embodiment of the present application, the channel region 513 further includes a third portion 5133 and a fourth portion 5134 protruding from a connection region between the source region 511 and the drain region 512, and the third portion 5133 and the fourth portion 5134 respectively connect the first portion 5131 and the second portion 5132 at two opposite sides of the connection region. The channel region thus provides a non-linear path for current flow between the source and drain regions. It should be noted that the shape of the first portion 5131 and the second portion 5132 may be any shape connecting the source region 511 and the drain region 512, and in the embodiment of the present application, only the shape of the first portion 5131 and the second portion 5132 is illustrated as a rectangle.
The embodiment of the application provides a semiconductor device and a manufacturing method thereof, wherein the semiconductor device comprises: the semiconductor device comprises a semiconductor substrate, wherein an active region, a drain region and a channel region which is connected with the source region and the drain region are formed in the semiconductor substrate; the channel region is of an annular structure, so that current between the source region and the drain region is transmitted along a non-linear path provided by the annular structure; a gate structure at least over the channel region of the semiconductor substrate. In the embodiments of the present application, the channel region is set to be an annular structure, so that the current between the source region and the drain region is transmitted along the non-linear path provided by the annular structure, thereby lengthening the circuit path between the source region and the drain region.
An embodiment of the present application provides a method for manufacturing a semiconductor device, and fig. 6 is a schematic flow chart of the method for manufacturing a semiconductor device provided in the embodiment of the present application, and the method mainly includes the following steps:
In the embodiments of the present application, a semiconductor substrate is provided, and the semiconductor substrate may be an elemental semiconductor material substrate (e.g., a silicon (Si) substrate, a germanium (Ge) substrate, etc.), a composite semiconductor material substrate (e.g., a silicon germanium (SiGe) substrate, etc.), or a silicon-on-insulator (SOI) substrate, a germanium-on-insulator (GeOI) substrate, etc.
In the embodiment of the present application, a plurality of shallow trench isolation structures are formed in the semiconductor substrate, the shallow trench isolation structures define a plurality of active regions, and a source region, a drain region, and a channel region connecting the source region and the drain region are formed in each of the active regions. The width of the channel region is larger than the width of the source region and the width of the drain region along a first direction parallel to the surface direction of the semiconductor substrate; wherein the first direction is perpendicular to a line direction of the source region and the drain region.
In the embodiment of the application, the semiconductor substrate is etched, and a groove is formed in the semiconductor substrate; and filling a dielectric material in the groove to form the isolation structure, wherein the isolation structure is shielded between the source region and the drain region to block a linear current path between the source region and the drain region.
In an embodiment of the present application, the channel region is connected to the source region at a side of the source region facing the isolation structure, and is connected to the drain region at a side of the drain region facing the isolation structure.
In some embodiments, the isolation structure may include a plurality of sub-isolation structures separately disposed, such that the process of forming the isolation structure is: forming a plurality of sub-isolation structures which are separately arranged in the semiconductor substrate; two adjacent sub-isolation structures are at least partially overlapped along a second direction; wherein the second direction is a connecting line direction of the source region and the drain region.
In the embodiment of the present application, the isolation structure is formed in the channel region of the semiconductor substrate, and the formed isolation structure is surrounded by the channel region. The inner ring side wall of the channel region is in contact with the outer side wall of the isolation structure. The channel region is positioned between the source region and the drain region; and the outer ring side wall of the channel region is respectively contacted with the side walls of the source region and the drain region.
In the embodiment of the application, the etching depth of the isolation structure is greater than the depth of the channel region along the thickness direction of the semiconductor substrate. So that current between the source region and the drain region flows at the surface of the channel region through the side of the isolation structure without flowing from the channel region under the isolation structure. In a specific application, the depth of the isolation structure is the same as the depth of a shallow trench isolation structure used for isolating the active region in the semiconductor device. The depth of the isolation structure is greater than the depth of the source region and the drain region.
In the embodiment of the present application, a gate structure is formed on the channel region, the source region and the drain region are located at two sides of the gate structure, and the gate structure intersects with the corresponding active region and extends to intersect with the shallow trench isolation structure.
The gate structure comprises a gate dielectric layer and a gate electrode layer positioned on the gate dielectric layer, wherein the gate dielectric layer is made of at least one of the following materials: silicon oxide, silicon oxynitride, high dielectric constant material. Wherein the high dielectric constant material may be hafnium oxide. The gate electrode layer is made of conductive materials such as metal, polycrystalline silicon or metal silicide materials.
It should be noted that, since the method embodiments provided in the embodiments of the present application correspond to the apparatus embodiments one to one, the method embodiments are not described herein again.
It should be appreciated that reference throughout this specification to "one embodiment" or "an embodiment" means that a particular feature, structure or characteristic described in connection with the embodiment is included in at least one embodiment of the present application. Thus, the appearances of the phrases "in one embodiment" or "in an embodiment" in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. It should be understood that, in the various embodiments of the present application, the sequence numbers of the above-mentioned processes do not mean the execution sequence, and the execution sequence of each process should be determined by its function and inherent logic, and should not constitute any limitation to the implementation process of the embodiments of the present application. The above-mentioned serial numbers of the embodiments of the present application are merely for description and do not represent the merits of the embodiments.
The methods disclosed in the several method embodiments provided in the present application may be combined arbitrarily without conflict to obtain new method embodiments.
Features disclosed in several of the product embodiments provided in the present application may be combined in any combination to yield new product embodiments without conflict.
The features disclosed in the several method or apparatus embodiments provided in the present application may be combined arbitrarily, without conflict, to arrive at new method embodiments or apparatus embodiments.
In the embodiments provided in the present application, it should be understood that the disclosed apparatus may be implemented in other manners. The above description is only for the specific embodiments of the present application, but the scope of the present application is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present application, and shall be covered by the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.
Claims (15)
1. A semiconductor device, comprising:
the semiconductor device comprises a semiconductor substrate, wherein an active region, a drain region and a channel region which is connected with the source region and the drain region are formed in the semiconductor substrate;
an isolation structure located within the semiconductor substrate; the isolation structure is shielded between the source region and the drain region so as to block a linear current path between the source region and the drain region; the isolation structure is formed by filling a dielectric material in a groove in the semiconductor substrate; the depth of the isolation structure is larger than that of the channel region along the thickness direction of the semiconductor substrate;
a gate structure at least over the channel region of the semiconductor substrate.
2. The semiconductor device according to claim 1,
the channel region is connected with the source region on the side of the source region facing the isolation structure, and is connected with the drain region on the side of the drain region facing the isolation structure.
3. The semiconductor device according to claim 1 or 2,
the width of the channel region is larger than the width of the source region and the width of the drain region along a first direction parallel to the surface direction of the semiconductor substrate; wherein the first direction is perpendicular to a line direction of the source region and the drain region.
4. The semiconductor device according to claim 1,
the channel region surrounds the isolation structure.
5. The semiconductor device according to claim 1,
the isolation structure comprises a plurality of sub-isolation structures which are separately arranged; two adjacent sub-isolation structures are at least partially overlapped along a second direction; wherein the second direction is a connecting line direction of the source region and the drain region.
6. A semiconductor device, comprising:
the semiconductor device comprises a semiconductor substrate, wherein an active region, a drain region and a channel region which is connected with the source region and the drain region are formed in the semiconductor substrate;
enabling the channel region to be an annular structure by arranging an isolation structure in the channel region, so that current between the source region and the drain region is transmitted along a non-linear path provided by the annular structure; the isolation structure is formed by filling a dielectric material in a groove in the semiconductor substrate; the depth of the isolation structure is larger than that of the channel region along the thickness direction of the semiconductor substrate;
a gate structure at least over the channel region of the semiconductor substrate.
7. The semiconductor device according to claim 6,
the source region and the drain region are respectively connected to two opposite sides of the annular structure.
8. The semiconductor device according to claim 6, wherein the channel region is a ring structure, and specifically comprises:
the cross section of the channel region in the direction parallel to the surface of the semiconductor substrate is annular, and the annular is symmetrical along the connecting line direction of the source region and the drain region.
9. The semiconductor device according to claim 6,
the channel region comprises a first part and a second part which are positioned in the connecting region of the source region and the drain region, and the first part and the second part are separated by at least one isolation structure.
10. The semiconductor device according to claim 9,
the channel region further comprises a third portion and a fourth portion protruding from a wiring region of the source region and the drain region, and the third portion and the fourth portion are respectively connected with the first portion and the second portion at two opposite sides of the wiring region.
11. A method of manufacturing a semiconductor device, the method comprising:
providing a semiconductor substrate, and forming a source region, a drain region and a channel region connecting the source region and the drain region in the semiconductor substrate;
etching the semiconductor substrate, and forming a groove in the semiconductor substrate;
filling a dielectric material in the groove to form an isolation structure positioned in the semiconductor substrate, wherein the isolation structure is shielded between the source region and the drain region to block a linear current path between the source region and the drain region; along the thickness direction of the semiconductor substrate, the etching depth of the isolation structure is greater than the depth of the channel region;
forming a gate structure at least over the channel region of the semiconductor substrate.
12. The method for manufacturing a semiconductor device according to claim 11,
the channel region is connected with the source region on the side of the source region facing the isolation structure, and is connected with the drain region on the side of the drain region facing the isolation structure.
13. The method for manufacturing a semiconductor device according to claim 11 or 12,
the width of the channel region is larger than the width of the source region and the width of the drain region along a first direction parallel to the surface direction of the semiconductor substrate; wherein the first direction is perpendicular to a line direction of the source region and the drain region.
14. The method of manufacturing a semiconductor device according to claim 11, wherein the forming an isolation structure in the semiconductor substrate comprises:
and forming the isolation structure in the channel region of the semiconductor substrate, wherein the formed isolation structure is surrounded by the channel region.
15. The method of manufacturing a semiconductor device according to claim 11, wherein the forming an isolation structure in the semiconductor substrate comprises:
forming a plurality of sub-isolation structures which are separately arranged in the semiconductor substrate; two adjacent sub-isolation structures are at least partially overlapped along a second direction; wherein the second direction is a connecting line direction of the source region and the drain region.
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60175458A (en) * | 1984-02-21 | 1985-09-09 | Toshiba Corp | Semiconductor device and manufacture thereof |
| US5814834A (en) * | 1995-12-04 | 1998-09-29 | Semiconductor Energy Laboratory Co. | Thin film semiconductor device |
| US5841170A (en) * | 1996-04-25 | 1998-11-24 | Sharp Kabushiki Kaisha | Field effect transistor and CMOS element having dopant exponentially graded in channel |
| US7339235B1 (en) * | 1996-09-18 | 2008-03-04 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device having SOI structure and manufacturing method thereof |
| CN105448725A (en) * | 2014-08-26 | 2016-03-30 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and forming method thereof |
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| KR102272382B1 (en) * | 2014-11-21 | 2021-07-05 | 삼성전자주식회사 | Semiconductor device |
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Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60175458A (en) * | 1984-02-21 | 1985-09-09 | Toshiba Corp | Semiconductor device and manufacture thereof |
| US5814834A (en) * | 1995-12-04 | 1998-09-29 | Semiconductor Energy Laboratory Co. | Thin film semiconductor device |
| US5841170A (en) * | 1996-04-25 | 1998-11-24 | Sharp Kabushiki Kaisha | Field effect transistor and CMOS element having dopant exponentially graded in channel |
| US7339235B1 (en) * | 1996-09-18 | 2008-03-04 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device having SOI structure and manufacturing method thereof |
| CN105448725A (en) * | 2014-08-26 | 2016-03-30 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and forming method thereof |
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