CN111564134A - Data voltage polarity control method, module and display device - Google Patents
Data voltage polarity control method, module and display device Download PDFInfo
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- CN111564134A CN111564134A CN202010534988.5A CN202010534988A CN111564134A CN 111564134 A CN111564134 A CN 111564134A CN 202010534988 A CN202010534988 A CN 202010534988A CN 111564134 A CN111564134 A CN 111564134A
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3614—Control of polarity reversal in general
Abstract
The invention provides a data voltage polarity control method, a data voltage polarity control module and a display device. The data voltage polarity control method includes: in the KXN frame picture display time, the grid drive circuit does not output a grid drive signal and controls the polarity inversion of data voltage accessed by a part of row pixel circuits in the multi-row and multi-column pixel circuits; controlling the polarity inversion of data voltages accessed by other pixel circuits except for part of the pixel circuits in the rows and columns of the pixel circuits at the KxN +1 frame picture display time, and controlling and adjusting the duty ratio of a gate driving signal output by the gate driving circuit to be a preset duty ratio; controlling the polarity inversion of data voltage accessed by a plurality of rows and a plurality of columns of pixel circuits in the KxN +2 frame picture display time; k is an integer greater than 2 and N is an integer greater than 1. The invention can realize polarity control signal inversion to improve afterimage and improve flicker phenomenon during polarity control signal inversion.
Description
Technical Field
The invention relates to the technical field of display, in particular to a data voltage polarity control method, a data voltage polarity control module and a display device.
Background
In the prior art, a display product is easy to cause picture jitter under a front-end weak signal condition, so that some pixel areas are always in a positive and negative Polarity asymmetric state, and thus an afterimage is formed. This flickering phenomenon is unacceptable to the customer,
the POL flipping refers to: controlling the POL signal to be inverted every preset time, namely, controlling the polarity of data voltage accessed by each pixel circuit in the display panel to be opposite in the display time of a first frame picture to the display time of a Kth frame picture and in the display time of an adjacent frame picture; the POL signal is turned over from the display time of the display picture of the (M + 1) th frame to the display time of the picture of the 2M th frame; and in the display time of the M +1 th frame image, the polarity of the data voltage accessed by each pixel circuit is the same as that of the data voltage accessed by each pixel circuit in the display time of the M +1 th frame image. The predetermined time may be 14 seconds or 28 seconds, and M is an integer greater than 1. However, as shown in fig. 1, when the POL signal inversion is implemented, since the polarity of the data voltage connected to each pixel circuit is the same as the polarity of the data voltage connected to each pixel circuit at the M +1 th frame picture display time TM +1, the voltage charged by the pixel circuits changes in the same direction, and a full-screen flicker phenomenon occurs. In fig. 1, a POL signal is denoted by P1, a data voltage on a data line included in the display panel (the pixel circuit is charged by the data voltage on the data line under the control of the gate driving signal) is denoted by D0, and a voltage charged for the pixel circuit is denoted by S0. As can be seen from fig. 1, at the M +1 th frame display time TM +1, the voltage charged in the pixel circuit becomes large, which results in an increase in luminance and a flicker phenomenon.
Disclosure of Invention
The invention mainly aims to provide a data voltage polarity control method, a data voltage polarity control module and a display device, and solves the problem of flicker phenomenon in the prior art when a control polarity control signal is turned over.
In order to achieve the above object, the present invention provides a data voltage polarity control method applied to a display panel, the display panel including a gate driving circuit and a plurality of rows and columns of pixel circuits, the data voltage polarity control method including:
in the KxN frame picture display time, the grid drive circuit does not output a grid drive signal and controls the polarity inversion of data voltage accessed by a part of row pixel circuits in the plurality of rows and columns of pixel circuits;
controlling the polarity inversion of data voltages accessed by other pixel circuits except for the partial column pixel circuits in the multiple rows and multiple columns of pixel circuits at the KxN +1 frame picture display time, and controlling and adjusting the duty ratio of a gate driving signal output by the gate driving circuit to be a preset duty ratio;
controlling the polarity inversion of the data voltage accessed by the pixel circuits in multiple rows and multiple columns at the KxN +2 frame picture display time;
k is an integer greater than 2 and N is an integer greater than 1.
Optionally, the partial column pixel circuits are a 4a-1 th column pixel circuit and a 4a th column pixel circuit; or the partial column pixel circuits are the 4a-2 th column pixel circuit and the 4a-3 th column pixel circuit; a is a positive integer.
Optionally, the partial column of pixel circuits are odd column of pixel circuits; or, the partial column pixel circuit is an even column pixel circuit.
Optionally, the display panel is a 75-inch 8K display panel, and the predetermined duty cycle is 1/4; alternatively, the first and second electrodes may be,
the display panel is a 65-inch 8K display panel, and the predetermined duty cycle is 0.35.
Optionally, the data voltage polarity control method includes:
and in other frame picture time except the KxN frame picture display time, the KxN +1 frame picture display time and the KxN +2 frame picture display time included in the display phase, the polarity of the data voltage accessed by the multi-row and multi-column pixel circuits is reversed.
The invention also provides a data voltage polarity control module, which is applied to a display panel, the display panel comprises a grid drive circuit and a plurality of rows and columns of pixel circuits, the data voltage polarity control module comprises a grid drive control unit and a data voltage polarity control unit, wherein,
the grid drive control unit is used for controlling the grid drive circuit not to output a grid drive signal at the KxN frame picture display time and controlling and adjusting the duty ratio of the grid drive signal output by the grid drive circuit to be a preset duty ratio at the KxN +1 frame picture display time;
the data voltage polarity control unit is used for controlling polarity inversion of data voltages accessed by a part of pixel circuits in the rows and columns of pixel circuits at the KxN frame picture display time, controlling polarity inversion of data voltages accessed by other pixel circuits except the part of pixel circuits in the rows and columns of pixel circuits at the KxN +1 frame picture display time, and controlling polarity inversion of the data voltages accessed by the rows and columns of pixel circuits at the KxN +2 frame picture display time;
k is an integer greater than 2 and N is an integer greater than 1.
Optionally, the partial column pixel circuits are a 4a-1 th column pixel circuit and a 4a th column pixel circuit; or the partial column pixel circuits are the 4a-2 th column pixel circuit and the 4a-3 th column pixel circuit; a is a positive integer.
Optionally, the partial column of pixel circuits are odd column of pixel circuits; or, the partial column pixel circuit is an even column pixel circuit.
Optionally, the display panel is a 75-inch 8K display panel, and the predetermined duty cycle is 1/4; alternatively, the first and second electrodes may be,
the display panel is a 65-inch 8K display panel, and the predetermined duty cycle is 0.35.
The invention also provides a display device which comprises the data voltage polarity control module.
Compared with the prior art, the data voltage Polarity control method, the data voltage Polarity control module and the display device can realize POL (Polarity control signal) signal inversion to improve afterimage and improve flicker phenomenon during POL signal inversion.
Drawings
FIG. 1 is a waveform diagram of a voltage charged by a pixel circuit when a POL signal is inverted in the prior art;
FIG. 2 is a flow chart of a data voltage polarity control method according to an embodiment of the present invention;
FIG. 3 is a schematic diagram showing the polarity of each pixel circuit in the display panel at the display time of the N-1 th frame;
FIG. 4 is a schematic diagram showing the polarity of each pixel circuit in the display panel at the display time of the Nth frame;
FIG. 5 is a schematic diagram showing the polarity of each pixel circuit in the display panel at the display time of the (N + 1) th frame;
FIG. 6 is a schematic diagram showing the polarity of each pixel circuit in the display panel at the display time of the (N + 2) th frame;
fig. 7 is a block diagram of a data voltage polarity control module according to an embodiment of the present invention;
fig. 8 is a waveform diagram of the luminance L0 at a predetermined point on the display panel when the polarity control signal P1 is inverted after the data voltage polarity control module according to the embodiment of the present invention is used.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The transistors used in all embodiments of the present invention may be transistors, thin film transistors, or field effect transistors or other devices with the same characteristics. In the embodiment of the present invention, in order to distinguish two poles of the transistor except the control pole, one pole is called a first pole, and the other pole is called a second pole.
In practical operation, when the transistor is a triode, the control electrode may be a base electrode, the first electrode may be a collector electrode, and the second electrode may be an emitter electrode; alternatively, the control electrode may be a base electrode, the first electrode may be an emitter electrode, and the second electrode may be a collector electrode.
In practical operation, when the transistor is a thin film transistor or a field effect transistor, the control electrode may be a gate electrode, the first electrode may be a drain electrode, and the second electrode may be a source electrode; alternatively, the control electrode may be a gate electrode, the first electrode may be a source electrode, and the second electrode may be a drain electrode.
The data voltage polarity control method according to the embodiment of the present invention is applied to a display panel, the display panel includes a gate driving circuit and a plurality of rows and columns of pixel circuits, as shown in fig. 2, the data voltage polarity control method includes:
s1, at the KxN frame picture display time, the grid drive circuit does not output grid drive signals and controls the polarity inversion of the data voltage accessed by partial row pixel circuits in the multi-row and multi-column pixel circuits;
s2: controlling the polarity inversion of data voltages accessed by other pixel circuits except for the partial column pixel circuits in the multiple rows and multiple columns of pixel circuits at the KxN +1 frame picture display time, and controlling and adjusting the duty ratio of a gate driving signal output by the gate driving circuit to be a preset duty ratio;
s3: controlling the polarity inversion of the data voltage accessed by the pixel circuits in multiple rows and multiple columns at the KxN +2 frame picture display time;
k is an integer greater than 2 and N is an integer greater than 1.
In the embodiment of the present invention, the polarity inversion of the data voltage refers to: the polarity of the data voltage is inverted from a positive polarity to a negative polarity, or the polarity of the data voltage is inverted from a negative polarity to a positive polarity.
In the data voltage polarity control method according to the embodiment of the present invention, a K × N frame display time and a K × N +1 frame display time are set between a K × N-1 frame display time and a K × N +2 frame display time, and at the K × N frame display time, the gate driving circuit does not output a gate driving signal, and each pixel circuit in the display panel still emits light according to display data in the K × N-1 frame display time, since no data voltage is charged to the pixel circuit at the K × N frame display time, a voltage of a gate of a driving transistor in the pixel circuit is not maintained and thus an emission luminance is reduced, and at the K × N +1 frame display time, a duty ratio of a gate driving signal output by the gate driving circuit is controlled to be adjusted to a predetermined duty ratio, the charging time of the pixel circuits is adjusted, and the light emitting brightness of each pixel circuit is correspondingly adjusted; and, at the time of displaying the screen of the KxN frame, the Polarity inversion of the data voltage accessed by some pixel circuits in the pixel circuits of the rows and columns is controlled, at the time of displaying the screen of the KxN +1 frame, the Polarity inversion of the data voltage accessed by other pixel circuits except the pixel circuits of the rows and columns is controlled, so that the data voltage accessed by the pixel circuits of the rows and columns is kept unchanged after the transition between the time of displaying the screen of the KxN frame and the time of displaying the screen of the KxN +1 frame, and the POLITY control signal inversion is realized to improve the residual image and improve the flicker phenomenon when the POL signal is inverted.
In specific implementation, during the display time of a KxN +1 frame, controlling and adjusting the duty ratio of a gate driving signal output by the gate driving circuit to be a preset duty ratio so as to adjust the charging time of the pixel circuit and correspondingly adjust the light emitting brightness of each pixel circuit; at this time, the setting of the predetermined duty ratio may be selected according to actual conditions; when the brightness is greatly reduced in the display time of the K multiplied by N frame picture, the grid line opening time can be improved by setting the preset duty ratio; when the luminance decrease is small at the time of display of the K × N frame picture, the gate line on time can be made to decrease by setting the predetermined duty ratio.
For example, when a data writing transistor (a gate of which is electrically connected to a corresponding row gate line) in a pixel circuit is an n-type transistor, the data writing transistor is turned on to charge the pixel circuit by a corresponding data voltage when a potential of a gate driving signal is a high voltage; when the electric potential of the grid driving signal is low voltage, the data writing transistor is turned off;
when a data writing transistor (a grid electrode of the data writing transistor is electrically connected with a corresponding row grid line) in a pixel circuit is a p-type transistor, when the potential of a grid driving signal is low voltage, the data writing transistor is turned on to charge the pixel circuit through a corresponding data voltage; when the potential of the gate driving signal is a high voltage, the data writing transistor is turned off.
Optionally, the display panel is a 75-inch 8K display panel, and the predetermined duty cycle is 1/4; alternatively, the first and second electrodes may be,
the display panel is a 65-inch 8K display panel, and the predetermined duty ratio is 0.35
In a specific implementation, when the display panel is a 75-inch 8K display panel and the data writing transistor in the pixel circuit in the display panel is an n-type transistor, the predetermined duty cycle may be 1/4, but is not limited thereto;
when the display panel is a 65-inch 8K display panel and the data writing transistor in the pixel circuit is an n-type transistor, the predetermined duty ratio may be 0.35, but is not limited thereto.
For example, when the display panel is a 75-inch 8K display panel and the data writing transistor in the pixel circuit is an n-type transistor, in a display period, the time when the potential of the gate driving signal is high voltage is 2.5H, and the time when the potential of the gate driving signal is low voltage is 7.5H, but not limited thereto; 1H may be equal to 3.7us, but is not limited thereto.
When the display panel is a 65-inch 8K display panel and the data writing transistor in the pixel circuit is an n-type transistor, the time period during which the potential of the gate driving signal is at the high voltage is 3.5H, and the time period during which the potential of the gate driving signal is at the low voltage is 6.5H in one display period, but not limited thereto.
Optionally, the partial column pixel circuits are a 4a-1 th column pixel circuit and a 4a th column pixel circuit; or the partial column pixel circuits are the 4a-2 th column pixel circuit and the 4a-3 th column pixel circuit; a is a positive integer.
Optionally, the partial column of pixel circuits are odd column of pixel circuits; or, the partial column pixel circuit is an even column pixel circuit.
In the above-mentioned method of only partially switching the polarity, in actual operation, there may be other polarity switching methods in the K × N +1 th frame screen display time and the K × N +1 th frame screen display time.
This is exemplified below by way of a polarity inversion.
At the display time of the frame N-1, the polarity of each pixel circuit in the display panel is as shown in FIG. 3; n is an integer greater than 1;
at the display time of the Nth frame of picture, the polarity of each pixel circuit in the display panel is as shown in FIG. 4;
at the display time of the (N + 1) th frame, the polarity of each pixel circuit in the display panel is as shown in fig. 5; n is an integer greater than 1;
the polarities of the respective pixel circuits in the display panel at the N +2 th frame screen display time are as shown in fig. 6.
In fig. 3, 4, 5 and 6, the nth row and mth column of the square blocks correspond to the nth row and mth column of the pixel circuits, n and m are positive integers, for example, in fig. 3, "+" in the first row and first column of the square blocks indicates that the data voltage accessed by the first row and first column of the pixel circuits is a positive polarity data voltage.
As can be seen from fig. 3 and 4, at the nth frame display time, the polarity of the data voltage supplied to the first column of pixel circuits, the polarity of the data voltage supplied to the second column of pixel circuits, the polarity of the data voltage supplied to the fifth column of pixel circuits, and the polarity of the data voltage supplied to the sixth column of pixel circuits are reversed;
as can be seen from fig. 3 and 4, in the nth frame screen display time, the polarity of the data voltage supplied to the third column pixel circuit, the polarity of the data voltage supplied to the fourth column pixel circuit, the polarity of the data voltage supplied to the seventh column pixel circuit, and the polarity of the data voltage supplied to the eighth column pixel circuit are not changed.
As can be seen from fig. 4 and 5, in the (N + 1) th frame display time, the polarity of the data voltage supplied to the pixel circuit in the third column, the polarity of the data voltage supplied to the pixel circuit in the fourth column, the polarity of the data voltage supplied to the pixel circuit in the seventh column, and the polarity of the data voltage supplied to the pixel circuit in the eighth column are reversed;
as can be seen from fig. 4 and 5, in the (N + 1) th frame display time, the polarity of the data voltage supplied to the first column pixel circuit, the polarity of the data voltage supplied to the second column pixel circuit, the polarity of the data voltage supplied to the fifth column pixel circuit, and the polarity of the data voltage supplied to the sixth column pixel circuit are reversed;
as shown in fig. 5 and 6, the polarity of the data voltage supplied to all the pixel circuits is inverted.
In an embodiment of the present invention, the data voltage polarity control method may further include:
and in other frame picture time except the KxN frame picture display time, the KxN +1 frame picture display time and the KxN +2 frame picture display time included in the display phase, the polarity of the data voltage accessed by the multi-row and multi-column pixel circuits is reversed.
In a specific implementation, in the other frame time except the K × N frame display time, the K × N +1 frame display time and the K × N +2 frame display time included in the display phase, the polarities of the data voltages accessed by the pixel circuits are opposite in the adjacent frame display time.
As shown in fig. 7, the data voltage polarity control module according to the embodiment of the present invention is applied to a display panel, the display panel includes a gate driving circuit 70 and a plurality of rows and columns of pixel circuits (not shown in fig. 7) that are connected to data voltages through corresponding data lines Dl, the data voltage polarity control module 80 includes a gate driving control unit 71 and a data voltage polarity control unit 72, wherein,
the gate driving control unit 71 is electrically connected to the gate driving circuit 70, and configured to control the gate driving circuit not to output a gate driving signal during a K × N frame image display time, and control and adjust a duty ratio of the gate driving signal output by the gate driving circuit to a predetermined duty ratio during a K × N +1 frame image display time;
the data voltage polarity control unit 72 is electrically connected to the data line Dl, and is configured to control polarity inversion of data voltages accessed by some of the rows and columns of pixel circuits in the rows and columns of pixel circuits at a K × N frame display time, control polarity inversion of data voltages accessed by other pixel circuits except the some of the rows and columns of pixel circuits in the rows and columns of pixel circuits at a K × N +1 frame display time, and control polarity inversion of data voltages accessed by the rows and columns of pixel circuits at a K × N +2 frame display time;
k is an integer greater than 2 and N is an integer greater than 1.
When the data voltage polarity control module according to the embodiment of the present invention operates, setting a K × N frame display time and a K × N +1 frame display time between a K × N-1 frame display time and a K × N +2 frame display time, wherein at the K × N frame display time, the gate driving circuit does not output a gate driving signal, and each pixel circuit in the display panel still emits light according to display data in the K × N-1 frame display time, because no data voltage is charged to the pixel circuit at the K × N frame display time, the voltage of the gate of the driving transistor in the pixel circuit is not maintained, and the emission brightness is reduced, and at the K × N +1 frame display time, controlling and adjusting the duty ratio of the gate driving signal output by the gate driving circuit to a predetermined duty ratio, the charging time of the pixel circuits is adjusted, and the light emitting brightness of each pixel circuit is correspondingly adjusted; and, at the time of displaying the screen of the KxN frame, the Polarity inversion of the data voltage accessed by some pixel circuits in the pixel circuits of the rows and columns is controlled, at the time of displaying the screen of the KxN +1 frame, the Polarity inversion of the data voltage accessed by other pixel circuits except the pixel circuits of the rows and columns is controlled, so that the data voltage accessed by the pixel circuits of the rows and columns is kept unchanged after the transition between the time of displaying the screen of the KxN frame and the time of displaying the screen of the KxN +1 frame, and the POLITY control signal inversion is realized to improve the residual image and improve the flicker phenomenon when the POL signal is inverted.
Optionally, the partial column pixel circuits are a 4a-1 th column pixel circuit and a 4a th column pixel circuit; or the partial column pixel circuits are the 4a-2 th column pixel circuit and the 4a-3 th column pixel circuit; a is a positive integer.
Optionally, the partial column of pixel circuits are odd column of pixel circuits; or, the partial column pixel circuit is an even column pixel circuit.
Optionally, the display panel is a 75-inch 8K display panel, and the predetermined duty cycle is 1/4; alternatively, the first and second electrodes may be,
the display panel is a 65-inch 8K display panel, and the predetermined duty cycle is 0.35.
Fig. 8 is a waveform diagram of the luminance L0 at a predetermined point on the display panel when the polarity control signal P1 is inverted after the data voltage polarity control module according to the embodiment of the present invention is used.
The display device according to the embodiment of the invention comprises the data voltage polarity control module.
The display device provided by the embodiment of the invention can be any product or component with a display function, such as a mobile phone, a tablet personal computer, a television, a display, a notebook computer, a digital photo frame, a navigator and the like.
While the foregoing is directed to the preferred embodiment of the present invention, it will be understood by those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention as defined in the appended claims.
Claims (10)
1. A data voltage polarity control method is applied to a display panel, the display panel comprises a grid driving circuit and a plurality of rows and columns of pixel circuits, and the data voltage polarity control method is characterized by comprising the following steps:
in the KxN frame picture display time, the grid drive circuit does not output a grid drive signal and controls the polarity inversion of data voltage accessed by a part of row pixel circuits in the plurality of rows and columns of pixel circuits;
controlling the polarity inversion of data voltages accessed by other pixel circuits except for the partial column pixel circuits in the multiple rows and multiple columns of pixel circuits at the KxN +1 frame picture display time, and controlling and adjusting the duty ratio of a gate driving signal output by the gate driving circuit to be a preset duty ratio;
controlling the polarity inversion of the data voltage accessed by the pixel circuits in multiple rows and multiple columns at the KxN +2 frame picture display time;
k is an integer greater than 2 and N is an integer greater than 1.
2. The method according to claim 1, wherein the partial column of pixel circuits are a 4a-1 th column of pixel circuits and a 4a th column of pixel circuits; or the partial column pixel circuits are the 4a-2 th column pixel circuit and the 4a-3 th column pixel circuit; a is a positive integer.
3. The data voltage polarity control method of claim 1, wherein the partial column pixel circuits are odd column pixel circuits; or, the partial column pixel circuit is an even column pixel circuit.
4. The data voltage polarity control method of claim 1, wherein the display panel is a 75-inch 8K display panel, the predetermined duty ratio is 1/4; alternatively, the first and second electrodes may be,
the display panel is a 65-inch 8K display panel, and the predetermined duty cycle is 0.35.
5. The data voltage polarity control method of any one of claims 1 to 4, wherein the data voltage polarity control method comprises:
and in other frame picture time except the KxN frame picture display time, the KxN +1 frame picture display time and the KxN +2 frame picture display time included in the display phase, the polarity of the data voltage accessed by the multi-row and multi-column pixel circuits is reversed.
6. A data voltage polarity control module is applied to a display panel, the display panel comprises a grid drive circuit and a plurality of rows and columns of pixel circuits, and is characterized in that the data voltage polarity control module comprises a grid drive control unit and a data voltage polarity control unit, wherein,
the grid drive control unit is used for controlling the grid drive circuit not to output a grid drive signal at the KxN frame picture display time and controlling and adjusting the duty ratio of the grid drive signal output by the grid drive circuit to be a preset duty ratio at the KxN +1 frame picture display time;
the data voltage polarity control unit is used for controlling polarity inversion of data voltages accessed by a part of pixel circuits in the rows and columns of pixel circuits at the KxN frame picture display time, controlling polarity inversion of data voltages accessed by other pixel circuits except the part of pixel circuits in the rows and columns of pixel circuits at the KxN +1 frame picture display time, and controlling polarity inversion of the data voltages accessed by the rows and columns of pixel circuits at the KxN +2 frame picture display time;
k is an integer greater than 2 and N is an integer greater than 1.
7. The data voltage polarity control module of claim 6, wherein the partial column pixel circuits are a 4a-1 th column pixel circuit and a 4a th column pixel circuit; or the partial column pixel circuits are the 4a-2 th column pixel circuit and the 4a-3 th column pixel circuit; a is a positive integer.
8. The data voltage polarity control module of claim 6, wherein the partial column pixel circuits are odd column pixel circuits; or, the partial column pixel circuit is an even column pixel circuit.
9. The data voltage polarity control module of claim 6, wherein the display panel is a 75-inch 8K display panel, the predetermined duty ratio is 1/4; alternatively, the first and second electrodes may be,
the display panel is a 65-inch 8K display panel, and the predetermined duty cycle is 0.35.
10. A display device comprising the data voltage polarity control module according to claim 9.
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| CN202010534988.5A CN111564134B (en) | 2020-06-12 | 2020-06-12 | Data voltage polarity control method, module and display device |
| PCT/CN2021/099366 WO2021249479A1 (en) | 2020-06-12 | 2021-06-10 | Data voltage polarity control method and device, and display device |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112037729A (en) * | 2020-09-23 | 2020-12-04 | 京东方科技集团股份有限公司 | Display panel control method and device, display panel and electronic equipment |
| CN113241032A (en) * | 2021-05-10 | 2021-08-10 | 深圳市华星光电半导体显示技术有限公司 | Display panel driving method, display panel and liquid crystal display device |
| WO2021249479A1 (en) * | 2020-06-12 | 2021-12-16 | 京东方科技集团股份有限公司 | Data voltage polarity control method and device, and display device |
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| WO2021249479A1 (en) | 2021-12-16 |
| CN111564134B (en) | 2023-06-20 |
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