CN111554584A - Method for packaging chip on double sides of substrate and structure of chip packaged on double sides of substrate - Google Patents
Method for packaging chip on double sides of substrate and structure of chip packaged on double sides of substrate Download PDFInfo
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- CN111554584A CN111554584A CN202010414108.0A CN202010414108A CN111554584A CN 111554584 A CN111554584 A CN 111554584A CN 202010414108 A CN202010414108 A CN 202010414108A CN 111554584 A CN111554584 A CN 111554584A
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- 239000004033 plastic Substances 0.000 claims description 61
- 229920003023 plastic Polymers 0.000 claims description 61
- 229910000679 solder Inorganic materials 0.000 claims description 34
- 238000000465 moulding Methods 0.000 claims description 12
- 150000001875 compounds Chemical class 0.000 claims description 11
- 238000003466 welding Methods 0.000 claims description 10
- 239000005022 packaging material Substances 0.000 claims description 5
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- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 3
- 238000002347 injection Methods 0.000 description 3
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/54—Providing fillings in containers, e.g. gas fillings
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
- H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
The invention provides a method for packaging a chip on two sides of a substrate and a structure for packaging the chip on two sides of the substrate, and relates to the technical field of chip packaging. According to the method for packaging the chip on the two sides of the substrate, the groove is formed on one side of the substrate, the first chip is attached in the groove, and the first chip is packaged in the groove in a printing and filling mode, so that the traditional pressure injection molding mode is replaced, the defects of glue overflow, wire arc punching and blocking of a mold and the like in the traditional manufacturing process are overcome, and the product packaging quality is improved. The structure of the substrate double-sided packaging chip is manufactured by adopting the method for packaging the substrate double-sided packaging chip, and the packaging quality is better.
Description
Technical Field
The invention relates to the technical field of chip packaging, in particular to a method for packaging a chip on two sides of a substrate and a structure for packaging the chip on two sides of the substrate.
Background
In the traditional double-sided packaging process, chips on two sides of a substrate are packaged by adopting a pressure injection molding mode on two side surfaces of the substrate. In the traditional pressure injection molding mode, if the height of the packaging body is different, molds with different sizes need to be purchased for pressure injection molding, and the flexibility is not high. In addition, the pressure injection molding method is adopted, so that the defects of glue overflow, line arc flash, mold blockage by glue and the like are easily caused in the process, and the packaging quality is seriously influenced.
Disclosure of Invention
The invention provides a method for packaging chips on two sides of a substrate, which can overcome the defects of glue overflow, line arc punching, mold blocking and the like in the traditional process and is beneficial to improving the packaging quality of products.
The invention also aims to provide a structure of a substrate double-side packaged chip, which can improve the packaging quality of products and reduce the process cost.
Embodiments of the invention may be implemented as follows:
in a first aspect, an embodiment of the present invention provides a method for double-sided packaging of a chip on a substrate, including:
providing a substrate: a groove and a welding pad are arranged on the surface of one side of the substrate, and the welding pad is arranged outside the groove;
mounting a first chip: the first chip is attached in the groove;
plastically packaging the first chip: forming a first plastic package body in the groove by adopting a printing filling mode so as to package the first chip;
mounting a second chip: mounting a second chip on one surface of the substrate, which is far away from the groove;
plastically packaging the second chip: and forming a second plastic package body on one surface of the substrate departing from the groove so as to package the second chip.
In an optional embodiment, the step of plastically packaging the first chip further includes:
and printing liquid plastic packaging material by using a steel mesh, filling the plastic packaging material into the groove, and performing reflux baking to form the first plastic packaging body.
In an alternative embodiment, the step of forming the first plastic package body further includes: the surface of the first plastic package body is flush with the notch of the groove.
In an optional embodiment, after the step of providing a substrate, the method further includes:
and performing primary ball planting on the welding pad.
In an alternative embodiment, the step of providing a substrate further comprises:
and forming the groove on one side surface of the substrate by adopting an etching process or a laser grooving mode.
In an optional embodiment, the step of plastically packaging the first chip further includes:
and sticking the first chip by adopting a normal installation mode, and routing the first chip and the substrate so as to electrically connect the first chip and the substrate.
In a second aspect, an embodiment of the present invention provides a structure of a substrate double-sided package chip, including a substrate, a first chip and a second chip, where a groove is formed on the substrate, the first chip is installed in the groove, and the second chip is installed on a side of the substrate away from the groove;
a welding pad is arranged on one side of the substrate, which is provided with the groove, and the welding pad is used for ball planting;
a first plastic package body is arranged in the groove and used for packaging the first chip; and a second plastic package body is arranged on one side of the substrate, which deviates from the groove, and is used for packaging a second chip.
In an alternative embodiment, the first plastic package body is formed in the groove by a printing filling mode.
In an optional embodiment, a solder ball is disposed on the pad.
In an alternative embodiment, the height of the first plastic package body is equal to the depth of the groove.
The method for packaging the chip on the two sides of the substrate and the structure for packaging the chip on the two sides of the substrate provided by the embodiment of the invention have the beneficial effects that:
according to the method for packaging the chip on the two sides of the substrate, provided by the embodiment of the invention, the groove is formed on the surface of one side of the substrate, the first chip is attached in the groove, and the first chip is packaged in the groove in a printing filling mode. The packaging process adopts a printing and filling mode to replace a pressure injection molding mode in the traditional process, can overcome the defects of glue overflow, line arc punching, mold blocking by glue and the like in the traditional process, and is favorable for improving the packaging quality of products. Meanwhile, a printing filling mode is adopted, the limitation of the height of a packaged product is avoided, different dies are not needed, the flexibility is higher, and the process cost is lower.
The structure of the substrate double-sided packaging chip provided by the embodiment of the invention is manufactured by adopting the method for packaging the substrate double-sided packaging chip, can overcome the defects of glue overflow, line arc punching and blocking of a die and the like in the traditional manufacturing process, and has better product packaging quality.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the embodiments will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present invention and therefore should not be considered as limiting the scope, and for those skilled in the art, other related drawings can be obtained according to the drawings without inventive efforts.
FIG. 1 is a schematic diagram of a double-sided package structure in the prior art;
fig. 2 is a schematic structural diagram of a substrate double-sided package chip according to an embodiment of the invention;
FIG. 3 is a flowchart illustrating a method for double-sided packaging of chips on a substrate according to an embodiment of the invention;
fig. 4 is a schematic structural diagram of a substrate in a structure of a substrate double-sided package chip according to an embodiment of the present invention;
fig. 5 is a schematic structural diagram illustrating a second chip mounted on a substrate in a method for double-sided packaging of chips on a substrate according to an embodiment of the present invention;
fig. 6 is a schematic structural diagram illustrating plastic encapsulation of a second chip in the method for double-sided packaging of chips on a substrate according to the embodiment of the present invention;
fig. 7 is a schematic structural diagram illustrating a first chip mounted on a substrate in a method for double-sided packaging of chips on a substrate according to an embodiment of the present invention;
fig. 8 is a schematic structural diagram illustrating plastic encapsulation of a first chip in the method for double-sided packaging of a chip on a substrate according to the embodiment of the present invention;
fig. 9 is a schematic structural diagram of ball mounting on a substrate in a method for double-sided packaging of a chip on a substrate according to an embodiment of the present invention.
Icon: 100-structure of double-sided packaging chip of substrate; 10-a circuit board; 11-a soldering pad; 12-new solder balls; 20-chip one; 21-plastic package body one; 30-chip two; 31-plastic package body two; 110-a substrate; 101-a groove; 111-line; 113-a bonding pad; 115-solder balls; 120-a first chip; 121-gold wire; 125-a first plastic package body; 130-a second chip; 131-metal solder balls; 135-second plastic package body.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. The components of embodiments of the present invention generally described and illustrated in the figures herein may be arranged and designed in a wide variety of different configurations.
Thus, the following detailed description of the embodiments of the present invention, presented in the figures, is not intended to limit the scope of the invention, as claimed, but is merely representative of selected embodiments of the invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures.
In the description of the present invention, it should be noted that if the terms "upper", "lower", "inside", "outside", etc. indicate an orientation or a positional relationship based on that shown in the drawings or that the product of the present invention is used as it is, this is only for convenience of description and simplification of the description, and it does not indicate or imply that the device or the element referred to must have a specific orientation, be constructed in a specific orientation, and be operated, and thus should not be construed as limiting the present invention.
Furthermore, the appearances of the terms "first," "second," and the like, if any, are used solely to distinguish one from another and are not to be construed as indicating or implying relative importance.
It should be noted that the features of the embodiments of the present invention may be combined with each other without conflict.
Fig. 1 is a schematic diagram of a dual-sided package structure in the prior art, and fig. 1 is shown.
With the rapid development of the semiconductor industry, electronic products are miniaturized with higher density, more and more functions and smaller product size, so that the double-sided structure of the double-sided chip package is widely applied to the semiconductor industry. The double-sided package can package chips with different functions on both sides (front and back sides) of the circuit board 10, has the advantages of high-density integration, small size of packaged products and excellent product performance, and is mainly applied to miniaturized and thinned communication terminal products.
In the conventional double-sided chip packaging process, a first chip 20 and a second chip 30 are respectively packaged on two sides of a circuit board 10, and a first plastic package body 21 and a second plastic package body 31 are respectively formed on two sides of the circuit board 10 mostly by adopting a pressure injection molding mode. Specifically, first ball mounting is performed on the back-side bonding pad 11 of the circuit board 10, that is, the low-temperature solder balls are printed on the back-side bonding pad 11 of the circuit board 10, then chip mounting/wire bonding is performed, and then the front side and the back side of the circuit board 10 are respectively encapsulated by pressure injection molding to form a first plastic package body 21 and a second plastic package body 31. Finally, grooving is carried out on the second plastic package body 31 through laser so as to enable the low-temperature solder balls on the back of the circuit board 10 to leak out, the solder balls are planted on the exposed low-temperature solder balls again, namely, the solder balls are planted for the second time, and the low-temperature solder balls are fused at high temperature to form new solder balls 12, namely, the ball planting for the second time is adopted in the traditional process.
In the prior art, a pressure injection molding mode is adopted, mold clamping pressure is high, technological parameters such as mold flow and pressure are difficult to control, defects such as glue overflow, line arc punching and bay, mold blockage caused by glue and the like are easy to occur in a technological process, and packaging quality is seriously influenced. In addition, the traditional process adopts a twice ball planting technology, and has the defects of generating holes, solder ball hidden cracks and the like when the solder balls at high and low temperatures are melted. The laser is utilized to dig grooves on the plastic package body, and due to the poor consistency of the grooves at multiple positions, the heights and/or sizes of subsequent ball planting are easily inconsistent, so that the upper board test of a product fails and the yield loss is caused.
In order to overcome the defects of the prior art, the application provides a method for packaging a chip on two sides of a substrate, which is beneficial to improving the packaging process, improving the packaging quality and reducing the packaging cost.
Fig. 2 is a schematic view of a structure 100 of a substrate double-sided packaged chip according to an embodiment of the present invention, and fig. 3 is a schematic view of a flow chart of a method for substrate double-sided packaging a chip according to an embodiment of the present invention, please refer to fig. 2 and fig. 3.
The embodiment provides a structure 100 of a substrate double-sided packaged chip, which includes a substrate 110, a first chip 120 and a second chip 130, wherein a groove 101 (see fig. 4) is formed in the substrate 110, the first chip 120 is installed in the groove 101, and the second chip 130 is installed on a side of the substrate 110 away from the groove 101. The substrate 110 is further provided with a bonding pad 113 at one side thereof provided with the groove 101, and the bonding pad 113 is used for ball mounting. A first plastic package body 125 is arranged in the groove 101 and used for packaging the first chip 120; one side of the substrate 110 departing from the groove 101 is provided with a second plastic package body 135 for packaging a second chip 130, so that the chips are packaged on the front side and the back side of the substrate 110, the product structure is more compact, and the integration level is high.
The recess 101 may be opened at the front or back of the substrate 110. In this embodiment, the recess 101 is formed on the back surface of the substrate 110, and the first chip 120 is attached to the bottom of the recess 101 and electrically connected to the circuit 111 on the substrate 110. The first plastic package body 125 is formed in the groove 101 by printing and filling. Since the substrate 110 is provided with the groove 101, the molding compound is filled into the groove 101 of the substrate 110, and the first chip 120, the substrate 110 and the circuit 111 are protected by reflow baking, thereby completing the manufacture of the first molding compound 125. The height of the first plastic package body 125 is determined according to the depth of the groove 101, and optionally, the height of the first plastic package body 125 is equal to the depth of the groove 101, so that the first plastic package body 125 has a more compact and firm structure and a smaller volume. The printing and filling mode is adopted to replace the traditional pressure injection molding mode, so that the defects of glue overflow, line arc punching, mold blocking by glue and the like can be overcome, and the product packaging quality is favorably improved. And, the printing filling mode is not influenced by product size, need not to change different moulds, need not to use the board of moulding plastics, greatly reduced encapsulation cost.
The second chip 130 is disposed on a surface of the substrate 110 away from the recess 101, in this embodiment, the second chip 130 is disposed on the front surface of the substrate 110, and the second chip 130 is electrically connected to the circuit 111 of the substrate 110. The second molding compound 135 is formed on the front surface of the substrate 110 by pressure injection molding to protect the second chip 130, the substrate 110 and the circuit 111. It should be noted that the first chip 120 and the second chip 130 are electrically connected to the substrate 110 respectively, the electrical connection includes but is not limited to wire bonding or metal ball bonding, and the wire bonding includes, for example, gold wire 121, copper wire, alloy wire, and the like, and is not limited in this respect.
The method for double-sided packaging of the chip on the substrate provided by the embodiment specifically comprises the following steps:
fig. 4 is a schematic structural diagram of a substrate 110 in a substrate double-sided package chip structure 100 according to an embodiment of the present invention, please refer to fig. 4.
S1: a substrate 110 is provided. The substrate 110 may be fabricated at a substrate 110 factory, a groove 101 is formed on one side surface of the substrate 110, and the groove 101 may be disposed by laser grooving or etching grooving, which is not particularly limited herein. Alternatively, etching and grooving are performed on the surface of the substrate 110, a protective film is used for protecting the substrate from being damaged at places where the grooving is not needed, and finally the protective film is removed to form the groove 101. The circuit 111 is arranged on the substrate 110, and a bonding pad 113 is arranged on one side of the substrate 110, on which the groove 101 is formed, and the bonding pad 113 is electrically connected with the circuit 111. It should be noted that, according to practical situations, the number of the pads 113 may be one or more, and a plurality of pads 113 are disposed on the periphery of the groove 101.
Fig. 5 is a schematic structural diagram of mounting a second chip 130 on a substrate 110 in a method for double-sided packaging of chips on a substrate according to an embodiment of the invention, please refer to fig. 5.
S2: the second chip 130 is mounted. The second chip 130 is mounted on the side of the substrate 110 away from the groove 101, the second chip 130 is mounted in a flip-chip manner, a metal solder ball 131 is disposed on the second chip 130, and the second chip 130 is soldered to the substrate 110 through the metal solder ball 131, so that the substrate 110 and the second chip 130 are electrically connected. Specifically, the second chip 130 and the substrate 110 are connected together after being cured by reflow.
Fig. 6 is a schematic structural diagram of plastic packaging the second chip 130 in the method for double-sided packaging the chip on the substrate 110 according to the embodiment of the invention, and please refer to fig. 6.
S3: the second chip 130 is plastically packaged. And forming a second plastic package body 135 on the surface of the substrate 110, which is far away from the groove 101, by using a plastic package material in a pressure injection molding manner, wherein the second plastic package body 135 protects the connected chip, the substrate 110 and the circuit 111, and thus the package of the second chip 130 is completed.
Fig. 7 is a schematic structural diagram of mounting a first chip 120 on a substrate 110 in a method for double-sided packaging of chips on the substrate 110 according to an embodiment of the present invention, please refer to fig. 7.
S4: the first chip 120 is mounted. The first chip 120 is attached to the groove 101 of the substrate 110, the substrate 110 is placed by turning 180 degrees, the notch of the groove 101 faces upwards, and the first chip 120 is attached to the bottom of the groove 101. In this embodiment, the first chip 120 is mounted on the substrate 110, and the first chip 120 is electrically connected to the substrate 110 by wire bonding. Specifically, taking the gold wire 121 as an example, one end of the gold wire 121 is soldered to the circuit 111 on the substrate 110, the other end is soldered to the chip, and the circuit 111 on the substrate 110 is connected to the pad 113. Of course, the bonding wire 121 may be a copper wire or an alloy wire, and the like, as long as the substrate 110 and the first chip 120 can be electrically connected, and is not particularly limited herein.
Fig. 8 is a schematic structural diagram of plastic packaging of the first chip 120 in the method for double-sided packaging of chips on a substrate according to the embodiment of the present invention, and please refer to fig. 8.
S5: the first chip 120 is plastic-encapsulated. By using a printing and filling manner, a liquid molding compound is printed by using a steel mesh, the molding compound is filled into the groove 101 of the substrate 110, and then reflow baking is performed to protect the connected chip, the substrate 110 and the circuit 111, so as to form a first molding compound 125, thereby completing the packaging of the first chip 120. It is easily understood that the height of the first plastic package body 125 is formed to be equal to the depth of the groove 101, i.e., the surface of the first plastic package body 125 is flush with the notch of the groove 101. Since the groove 101 is formed in the substrate 110, the arrangement of the groove 101 provides a condition for forming the first plastic package body 125 by a printing and filling manner, and the depth of the groove 101, i.e., the height difference formed by the groove 101, can satisfy the height required for replacing the plastic package body formed by using a mold in the conventional pressure injection molding. In this embodiment, a steel mesh printing liquid plastic packaging material filling manner is adopted to replace a traditional pressure injection molding encapsulation manner, so that the defects of glue overflow, line arc flash, mold blockage caused by difficult control of process parameters such as mold flow and pressure, and the like due to large injection pressure and mold clamping pressure in pressure injection molding are avoided. Meanwhile, the printing filling mode is adopted in the embodiment, the limitation of the height of the plastic package body is avoided, the defect that different plastic package body height sizes need to purchase different injection molds in the traditional pressure injection molding is avoided, and the high cost of purchasing injection molding machines and molds is saved.
Fig. 9 is a schematic structural diagram of ball mounting on a substrate 110 in a method for double-sided packaging a chip on a substrate according to an embodiment of the invention, please refer to fig. 9.
S6: the ball is implanted on the pad 113. Optionally, a solder ball 115 is implanted on one side of the substrate 110 where the recess 101 is opened, and the solder ball 115 is disposed on the pad 113. The solder ball 115 is formed stably by reflow after the solder ball 115 is implanted on the pad 113, and the solder ball 115 is used as a connection terminal of a packaged product for electrical connection with other electronic devices. It should be understood that the solder balls 115 are used in this embodiment, and in other alternative embodiments, other metal balls may be used, which is not limited herein.
S7: and printing. The laser is used to imprint the required characters on the surface of the first plastic package body 125 and/or the surface of the second plastic package body 135.
S8: and cutting and packaging. And cutting the plastic-sealed product into single pieces by using a cutting knife on a cutting machine table, and packaging and outputting the cut single pieces to finish the manufacturing process of the product.
It should be noted that, in an actual production process, the sequence of some steps may be appropriately adjusted, for example, the first chip 120 may be plastically packaged first, and then the second chip 130 may be plastically packaged. For another example, the ball may be first mounted on the bonding pad 113, and then the first chip 120 is subjected to plastic package; alternatively, the first chip 120 is first subjected to plastic molding, and then the solder pads 113 are subjected to ball bonding, which is not limited herein. In addition, in the embodiment, the first chip 120 is electrically connected to the substrate 110 by wire bonding, and the second chip 130 is electrically connected to the substrate 110 by using the metal solder balls 131. In other alternative embodiments, the first chip 120 may be electrically connected to the substrate 110 by using solder balls, and the second chip 130 is electrically connected to the substrate 110 by wire bonding; or, the first chip 120 is electrically connected to the substrate 110 by using solder balls, and the second chip 130 is electrically connected to the substrate 110 by using metal solder balls 131; alternatively, the first chip 120 is electrically connected to the substrate 110 by wire bonding, and the second chip 130 is electrically connected to the substrate 110 by wire bonding, which is not limited herein.
In summary, the method and structure for double-sided packaging of chips on a substrate provided by the present embodiment have the following advantages:
the first chip 120 is mounted in the groove 101 by forming the groove 101 on one side surface of the substrate 110, and the first molding compound 125 is formed in the groove 101 by printing and filling, so as to protect the first chip 120, the substrate 110 and the circuit 111. The depth of the groove 101 is equal to the height of the first plastic package body 125, and the depth of the groove 101 can satisfy the requirement of replacing the height of the plastic package body formed by using a mold required by the traditional pressure injection molding. The first molding compound 125 is formed by printing and filling, and the molding compound height is determined according to the height of the groove 101 of the etched substrate 110. Compared with the traditional pressure injection molding, the printing and filling mode can avoid the characteristics of large mold closing pressure, difficult control of process parameters and the like in the pressure injection molding process, and avoid the defects of glue overflow, line arc flash, mold blockage by glue and the like caused by pressure injection molding. Meanwhile, the printing and filling mode is not limited by the height of the plastic package body, different injection molds are prevented from being replaced due to different sizes of the plastic package body, and high cost of an injection molding machine table and a mold is saved.
Secondly, in this embodiment, the solder pads 113 are disposed on the surface of the substrate 110 on the side where the groove 101 is formed, the solder pads 113 and the groove 101 are disposed at intervals, and the first chip 120 is plastically encapsulated in the groove 101 without affecting the solder pads 113. It is only necessary to plant the ball on the bonding pad 113 once. Compared with the traditional process in which the ball mounting technology is adopted twice, the process cycle is greatly shortened, and the packaging efficiency is improved. Meanwhile, the defects of cavities generated when the high-temperature and low-temperature solder balls 115 are melted, hidden cracks of the solder balls 115 and the like caused by twice ball planting in the traditional process can be avoided, and the defects of inconsistent height and size of subsequent ball planting caused by the fact that grooves are dug at multiple positions on the plastic package body and the consistency of the grooves is poor can be avoided, so that the packaging quality and the yield are improved.
The above description is only for the specific embodiment of the present invention, but the scope of the present invention is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present invention are included in the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the appended claims.
Claims (10)
1. A method for double-sided packaging of chips on a substrate is characterized by comprising the following steps:
providing a substrate: a groove and a welding pad are arranged on the surface of one side of the substrate, and the welding pad is arranged outside the groove;
mounting a first chip: the first chip is attached in the groove;
plastically packaging the first chip: forming a first plastic package body in the groove by adopting a printing filling mode so as to package the first chip;
mounting a second chip: mounting a second chip on one surface of the substrate, which is far away from the groove;
plastically packaging the second chip: and forming a second plastic package body on one surface of the substrate departing from the groove so as to package the second chip.
2. The method for double-sided packaging of chips on a substrate according to claim 1, wherein the step of plastically packaging the first chip further comprises:
and printing liquid plastic packaging material by using a steel mesh, filling the plastic packaging material into the groove, and performing reflux baking to form the first plastic packaging body.
3. The method for double-sided packaging of chips on a substrate according to claim 2, wherein the step of forming the first plastic package body further comprises: the surface of the first plastic package body is flush with the notch of the groove.
4. The method of claim 1, wherein the step of providing a substrate is followed by the step of double-sided packaging the chip with the substrate further comprising:
and performing primary ball planting on the welding pad.
5. The method of claim 1, wherein the step of providing a substrate further comprises:
and forming the groove on one side surface of the substrate by adopting an etching process or a laser grooving mode.
6. The method for double-sided packaging of chips on a substrate according to claim 1, wherein the step of plastically packaging the first chip further comprises:
and sticking the first chip by adopting a normal installation mode, and routing the first chip and the substrate so as to electrically connect the first chip and the substrate.
7. A structure of a substrate double-sided packaging chip is characterized by comprising a substrate, a first chip and a second chip, wherein a groove is formed in the substrate, the first chip is installed in the groove, and the second chip is installed on one side, away from the groove, of the substrate;
a welding pad is arranged on one side of the substrate, which is provided with the groove, and the welding pad is used for ball planting;
a first plastic package body is arranged in the groove and used for packaging the first chip; and a second plastic package body is arranged on one side of the substrate, which deviates from the groove, and is used for packaging a second chip.
8. The substrate double-sided packaging chip structure according to claim 7, wherein the first plastic package body is formed in the groove by printing and filling.
9. The substrate double-sided packaging chip structure according to claim 7, wherein solder balls are disposed on the pads.
10. The substrate double-sided packaging chip structure according to claim 7, wherein the height of the first molding compound is equal to the depth of the groove.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010414108.0A CN111554584A (en) | 2020-05-15 | 2020-05-15 | Method for packaging chip on double sides of substrate and structure of chip packaged on double sides of substrate |
| CN202010912533.2A CN111816577A (en) | 2020-05-15 | 2020-09-03 | Method for packaging chip on double sides of substrate and structure of chip packaged on double sides of substrate |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202010414108.0A CN111554584A (en) | 2020-05-15 | 2020-05-15 | Method for packaging chip on double sides of substrate and structure of chip packaged on double sides of substrate |
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| CN111554584A true CN111554584A (en) | 2020-08-18 |
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| CN202010912533.2A Pending CN111816577A (en) | 2020-05-15 | 2020-09-03 | Method for packaging chip on double sides of substrate and structure of chip packaged on double sides of substrate |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN113675093A (en) * | 2021-07-14 | 2021-11-19 | 复旦大学 | Packaging design and preparation method of double-sided plastic-packaged heat dissipation structure |
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| CN113301486B (en) * | 2021-06-17 | 2022-04-29 | 甬矽电子(宁波)股份有限公司 | Double-silicon-microphone packaging structure and preparation method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| JPH1093013A (en) * | 1996-09-17 | 1998-04-10 | Seiko Epson Corp | Semiconductor device |
| KR100782774B1 (en) * | 2006-05-25 | 2007-12-05 | 삼성전기주식회사 | System in package module |
| CN103311214A (en) * | 2013-05-14 | 2013-09-18 | 中国科学院微电子研究所 | Base plate for stacked packaging |
| CN109801846A (en) * | 2014-01-26 | 2019-05-24 | 清华大学 | A kind of encapsulating structure and packaging method |
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2020
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113675093A (en) * | 2021-07-14 | 2021-11-19 | 复旦大学 | Packaging design and preparation method of double-sided plastic-packaged heat dissipation structure |
| CN113675093B (en) * | 2021-07-14 | 2024-05-24 | 复旦大学 | Packaging design and preparation method of double-sided plastic packaging heat dissipation structure |
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